1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM/SEC 4.x driver backend
4 * Private/internal definitions between modules
6 * Copyright 2008-2011 Freescale Semiconductor, Inc.
14 #include <crypto/engine.h>
16 /* Currently comes from Kconfig param as a ^2 (driver-required) */
17 #define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE)
20 * Maximum size for crypto-engine software queue based on Job Ring
21 * size (JOBR_DEPTH) and a THRESHOLD (reserved for the non-crypto-API
22 * requests that are not passed through crypto-engine)
25 #define CRYPTO_ENGINE_MAX_QLEN (JOBR_DEPTH - THRESHOLD)
27 /* Kconfig params for interrupt coalescing if selected (else zero) */
28 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_INTC
29 #define JOBR_INTC JRCFG_ICEN
30 #define JOBR_INTC_TIME_THLD CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD
31 #define JOBR_INTC_COUNT_THLD CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD
34 #define JOBR_INTC_TIME_THLD 0
35 #define JOBR_INTC_COUNT_THLD 0
39 * Storage for tracking each in-process entry moving across a ring
40 * Each entry on an output ring needs one of these
42 struct caam_jrentry_info {
43 void (*callbk)(struct device *dev, u32 *desc, u32 status, void *arg);
44 void *cbkarg; /* Argument per ring entry */
45 u32 *desc_addr_virt; /* Stored virt addr for postprocessing */
46 dma_addr_t desc_addr_dma; /* Stored bus addr for done matching */
47 u32 desc_size; /* Stored size for postprocessing, header derived */
50 /* Private sub-storage for a single JobR */
51 struct caam_drv_private_jr {
52 struct list_head list_node; /* Job Ring device list */
55 struct caam_job_ring __iomem *rregs; /* JobR's register space */
56 struct tasklet_struct irqtask;
57 int irq; /* One per queue */
60 /* Number of scatterlist crypt transforms active on the JobR */
61 atomic_t tfm_count ____cacheline_aligned;
64 struct caam_jrentry_info *entinfo; /* Alloc'ed 1 per ring entry */
65 spinlock_t inplock ____cacheline_aligned; /* Input ring index lock */
66 u32 inpring_avail; /* Number of free entries in input ring */
67 int head; /* entinfo (s/w ring) head index */
68 void *inpring; /* Base of input ring, alloc
70 int out_ring_read_index; /* Output index "tail" */
71 int tail; /* entinfo (s/w ring) tail index */
72 void *outring; /* Base of output ring, DMA-safe */
73 struct crypto_engine *engine;
77 * Driver-private storage for a single CAAM block instance
79 struct caam_drv_private {
80 /* Physical-presence section */
81 struct caam_ctrl __iomem *ctrl; /* controller region */
82 struct caam_deco __iomem *deco; /* DECO/CCB views */
83 struct caam_assurance __iomem *assure;
84 struct caam_queue_if __iomem *qi; /* QI control region */
85 struct caam_job_ring __iomem *jr[4]; /* JobR's register space */
87 struct iommu_domain *domain;
90 * Detected geometry block. Filled in from device tree if powerpc,
91 * or from register-based version detection code
93 u8 total_jobrs; /* Total Job Rings in device */
94 u8 qi_present; /* Nonzero if QI present in device */
95 u8 blob_present; /* Nonzero if BLOB support present in device */
96 u8 mc_en; /* Nonzero if MC f/w is active */
97 int secvio_irq; /* Security violation interrupt number */
98 int virt_en; /* Virtualization enabled in CAAM */
99 int era; /* CAAM Era (internal HW revision) */
101 #define RNG4_MAX_HANDLES 2
103 u32 rng4_sh_init; /* This bitmap shows which of the State
104 Handles of the RNG4 block are initialized
107 struct clk_bulk_data *clks;
110 * debugfs entries for developer view into driver/device
111 * variables at runtime.
113 #ifdef CONFIG_DEBUG_FS
114 struct dentry *ctl; /* controller dir */
115 struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap;
119 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API
121 int caam_algapi_init(struct device *dev);
122 void caam_algapi_exit(void);
126 static inline int caam_algapi_init(struct device *dev)
131 static inline void caam_algapi_exit(void)
135 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API */
137 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API
139 int caam_algapi_hash_init(struct device *dev);
140 void caam_algapi_hash_exit(void);
144 static inline int caam_algapi_hash_init(struct device *dev)
149 static inline void caam_algapi_hash_exit(void)
153 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API */
155 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API
157 int caam_pkc_init(struct device *dev);
158 void caam_pkc_exit(void);
162 static inline int caam_pkc_init(struct device *dev)
167 static inline void caam_pkc_exit(void)
171 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API */
173 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API
175 int caam_rng_init(struct device *dev);
176 void caam_rng_exit(struct device *dev);
180 static inline int caam_rng_init(struct device *dev)
185 static inline void caam_rng_exit(struct device *dev) {}
187 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API */
189 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API
191 int caam_prng_register(struct device *dev);
192 void caam_prng_unregister(void *data);
196 static inline int caam_prng_register(struct device *dev)
201 static inline void caam_prng_unregister(void *data) {}
202 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API */
204 #ifdef CONFIG_CAAM_QI
206 int caam_qi_algapi_init(struct device *dev);
207 void caam_qi_algapi_exit(void);
211 static inline int caam_qi_algapi_init(struct device *dev)
216 static inline void caam_qi_algapi_exit(void)
220 #endif /* CONFIG_CAAM_QI */
222 static inline u64 caam_get_dma_mask(struct device *dev)
224 struct device_node *nprop = dev->of_node;
226 if (caam_ptr_sz != sizeof(u64))
227 return DMA_BIT_MASK(32);
230 return DMA_BIT_MASK(49);
232 if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring") ||
233 of_device_is_compatible(nprop, "fsl,sec-v5.0"))
234 return DMA_BIT_MASK(40);
236 return DMA_BIT_MASK(36);
240 #endif /* INTERN_H */