GNU Linux-libre 4.4.300-gnu1
[releases.git] / drivers / crypto / caam / ctrl.c
1 /* * CAAM control-plane driver backend
2  * Controller-level driver, kernel property detection, initialization
3  *
4  * Copyright 2008-2012 Freescale Semiconductor, Inc.
5  */
6
7 #include <linux/device.h>
8 #include <linux/of_address.h>
9 #include <linux/of_irq.h>
10
11 #include "compat.h"
12 #include "regs.h"
13 #include "intern.h"
14 #include "jr.h"
15 #include "desc_constr.h"
16 #include "error.h"
17
18 /*
19  * i.MX targets tend to have clock control subsystems that can
20  * enable/disable clocking to our device.
21  */
22 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
23 static inline struct clk *caam_drv_identify_clk(struct device *dev,
24                                                 char *clk_name)
25 {
26         return devm_clk_get(dev, clk_name);
27 }
28 #else
29 static inline struct clk *caam_drv_identify_clk(struct device *dev,
30                                                 char *clk_name)
31 {
32         return NULL;
33 }
34 #endif
35
36 /*
37  * Descriptor to instantiate RNG State Handle 0 in normal mode and
38  * load the JDKEK, TDKEK and TDSK registers
39  */
40 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
41 {
42         u32 *jump_cmd, op_flags;
43
44         init_job_desc(desc, 0);
45
46         op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
47                         (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
48
49         /* INIT RNG in non-test mode */
50         append_operation(desc, op_flags);
51
52         if (!handle && do_sk) {
53                 /*
54                  * For SH0, Secure Keys must be generated as well
55                  */
56
57                 /* wait for done */
58                 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
59                 set_jump_tgt_here(desc, jump_cmd);
60
61                 /*
62                  * load 1 to clear written reg:
63                  * resets the done interrrupt and returns the RNG to idle.
64                  */
65                 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
66
67                 /* Initialize State Handle  */
68                 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
69                                  OP_ALG_AAI_RNG4_SK);
70         }
71
72         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
73 }
74
75 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
76 static void build_deinstantiation_desc(u32 *desc, int handle)
77 {
78         init_job_desc(desc, 0);
79
80         /* Uninstantiate State Handle 0 */
81         append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
82                          (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
83
84         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
85 }
86
87 /*
88  * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
89  *                        the software (no JR/QI used).
90  * @ctrldev - pointer to device
91  * @status - descriptor status, after being run
92  *
93  * Return: - 0 if no error occurred
94  *         - -ENODEV if the DECO couldn't be acquired
95  *         - -EAGAIN if an error occurred while executing the descriptor
96  */
97 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
98                                         u32 *status)
99 {
100         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
101         struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
102         struct caam_deco __iomem *deco = ctrlpriv->deco;
103         unsigned int timeout = 100000;
104         u32 deco_dbg_reg, flags;
105         int i;
106
107
108         if (ctrlpriv->virt_en == 1) {
109                 setbits32(&ctrl->deco_rsr, DECORSR_JR0);
110
111                 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
112                        --timeout)
113                         cpu_relax();
114
115                 timeout = 100000;
116         }
117
118         setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
119
120         while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
121                                                                  --timeout)
122                 cpu_relax();
123
124         if (!timeout) {
125                 dev_err(ctrldev, "failed to acquire DECO 0\n");
126                 clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
127                 return -ENODEV;
128         }
129
130         for (i = 0; i < desc_len(desc); i++)
131                 wr_reg32(&deco->descbuf[i], *(desc + i));
132
133         flags = DECO_JQCR_WHL;
134         /*
135          * If the descriptor length is longer than 4 words, then the
136          * FOUR bit in JRCTRL register must be set.
137          */
138         if (desc_len(desc) >= 4)
139                 flags |= DECO_JQCR_FOUR;
140
141         /* Instruct the DECO to execute it */
142         setbits32(&deco->jr_ctl_hi, flags);
143
144         timeout = 10000000;
145         do {
146                 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
147                 /*
148                  * If an error occured in the descriptor, then
149                  * the DECO status field will be set to 0x0D
150                  */
151                 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
152                     DESC_DBG_DECO_STAT_HOST_ERR)
153                         break;
154                 cpu_relax();
155         } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
156
157         *status = rd_reg32(&deco->op_status_hi) &
158                   DECO_OP_STATUS_HI_ERR_MASK;
159
160         if (ctrlpriv->virt_en == 1)
161                 clrbits32(&ctrl->deco_rsr, DECORSR_JR0);
162
163         /* Mark the DECO as free */
164         clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
165
166         if (!timeout)
167                 return -EAGAIN;
168
169         return 0;
170 }
171
172 /*
173  * instantiate_rng - builds and executes a descriptor on DECO0,
174  *                   which initializes the RNG block.
175  * @ctrldev - pointer to device
176  * @state_handle_mask - bitmask containing the instantiation status
177  *                      for the RNG4 state handles which exist in
178  *                      the RNG4 block: 1 if it's been instantiated
179  *                      by an external entry, 0 otherwise.
180  * @gen_sk  - generate data to be loaded into the JDKEK, TDKEK and TDSK;
181  *            Caution: this can be done only once; if the keys need to be
182  *            regenerated, a POR is required
183  *
184  * Return: - 0 if no error occurred
185  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
186  *         - -ENODEV if DECO0 couldn't be acquired
187  *         - -EAGAIN if an error occurred when executing the descriptor
188  *            f.i. there was a RNG hardware error due to not "good enough"
189  *            entropy being aquired.
190  */
191 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
192                            int gen_sk)
193 {
194         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
195         struct caam_ctrl __iomem *ctrl;
196         u32 *desc, status = 0, rdsta_val;
197         int ret = 0, sh_idx;
198
199         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
200         desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
201         if (!desc)
202                 return -ENOMEM;
203
204         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
205                 /*
206                  * If the corresponding bit is set, this state handle
207                  * was initialized by somebody else, so it's left alone.
208                  */
209                 if ((1 << sh_idx) & state_handle_mask)
210                         continue;
211
212                 /* Create the descriptor for instantiating RNG State Handle */
213                 build_instantiation_desc(desc, sh_idx, gen_sk);
214
215                 /* Try to run it through DECO0 */
216                 ret = run_descriptor_deco0(ctrldev, desc, &status);
217
218                 /*
219                  * If ret is not 0, or descriptor status is not 0, then
220                  * something went wrong. No need to try the next state
221                  * handle (if available), bail out here.
222                  * Also, if for some reason, the State Handle didn't get
223                  * instantiated although the descriptor has finished
224                  * without any error (HW optimizations for later
225                  * CAAM eras), then try again.
226                  */
227                 if (ret)
228                         break;
229
230                 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
231                 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
232                     !(rdsta_val & (1 << sh_idx))) {
233                         ret = -EAGAIN;
234                         break;
235                 }
236
237                 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
238                 /* Clear the contents before recreating the descriptor */
239                 memset(desc, 0x00, CAAM_CMD_SZ * 7);
240         }
241
242         kfree(desc);
243
244         return ret;
245 }
246
247 /*
248  * deinstantiate_rng - builds and executes a descriptor on DECO0,
249  *                     which deinitializes the RNG block.
250  * @ctrldev - pointer to device
251  * @state_handle_mask - bitmask containing the instantiation status
252  *                      for the RNG4 state handles which exist in
253  *                      the RNG4 block: 1 if it's been instantiated
254  *
255  * Return: - 0 if no error occurred
256  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
257  *         - -ENODEV if DECO0 couldn't be acquired
258  *         - -EAGAIN if an error occurred when executing the descriptor
259  */
260 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
261 {
262         u32 *desc, status;
263         int sh_idx, ret = 0;
264
265         desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
266         if (!desc)
267                 return -ENOMEM;
268
269         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
270                 /*
271                  * If the corresponding bit is set, then it means the state
272                  * handle was initialized by us, and thus it needs to be
273                  * deintialized as well
274                  */
275                 if ((1 << sh_idx) & state_handle_mask) {
276                         /*
277                          * Create the descriptor for deinstantating this state
278                          * handle
279                          */
280                         build_deinstantiation_desc(desc, sh_idx);
281
282                         /* Try to run it through DECO0 */
283                         ret = run_descriptor_deco0(ctrldev, desc, &status);
284
285                         if (ret ||
286                             (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
287                                 dev_err(ctrldev,
288                                         "Failed to deinstantiate RNG4 SH%d\n",
289                                         sh_idx);
290                                 break;
291                         }
292                         dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
293                 }
294         }
295
296         kfree(desc);
297
298         return ret;
299 }
300
301 static int caam_remove(struct platform_device *pdev)
302 {
303         struct device *ctrldev;
304         struct caam_drv_private *ctrlpriv;
305         struct caam_ctrl __iomem *ctrl;
306         int ring;
307
308         ctrldev = &pdev->dev;
309         ctrlpriv = dev_get_drvdata(ctrldev);
310         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
311
312         /* Remove platform devices for JobRs */
313         for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
314                 if (ctrlpriv->jrpdev[ring])
315                         of_device_unregister(ctrlpriv->jrpdev[ring]);
316         }
317
318         /* De-initialize RNG state handles initialized by this driver. */
319         if (ctrlpriv->rng4_sh_init)
320                 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
321
322         /* Shut down debug views */
323 #ifdef CONFIG_DEBUG_FS
324         debugfs_remove_recursive(ctrlpriv->dfs_root);
325 #endif
326
327         /* Unmap controller region */
328         iounmap(ctrl);
329
330         /* shut clocks off before finalizing shutdown */
331         clk_disable_unprepare(ctrlpriv->caam_ipg);
332         clk_disable_unprepare(ctrlpriv->caam_mem);
333         clk_disable_unprepare(ctrlpriv->caam_aclk);
334         clk_disable_unprepare(ctrlpriv->caam_emi_slow);
335
336         return 0;
337 }
338
339 /*
340  * kick_trng - sets the various parameters for enabling the initialization
341  *             of the RNG4 block in CAAM
342  * @pdev - pointer to the platform device
343  * @ent_delay - Defines the length (in system clocks) of each entropy sample.
344  */
345 static void kick_trng(struct platform_device *pdev, int ent_delay)
346 {
347         struct device *ctrldev = &pdev->dev;
348         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
349         struct caam_ctrl __iomem *ctrl;
350         struct rng4tst __iomem *r4tst;
351         u32 val;
352
353         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
354         r4tst = &ctrl->r4tst[0];
355
356         /* put RNG4 into program mode */
357         setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
358
359         /*
360          * Performance-wise, it does not make sense to
361          * set the delay to a value that is lower
362          * than the last one that worked (i.e. the state handles
363          * were instantiated properly. Thus, instead of wasting
364          * time trying to set the values controlling the sample
365          * frequency, the function simply returns.
366          */
367         val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
368               >> RTSDCTL_ENT_DLY_SHIFT;
369         if (ent_delay <= val) {
370                 /* put RNG4 into run mode */
371                 clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
372                 return;
373         }
374
375         val = rd_reg32(&r4tst->rtsdctl);
376         val = (val & ~RTSDCTL_ENT_DLY_MASK) |
377               (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
378         wr_reg32(&r4tst->rtsdctl, val);
379         /* min. freq. count, equal to 1/4 of the entropy sample length */
380         wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
381         /* disable maximum frequency count */
382         wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
383         /* read the control register */
384         val = rd_reg32(&r4tst->rtmctl);
385         /*
386          * select raw sampling in both entropy shifter
387          * and statistical checker
388          */
389         setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
390         /* put RNG4 into run mode */
391         clrbits32(&val, RTMCTL_PRGM);
392         /* write back the control register */
393         wr_reg32(&r4tst->rtmctl, val);
394 }
395
396 /**
397  * caam_get_era() - Return the ERA of the SEC on SoC, based
398  * on "sec-era" propery in the DTS. This property is updated by u-boot.
399  **/
400 int caam_get_era(void)
401 {
402         struct device_node *caam_node;
403         int ret;
404         u32 prop;
405
406         caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
407         ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
408         of_node_put(caam_node);
409
410         return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop;
411 }
412 EXPORT_SYMBOL(caam_get_era);
413
414 /* Probe routine for CAAM top (controller) level */
415 static int caam_probe(struct platform_device *pdev)
416 {
417         int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
418         u64 caam_id;
419         struct device *dev;
420         struct device_node *nprop, *np;
421         struct caam_ctrl __iomem *ctrl;
422         struct caam_drv_private *ctrlpriv;
423         struct clk *clk;
424 #ifdef CONFIG_DEBUG_FS
425         struct caam_perfmon *perfmon;
426 #endif
427         u32 scfgr, comp_params;
428         u32 cha_vid_ls;
429         int pg_size;
430         int BLOCK_OFFSET = 0;
431
432         ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
433         if (!ctrlpriv)
434                 return -ENOMEM;
435
436         dev = &pdev->dev;
437         dev_set_drvdata(dev, ctrlpriv);
438         ctrlpriv->pdev = pdev;
439         nprop = pdev->dev.of_node;
440
441         /* Enable clocking */
442         clk = caam_drv_identify_clk(&pdev->dev, "ipg");
443         if (IS_ERR(clk)) {
444                 ret = PTR_ERR(clk);
445                 dev_err(&pdev->dev,
446                         "can't identify CAAM ipg clk: %d\n", ret);
447                 return ret;
448         }
449         ctrlpriv->caam_ipg = clk;
450
451         clk = caam_drv_identify_clk(&pdev->dev, "mem");
452         if (IS_ERR(clk)) {
453                 ret = PTR_ERR(clk);
454                 dev_err(&pdev->dev,
455                         "can't identify CAAM mem clk: %d\n", ret);
456                 return ret;
457         }
458         ctrlpriv->caam_mem = clk;
459
460         clk = caam_drv_identify_clk(&pdev->dev, "aclk");
461         if (IS_ERR(clk)) {
462                 ret = PTR_ERR(clk);
463                 dev_err(&pdev->dev,
464                         "can't identify CAAM aclk clk: %d\n", ret);
465                 return ret;
466         }
467         ctrlpriv->caam_aclk = clk;
468
469         clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
470         if (IS_ERR(clk)) {
471                 ret = PTR_ERR(clk);
472                 dev_err(&pdev->dev,
473                         "can't identify CAAM emi_slow clk: %d\n", ret);
474                 return ret;
475         }
476         ctrlpriv->caam_emi_slow = clk;
477
478         ret = clk_prepare_enable(ctrlpriv->caam_ipg);
479         if (ret < 0) {
480                 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
481                 return ret;
482         }
483
484         ret = clk_prepare_enable(ctrlpriv->caam_mem);
485         if (ret < 0) {
486                 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
487                         ret);
488                 goto disable_caam_ipg;
489         }
490
491         ret = clk_prepare_enable(ctrlpriv->caam_aclk);
492         if (ret < 0) {
493                 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
494                 goto disable_caam_mem;
495         }
496
497         ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
498         if (ret < 0) {
499                 dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
500                         ret);
501                 goto disable_caam_aclk;
502         }
503
504         /* Get configuration properties from device tree */
505         /* First, get register page */
506         ctrl = of_iomap(nprop, 0);
507         if (ctrl == NULL) {
508                 dev_err(dev, "caam: of_iomap() failed\n");
509                 ret = -ENOMEM;
510                 goto disable_caam_emi_slow;
511         }
512         /* Finding the page size for using the CTPR_MS register */
513         comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
514         pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
515
516         /* Allocating the BLOCK_OFFSET based on the supported page size on
517          * the platform
518          */
519         if (pg_size == 0)
520                 BLOCK_OFFSET = PG_SIZE_4K;
521         else
522                 BLOCK_OFFSET = PG_SIZE_64K;
523
524         ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
525         ctrlpriv->assure = (struct caam_assurance __force *)
526                            ((uint8_t *)ctrl +
527                             BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
528                            );
529         ctrlpriv->deco = (struct caam_deco __force *)
530                          ((uint8_t *)ctrl +
531                          BLOCK_OFFSET * DECO_BLOCK_NUMBER
532                          );
533
534         /* Get the IRQ of the controller (for security violations only) */
535         ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
536
537         /*
538          * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
539          * long pointers in master configuration register
540          */
541         clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
542                       MCFGR_AWCACHE_BUFF | MCFGR_WDENABLE |
543                       (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
544
545         /*
546          *  Read the Compile Time paramters and SCFGR to determine
547          * if Virtualization is enabled for this platform
548          */
549         scfgr = rd_reg32(&ctrl->scfgr);
550
551         ctrlpriv->virt_en = 0;
552         if (comp_params & CTPR_MS_VIRT_EN_INCL) {
553                 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
554                  * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
555                  */
556                 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
557                     (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
558                        (scfgr & SCFGR_VIRT_EN)))
559                                 ctrlpriv->virt_en = 1;
560         } else {
561                 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
562                 if (comp_params & CTPR_MS_VIRT_EN_POR)
563                                 ctrlpriv->virt_en = 1;
564         }
565
566         if (ctrlpriv->virt_en == 1)
567                 setbits32(&ctrl->jrstart, JRSTART_JR0_START |
568                           JRSTART_JR1_START | JRSTART_JR2_START |
569                           JRSTART_JR3_START);
570
571         if (sizeof(dma_addr_t) == sizeof(u64))
572                 if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
573                         dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
574                 else
575                         dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
576         else
577                 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
578
579         /*
580          * Detect and enable JobRs
581          * First, find out how many ring spec'ed, allocate references
582          * for all, then go probe each one.
583          */
584         rspec = 0;
585         for_each_available_child_of_node(nprop, np)
586                 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
587                     of_device_is_compatible(np, "fsl,sec4.0-job-ring"))
588                         rspec++;
589
590         ctrlpriv->jrpdev = devm_kcalloc(&pdev->dev, rspec,
591                                         sizeof(*ctrlpriv->jrpdev), GFP_KERNEL);
592         if (ctrlpriv->jrpdev == NULL) {
593                 ret = -ENOMEM;
594                 goto iounmap_ctrl;
595         }
596
597         ring = 0;
598         ctrlpriv->total_jobrs = 0;
599         for_each_available_child_of_node(nprop, np)
600                 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
601                     of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
602                         ctrlpriv->jrpdev[ring] =
603                                 of_platform_device_create(np, NULL, dev);
604                         if (!ctrlpriv->jrpdev[ring]) {
605                                 pr_warn("JR%d Platform device creation error\n",
606                                         ring);
607                                 continue;
608                         }
609                         ctrlpriv->jr[ring] = (struct caam_job_ring __force *)
610                                              ((uint8_t *)ctrl +
611                                              (ring + JR_BLOCK_NUMBER) *
612                                               BLOCK_OFFSET
613                                              );
614                         ctrlpriv->total_jobrs++;
615                         ring++;
616         }
617
618         /* Check to see if QI present. If so, enable */
619         ctrlpriv->qi_present =
620                         !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
621                            CTPR_MS_QI_MASK);
622         if (ctrlpriv->qi_present) {
623                 ctrlpriv->qi = (struct caam_queue_if __force *)
624                                ((uint8_t *)ctrl +
625                                  BLOCK_OFFSET * QI_BLOCK_NUMBER
626                                );
627                 /* This is all that's required to physically enable QI */
628                 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
629         }
630
631         /* If no QI and no rings specified, quit and go home */
632         if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
633                 dev_err(dev, "no queues configured, terminating\n");
634                 ret = -ENOMEM;
635                 goto caam_remove;
636         }
637
638         cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
639
640         /*
641          * If SEC has RNG version >= 4 and RNG state handle has not been
642          * already instantiated, do RNG instantiation
643          */
644         if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
645                 ctrlpriv->rng4_sh_init =
646                         rd_reg32(&ctrl->r4tst[0].rdsta);
647                 /*
648                  * If the secure keys (TDKEK, JDKEK, TDSK), were already
649                  * generated, signal this to the function that is instantiating
650                  * the state handles. An error would occur if RNG4 attempts
651                  * to regenerate these keys before the next POR.
652                  */
653                 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
654                 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
655                 do {
656                         int inst_handles =
657                                 rd_reg32(&ctrl->r4tst[0].rdsta) &
658                                                                 RDSTA_IFMASK;
659                         /*
660                          * If either SH were instantiated by somebody else
661                          * (e.g. u-boot) then it is assumed that the entropy
662                          * parameters are properly set and thus the function
663                          * setting these (kick_trng(...)) is skipped.
664                          * Also, if a handle was instantiated, do not change
665                          * the TRNG parameters.
666                          */
667                         if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
668                                 dev_info(dev,
669                                          "Entropy delay = %u\n",
670                                          ent_delay);
671                                 kick_trng(pdev, ent_delay);
672                                 ent_delay += 400;
673                         }
674                         /*
675                          * if instantiate_rng(...) fails, the loop will rerun
676                          * and the kick_trng(...) function will modfiy the
677                          * upper and lower limits of the entropy sampling
678                          * interval, leading to a sucessful initialization of
679                          * the RNG.
680                          */
681                         ret = instantiate_rng(dev, inst_handles,
682                                               gen_sk);
683                         if (ret == -EAGAIN)
684                                 /*
685                                  * if here, the loop will rerun,
686                                  * so don't hog the CPU
687                                  */
688                                 cpu_relax();
689                 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
690                 if (ret) {
691                         dev_err(dev, "failed to instantiate RNG");
692                         goto caam_remove;
693                 }
694                 /*
695                  * Set handles init'ed by this module as the complement of the
696                  * already initialized ones
697                  */
698                 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
699
700                 /* Enable RDB bit so that RNG works faster */
701                 setbits32(&ctrl->scfgr, SCFGR_RDBENABLE);
702         }
703
704         /* NOTE: RTIC detection ought to go here, around Si time */
705
706         caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
707                   (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
708
709         /* Report "alive" for developer to see */
710         dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
711                  caam_get_era());
712         dev_info(dev, "job rings = %d, qi = %d\n",
713                  ctrlpriv->total_jobrs, ctrlpriv->qi_present);
714
715 #ifdef CONFIG_DEBUG_FS
716         /*
717          * FIXME: needs better naming distinction, as some amalgamation of
718          * "caam" and nprop->full_name. The OF name isn't distinctive,
719          * but does separate instances
720          */
721         perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
722
723         ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
724         ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
725
726         /* Controller-level - performance monitor counters */
727         ctrlpriv->ctl_rq_dequeued =
728                 debugfs_create_u64("rq_dequeued",
729                                    S_IRUSR | S_IRGRP | S_IROTH,
730                                    ctrlpriv->ctl, &perfmon->req_dequeued);
731         ctrlpriv->ctl_ob_enc_req =
732                 debugfs_create_u64("ob_rq_encrypted",
733                                    S_IRUSR | S_IRGRP | S_IROTH,
734                                    ctrlpriv->ctl, &perfmon->ob_enc_req);
735         ctrlpriv->ctl_ib_dec_req =
736                 debugfs_create_u64("ib_rq_decrypted",
737                                    S_IRUSR | S_IRGRP | S_IROTH,
738                                    ctrlpriv->ctl, &perfmon->ib_dec_req);
739         ctrlpriv->ctl_ob_enc_bytes =
740                 debugfs_create_u64("ob_bytes_encrypted",
741                                    S_IRUSR | S_IRGRP | S_IROTH,
742                                    ctrlpriv->ctl, &perfmon->ob_enc_bytes);
743         ctrlpriv->ctl_ob_prot_bytes =
744                 debugfs_create_u64("ob_bytes_protected",
745                                    S_IRUSR | S_IRGRP | S_IROTH,
746                                    ctrlpriv->ctl, &perfmon->ob_prot_bytes);
747         ctrlpriv->ctl_ib_dec_bytes =
748                 debugfs_create_u64("ib_bytes_decrypted",
749                                    S_IRUSR | S_IRGRP | S_IROTH,
750                                    ctrlpriv->ctl, &perfmon->ib_dec_bytes);
751         ctrlpriv->ctl_ib_valid_bytes =
752                 debugfs_create_u64("ib_bytes_validated",
753                                    S_IRUSR | S_IRGRP | S_IROTH,
754                                    ctrlpriv->ctl, &perfmon->ib_valid_bytes);
755
756         /* Controller level - global status values */
757         ctrlpriv->ctl_faultaddr =
758                 debugfs_create_u64("fault_addr",
759                                    S_IRUSR | S_IRGRP | S_IROTH,
760                                    ctrlpriv->ctl, &perfmon->faultaddr);
761         ctrlpriv->ctl_faultdetail =
762                 debugfs_create_u32("fault_detail",
763                                    S_IRUSR | S_IRGRP | S_IROTH,
764                                    ctrlpriv->ctl, &perfmon->faultdetail);
765         ctrlpriv->ctl_faultstatus =
766                 debugfs_create_u32("fault_status",
767                                    S_IRUSR | S_IRGRP | S_IROTH,
768                                    ctrlpriv->ctl, &perfmon->status);
769
770         /* Internal covering keys (useful in non-secure mode only) */
771         ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
772         ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
773         ctrlpriv->ctl_kek = debugfs_create_blob("kek",
774                                                 S_IRUSR |
775                                                 S_IRGRP | S_IROTH,
776                                                 ctrlpriv->ctl,
777                                                 &ctrlpriv->ctl_kek_wrap);
778
779         ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
780         ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
781         ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
782                                                  S_IRUSR |
783                                                  S_IRGRP | S_IROTH,
784                                                  ctrlpriv->ctl,
785                                                  &ctrlpriv->ctl_tkek_wrap);
786
787         ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
788         ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
789         ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
790                                                  S_IRUSR |
791                                                  S_IRGRP | S_IROTH,
792                                                  ctrlpriv->ctl,
793                                                  &ctrlpriv->ctl_tdsk_wrap);
794 #endif
795         return 0;
796
797 caam_remove:
798         caam_remove(pdev);
799 iounmap_ctrl:
800         iounmap(ctrl);
801 disable_caam_emi_slow:
802         clk_disable_unprepare(ctrlpriv->caam_emi_slow);
803 disable_caam_aclk:
804         clk_disable_unprepare(ctrlpriv->caam_aclk);
805 disable_caam_mem:
806         clk_disable_unprepare(ctrlpriv->caam_mem);
807 disable_caam_ipg:
808         clk_disable_unprepare(ctrlpriv->caam_ipg);
809         return ret;
810 }
811
812 static struct of_device_id caam_match[] = {
813         {
814                 .compatible = "fsl,sec-v4.0",
815         },
816         {
817                 .compatible = "fsl,sec4.0",
818         },
819         {},
820 };
821 MODULE_DEVICE_TABLE(of, caam_match);
822
823 static struct platform_driver caam_driver = {
824         .driver = {
825                 .name = "caam",
826                 .of_match_table = caam_match,
827         },
828         .probe       = caam_probe,
829         .remove      = caam_remove,
830 };
831
832 module_platform_driver(caam_driver);
833
834 MODULE_LICENSE("GPL");
835 MODULE_DESCRIPTION("FSL CAAM request backend");
836 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");