drivers/crypto/caam/caamhash.c

   1 /*
   2  * caam - Freescale FSL CAAM support for ahash functions of crypto API
   3  *
   4  * Copyright 2011 Freescale Semiconductor, Inc.
   5  *
   6  * Based on caamalg.c crypto API driver.
   7  *
   8  * relationship of digest job descriptor or first job descriptor after init to
   9  * shared descriptors:
  10  *
  11  * ---------------                     ---------------
  12  * | JobDesc #1  |-------------------->|  ShareDesc  |
  13  * | *(packet 1) |                     |  (hashKey)  |
  14  * ---------------                     | (operation) |
  15  *                                     ---------------
  16  *
  17  * relationship of subsequent job descriptors to shared descriptors:
  18  *
  19  * ---------------                     ---------------
  20  * | JobDesc #2  |-------------------->|  ShareDesc  |
  21  * | *(packet 2) |      |------------->|  (hashKey)  |
  22  * ---------------      |    |-------->| (operation) |
  23  *       .              |    |         | (load ctx2) |
  24  *       .              |    |         ---------------
  25  * ---------------      |    |
  26  * | JobDesc #3  |------|    |
  27  * | *(packet 3) |           |
  28  * ---------------           |
  29  *       .                   |
  30  *       .                   |
  31  * ---------------           |
  32  * | JobDesc #4  |------------
  33  * | *(packet 4) |
  34  * ---------------
  35  *
  36  * The SharedDesc never changes for a connection unless rekeyed, but
  37  * each packet will likely be in a different place. So all we need
  38  * to know to process the packet is where the input is, where the
  39  * output goes, and what context we want to process with. Context is
  40  * in the SharedDesc, packet references in the JobDesc.
  41  *
  42  * So, a job desc looks like:
  43  *
  44  * ---------------------
  45  * | Header            |
  46  * | ShareDesc Pointer |
  47  * | SEQ_OUT_PTR       |
  48  * | (output buffer)   |
  49  * | (output length)   |
  50  * | SEQ_IN_PTR        |
  51  * | (input buffer)    |
  52  * | (input length)    |
  53  * ---------------------
  54  */
  55
  56 #include "compat.h"
  57
  58 #include "regs.h"
  59 #include "intern.h"
  60 #include "desc_constr.h"
  61 #include "jr.h"
  62 #include "error.h"
  63 #include "sg_sw_sec4.h"
  64 #include "key_gen.h"
  65
  66 #define CAAM_CRA_PRIORITY               3000
  67
  68 /* max hash key is max split key size */
  69 #define CAAM_MAX_HASH_KEY_SIZE          (SHA512_DIGEST_SIZE * 2)
  70
  71 #define CAAM_MAX_HASH_BLOCK_SIZE        SHA512_BLOCK_SIZE
  72 #define CAAM_MAX_HASH_DIGEST_SIZE       SHA512_DIGEST_SIZE
  73
  74 /* length of descriptors text */
  75 #define DESC_AHASH_BASE                 (4 * CAAM_CMD_SZ)
  76 #define DESC_AHASH_UPDATE_LEN           (6 * CAAM_CMD_SZ)
  77 #define DESC_AHASH_UPDATE_FIRST_LEN     (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
  78 #define DESC_AHASH_FINAL_LEN            (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
  79 #define DESC_AHASH_FINUP_LEN            (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
  80 #define DESC_AHASH_DIGEST_LEN           (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
  81
  82 #define DESC_HASH_MAX_USED_BYTES        (DESC_AHASH_FINAL_LEN + \
  83                                          CAAM_MAX_HASH_KEY_SIZE)
  84 #define DESC_HASH_MAX_USED_LEN          (DESC_HASH_MAX_USED_BYTES / CAAM_CMD_SZ)
  85
  86 /* caam context sizes for hashes: running digest + 8 */
  87 #define HASH_MSG_LEN                    8
  88 #define MAX_CTX_LEN                     (HASH_MSG_LEN + SHA512_DIGEST_SIZE)
  89
  90 #ifdef DEBUG
  91 /* for print_hex_dumps with line references */
  92 #define debug(format, arg...) printk(format, arg)
  93 #else
  94 #define debug(format, arg...)
  95 #endif
  96
  97
  98 static struct list_head hash_list;
  99
 100 /* ahash per-session context */
 101 struct caam_hash_ctx {
 102         u32 sh_desc_update[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
 103         u32 sh_desc_update_first[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
 104         u32 sh_desc_fin[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
 105         u32 sh_desc_digest[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
 106         u32 sh_desc_finup[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
 107         dma_addr_t sh_desc_update_dma ____cacheline_aligned;
 108         dma_addr_t sh_desc_update_first_dma;
 109         dma_addr_t sh_desc_fin_dma;
 110         dma_addr_t sh_desc_digest_dma;
 111         dma_addr_t sh_desc_finup_dma;
 112         struct device *jrdev;
 113         u32 alg_type;
 114         u32 alg_op;
 115         u8 key[CAAM_MAX_HASH_KEY_SIZE];
 116         dma_addr_t key_dma;
 117         int ctx_len;
 118         unsigned int split_key_len;
 119         unsigned int split_key_pad_len;
 120 };
 121
 122 /* ahash state */
 123 struct caam_hash_state {
 124         dma_addr_t buf_dma;
 125         dma_addr_t ctx_dma;
 126         u8 buf_0[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
 127         int buflen_0;
 128         u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
 129         int buflen_1;
 130         u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
 131         int (*update)(struct ahash_request *req);
 132         int (*final)(struct ahash_request *req);
 133         int (*finup)(struct ahash_request *req);
 134         int current_buf;
 135 };
 136
 137 struct caam_export_state {
 138         u8 buf[CAAM_MAX_HASH_BLOCK_SIZE];
 139         u8 caam_ctx[MAX_CTX_LEN];
 140         int buflen;
 141         int (*update)(struct ahash_request *req);
 142         int (*final)(struct ahash_request *req);
 143         int (*finup)(struct ahash_request *req);
 144 };
 145
 146 /* Common job descriptor seq in/out ptr routines */
 147
 148 /* Map state->caam_ctx, and append seq_out_ptr command that points to it */
 149 static inline int map_seq_out_ptr_ctx(u32 *desc, struct device *jrdev,
 150                                       struct caam_hash_state *state,
 151                                       int ctx_len)
 152 {
 153         state->ctx_dma = dma_map_single(jrdev, state->caam_ctx,
 154                                         ctx_len, DMA_FROM_DEVICE);
 155         if (dma_mapping_error(jrdev, state->ctx_dma)) {
 156                 dev_err(jrdev, "unable to map ctx\n");
 157                 state->ctx_dma = 0;
 158                 return -ENOMEM;
 159         }
 160
 161         append_seq_out_ptr(desc, state->ctx_dma, ctx_len, 0);
 162
 163         return 0;
 164 }
 165
 166 /* Map req->result, and append seq_out_ptr command that points to it */
 167 static inline dma_addr_t map_seq_out_ptr_result(u32 *desc, struct device *jrdev,
 168                                                 u8 *result, int digestsize)
 169 {
 170         dma_addr_t dst_dma;
 171
 172         dst_dma = dma_map_single(jrdev, result, digestsize, DMA_FROM_DEVICE);
 173         append_seq_out_ptr(desc, dst_dma, digestsize, 0);
 174
 175         return dst_dma;
 176 }
 177
 178 /* Map current buffer in state and put it in link table */
 179 static inline dma_addr_t buf_map_to_sec4_sg(struct device *jrdev,
 180                                             struct sec4_sg_entry *sec4_sg,
 181                                             u8 *buf, int buflen)
 182 {
 183         dma_addr_t buf_dma;
 184
 185         buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE);
 186         dma_to_sec4_sg_one(sec4_sg, buf_dma, buflen, 0);
 187
 188         return buf_dma;
 189 }
 190
 191 /*
 192  * Only put buffer in link table if it contains data, which is possible,
 193  * since a buffer has previously been used, and needs to be unmapped,
 194  */
 195 static inline dma_addr_t
 196 try_buf_map_to_sec4_sg(struct device *jrdev, struct sec4_sg_entry *sec4_sg,
 197                        u8 *buf, dma_addr_t buf_dma, int buflen,
 198                        int last_buflen)
 199 {
 200         if (buf_dma && !dma_mapping_error(jrdev, buf_dma))
 201                 dma_unmap_single(jrdev, buf_dma, last_buflen, DMA_TO_DEVICE);
 202         if (buflen)
 203                 buf_dma = buf_map_to_sec4_sg(jrdev, sec4_sg, buf, buflen);
 204         else
 205                 buf_dma = 0;
 206
 207         return buf_dma;
 208 }
 209
 210 /* Map state->caam_ctx, and add it to link table */
 211 static inline int ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev,
 212                                      struct caam_hash_state *state, int ctx_len,
 213                                      struct sec4_sg_entry *sec4_sg, u32 flag)
 214 {
 215         state->ctx_dma = dma_map_single(jrdev, state->caam_ctx, ctx_len, flag);
 216         if (dma_mapping_error(jrdev, state->ctx_dma)) {
 217                 dev_err(jrdev, "unable to map ctx\n");
 218                 state->ctx_dma = 0;
 219                 return -ENOMEM;
 220         }
 221
 222         dma_to_sec4_sg_one(sec4_sg, state->ctx_dma, ctx_len, 0);
 223
 224         return 0;
 225 }
 226
 227 /* Common shared descriptor commands */
 228 static inline void append_key_ahash(u32 *desc, struct caam_hash_ctx *ctx)
 229 {
 230         append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
 231                           ctx->split_key_len, CLASS_2 |
 232                           KEY_DEST_MDHA_SPLIT | KEY_ENC);
 233 }
 234
 235 /* Append key if it has been set */
 236 static inline void init_sh_desc_key_ahash(u32 *desc, struct caam_hash_ctx *ctx)
 237 {
 238         u32 *key_jump_cmd;
 239
 240         init_sh_desc(desc, HDR_SHARE_SERIAL);
 241
 242         if (ctx->split_key_len) {
 243                 /* Skip if already shared */
 244                 key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
 245                                            JUMP_COND_SHRD);
 246
 247                 append_key_ahash(desc, ctx);
 248
 249                 set_jump_tgt_here(desc, key_jump_cmd);
 250         }
 251
 252         /* Propagate errors from shared to job descriptor */
 253         append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
 254 }
 255
 256 /*
 257  * For ahash read data from seqin following state->caam_ctx,
 258  * and write resulting class2 context to seqout, which may be state->caam_ctx
 259  * or req->result
 260  */
 261 static inline void ahash_append_load_str(u32 *desc, int digestsize)
 262 {
 263         /* Calculate remaining bytes to read */
 264         append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
 265
 266         /* Read remaining bytes */
 267         append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_LAST2 |
 268                              FIFOLD_TYPE_MSG | KEY_VLF);
 269
 270         /* Store class2 context bytes */
 271         append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
 272                          LDST_SRCDST_BYTE_CONTEXT);
 273 }
 274
 275 /*
 276  * For ahash update, final and finup, import context, read and write to seqout
 277  */
 278 static inline void ahash_ctx_data_to_out(u32 *desc, u32 op, u32 state,
 279                                          int digestsize,
 280                                          struct caam_hash_ctx *ctx)
 281 {
 282         init_sh_desc_key_ahash(desc, ctx);
 283
 284         /* Import context from software */
 285         append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
 286                    LDST_CLASS_2_CCB | ctx->ctx_len);
 287
 288         /* Class 2 operation */
 289         append_operation(desc, op | state | OP_ALG_ENCRYPT);
 290
 291         /*
 292          * Load from buf and/or src and write to req->result or state->context
 293          */
 294         ahash_append_load_str(desc, digestsize);
 295 }
 296
 297 /* For ahash firsts and digest, read and write to seqout */
 298 static inline void ahash_data_to_out(u32 *desc, u32 op, u32 state,
 299                                      int digestsize, struct caam_hash_ctx *ctx)
 300 {
 301         init_sh_desc_key_ahash(desc, ctx);
 302
 303         /* Class 2 operation */
 304         append_operation(desc, op | state | OP_ALG_ENCRYPT);
 305
 306         /*
 307          * Load from buf and/or src and write to req->result or state->context
 308          */
 309         ahash_append_load_str(desc, digestsize);
 310 }
 311
 312 static int ahash_set_sh_desc(struct crypto_ahash *ahash)
 313 {
 314         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 315         int digestsize = crypto_ahash_digestsize(ahash);
 316         struct device *jrdev = ctx->jrdev;
 317         u32 have_key = 0;
 318         u32 *desc;
 319
 320         if (ctx->split_key_len)
 321                 have_key = OP_ALG_AAI_HMAC_PRECOMP;
 322
 323         /* ahash_update shared descriptor */
 324         desc = ctx->sh_desc_update;
 325
 326         init_sh_desc(desc, HDR_SHARE_SERIAL);
 327
 328         /* Import context from software */
 329         append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
 330                    LDST_CLASS_2_CCB | ctx->ctx_len);
 331
 332         /* Class 2 operation */
 333         append_operation(desc, ctx->alg_type | OP_ALG_AS_UPDATE |
 334                          OP_ALG_ENCRYPT);
 335
 336         /* Load data and write to result or context */
 337         ahash_append_load_str(desc, ctx->ctx_len);
 338
 339         ctx->sh_desc_update_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
 340                                                  DMA_TO_DEVICE);
 341         if (dma_mapping_error(jrdev, ctx->sh_desc_update_dma)) {
 342                 dev_err(jrdev, "unable to map shared descriptor\n");
 343                 return -ENOMEM;
 344         }
 345 #ifdef DEBUG
 346         print_hex_dump(KERN_ERR,
 347                        "ahash update shdesc@"__stringify(__LINE__)": ",
 348                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
 349 #endif
 350
 351         /* ahash_update_first shared descriptor */
 352         desc = ctx->sh_desc_update_first;
 353
 354         ahash_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INIT,
 355                           ctx->ctx_len, ctx);
 356
 357         ctx->sh_desc_update_first_dma = dma_map_single(jrdev, desc,
 358                                                        desc_bytes(desc),
 359                                                        DMA_TO_DEVICE);
 360         if (dma_mapping_error(jrdev, ctx->sh_desc_update_first_dma)) {
 361                 dev_err(jrdev, "unable to map shared descriptor\n");
 362                 return -ENOMEM;
 363         }
 364 #ifdef DEBUG
 365         print_hex_dump(KERN_ERR,
 366                        "ahash update first shdesc@"__stringify(__LINE__)": ",
 367                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
 368 #endif
 369
 370         /* ahash_final shared descriptor */
 371         desc = ctx->sh_desc_fin;
 372
 373         ahash_ctx_data_to_out(desc, have_key | ctx->alg_type,
 374                               OP_ALG_AS_FINALIZE, digestsize, ctx);
 375
 376         ctx->sh_desc_fin_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
 377                                               DMA_TO_DEVICE);
 378         if (dma_mapping_error(jrdev, ctx->sh_desc_fin_dma)) {
 379                 dev_err(jrdev, "unable to map shared descriptor\n");
 380                 return -ENOMEM;
 381         }
 382 #ifdef DEBUG
 383         print_hex_dump(KERN_ERR, "ahash final shdesc@"__stringify(__LINE__)": ",
 384                        DUMP_PREFIX_ADDRESS, 16, 4, desc,
 385                        desc_bytes(desc), 1);
 386 #endif
 387
 388         /* ahash_finup shared descriptor */
 389         desc = ctx->sh_desc_finup;
 390
 391         ahash_ctx_data_to_out(desc, have_key | ctx->alg_type,
 392                               OP_ALG_AS_FINALIZE, digestsize, ctx);
 393
 394         ctx->sh_desc_finup_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
 395                                                 DMA_TO_DEVICE);
 396         if (dma_mapping_error(jrdev, ctx->sh_desc_finup_dma)) {
 397                 dev_err(jrdev, "unable to map shared descriptor\n");
 398                 return -ENOMEM;
 399         }
 400 #ifdef DEBUG
 401         print_hex_dump(KERN_ERR, "ahash finup shdesc@"__stringify(__LINE__)": ",
 402                        DUMP_PREFIX_ADDRESS, 16, 4, desc,
 403                        desc_bytes(desc), 1);
 404 #endif
 405
 406         /* ahash_digest shared descriptor */
 407         desc = ctx->sh_desc_digest;
 408
 409         ahash_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INITFINAL,
 410                           digestsize, ctx);
 411
 412         ctx->sh_desc_digest_dma = dma_map_single(jrdev, desc,
 413                                                  desc_bytes(desc),
 414                                                  DMA_TO_DEVICE);
 415         if (dma_mapping_error(jrdev, ctx->sh_desc_digest_dma)) {
 416                 dev_err(jrdev, "unable to map shared descriptor\n");
 417                 return -ENOMEM;
 418         }
 419 #ifdef DEBUG
 420         print_hex_dump(KERN_ERR,
 421                        "ahash digest shdesc@"__stringify(__LINE__)": ",
 422                        DUMP_PREFIX_ADDRESS, 16, 4, desc,
 423                        desc_bytes(desc), 1);
 424 #endif
 425
 426         return 0;
 427 }
 428
 429 static int gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in,
 430                               u32 keylen)
 431 {
 432         return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len,
 433                                ctx->split_key_pad_len, key_in, keylen,
 434                                ctx->alg_op);
 435 }
 436
 437 /* Digest hash size if it is too large */
 438 static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in,
 439                            u32 *keylen, u8 *key_out, u32 digestsize)
 440 {
 441         struct device *jrdev = ctx->jrdev;
 442         u32 *desc;
 443         struct split_key_result result;
 444         dma_addr_t src_dma, dst_dma;
 445         int ret;
 446
 447         desc = kmalloc(CAAM_CMD_SZ * 8 + CAAM_PTR_SZ * 2, GFP_KERNEL | GFP_DMA);
 448         if (!desc) {
 449                 dev_err(jrdev, "unable to allocate key input memory\n");
 450                 return -ENOMEM;
 451         }
 452
 453         init_job_desc(desc, 0);
 454
 455         src_dma = dma_map_single(jrdev, (void *)key_in, *keylen,
 456                                  DMA_TO_DEVICE);
 457         if (dma_mapping_error(jrdev, src_dma)) {
 458                 dev_err(jrdev, "unable to map key input memory\n");
 459                 kfree(desc);
 460                 return -ENOMEM;
 461         }
 462         dst_dma = dma_map_single(jrdev, (void *)key_out, digestsize,
 463                                  DMA_FROM_DEVICE);
 464         if (dma_mapping_error(jrdev, dst_dma)) {
 465                 dev_err(jrdev, "unable to map key output memory\n");
 466                 dma_unmap_single(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
 467                 kfree(desc);
 468                 return -ENOMEM;
 469         }
 470
 471         /* Job descriptor to perform unkeyed hash on key_in */
 472         append_operation(desc, ctx->alg_type | OP_ALG_ENCRYPT |
 473                          OP_ALG_AS_INITFINAL);
 474         append_seq_in_ptr(desc, src_dma, *keylen, 0);
 475         append_seq_fifo_load(desc, *keylen, FIFOLD_CLASS_CLASS2 |
 476                              FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_MSG);
 477         append_seq_out_ptr(desc, dst_dma, digestsize, 0);
 478         append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
 479                          LDST_SRCDST_BYTE_CONTEXT);
 480
 481 #ifdef DEBUG
 482         print_hex_dump(KERN_ERR, "key_in@"__stringify(__LINE__)": ",
 483                        DUMP_PREFIX_ADDRESS, 16, 4, key_in, *keylen, 1);
 484         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
 485                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
 486 #endif
 487
 488         result.err = 0;
 489         init_completion(&result.completion);
 490
 491         ret = caam_jr_enqueue(jrdev, desc, split_key_done, &result);
 492         if (!ret) {
 493                 /* in progress */
 494                 wait_for_completion(&result.completion);
 495                 ret = result.err;
 496 #ifdef DEBUG
 497                 print_hex_dump(KERN_ERR,
 498                                "digested key@"__stringify(__LINE__)": ",
 499                                DUMP_PREFIX_ADDRESS, 16, 4, key_in,
 500                                digestsize, 1);
 501 #endif
 502         }
 503         dma_unmap_single(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
 504         dma_unmap_single(jrdev, dst_dma, digestsize, DMA_FROM_DEVICE);
 505
 506         *keylen = digestsize;
 507
 508         kfree(desc);
 509
 510         return ret;
 511 }
 512
 513 static int ahash_setkey(struct crypto_ahash *ahash,
 514                         const u8 *key, unsigned int keylen)
 515 {
 516         /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
 517         static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
 518         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 519         struct device *jrdev = ctx->jrdev;
 520         int blocksize = crypto_tfm_alg_blocksize(&ahash->base);
 521         int digestsize = crypto_ahash_digestsize(ahash);
 522         int ret;
 523         u8 *hashed_key = NULL;
 524
 525 #ifdef DEBUG
 526         printk(KERN_ERR "keylen %d\n", keylen);
 527 #endif
 528
 529         if (keylen > blocksize) {
 530                 hashed_key = kmalloc_array(digestsize,
 531                                            sizeof(*hashed_key),
 532                                            GFP_KERNEL | GFP_DMA);
 533                 if (!hashed_key)
 534                         return -ENOMEM;
 535                 ret = hash_digest_key(ctx, key, &keylen, hashed_key,
 536                                       digestsize);
 537                 if (ret)
 538                         goto bad_free_key;
 539                 key = hashed_key;
 540         }
 541
 542         /* Pick class 2 key length from algorithm submask */
 543         ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
 544                                       OP_ALG_ALGSEL_SHIFT] * 2;
 545         ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16);
 546
 547 #ifdef DEBUG
 548         printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
 549                ctx->split_key_len, ctx->split_key_pad_len);
 550         print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
 551                        DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
 552 #endif
 553
 554         ret = gen_split_hash_key(ctx, key, keylen);
 555         if (ret)
 556                 goto bad_free_key;
 557
 558         ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len,
 559                                       DMA_TO_DEVICE);
 560         if (dma_mapping_error(jrdev, ctx->key_dma)) {
 561                 dev_err(jrdev, "unable to map key i/o memory\n");
 562                 ret = -ENOMEM;
 563                 goto error_free_key;
 564         }
 565 #ifdef DEBUG
 566         print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
 567                        DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
 568                        ctx->split_key_pad_len, 1);
 569 #endif
 570
 571         ret = ahash_set_sh_desc(ahash);
 572         if (ret) {
 573                 dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len,
 574                                  DMA_TO_DEVICE);
 575         }
 576  error_free_key:
 577         kfree(hashed_key);
 578         return ret;
 579  bad_free_key:
 580         kfree(hashed_key);
 581         crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN);
 582         return -EINVAL;
 583 }
 584
 585 /*
 586  * ahash_edesc - s/w-extended ahash descriptor
 587  * @dst_dma: physical mapped address of req->result
 588  * @sec4_sg_dma: physical mapped address of h/w link table
 589  * @src_nents: number of segments in input scatterlist
 590  * @sec4_sg_bytes: length of dma mapped sec4_sg space
 591  * @hw_desc: the h/w job descriptor followed by any referenced link tables
 592  * @sec4_sg: h/w link table
 593  */
 594 struct ahash_edesc {
 595         dma_addr_t dst_dma;
 596         dma_addr_t sec4_sg_dma;
 597         int src_nents;
 598         int sec4_sg_bytes;
 599         u32 hw_desc[DESC_JOB_IO_LEN / sizeof(u32)] ____cacheline_aligned;
 600         struct sec4_sg_entry sec4_sg[0];
 601 };
 602
 603 static inline void ahash_unmap(struct device *dev,
 604                         struct ahash_edesc *edesc,
 605                         struct ahash_request *req, int dst_len)
 606 {
 607         if (edesc->src_nents)
 608                 dma_unmap_sg(dev, req->src, edesc->src_nents, DMA_TO_DEVICE);
 609         if (edesc->dst_dma)
 610                 dma_unmap_single(dev, edesc->dst_dma, dst_len, DMA_FROM_DEVICE);
 611
 612         if (edesc->sec4_sg_bytes)
 613                 dma_unmap_single(dev, edesc->sec4_sg_dma,
 614                                  edesc->sec4_sg_bytes, DMA_TO_DEVICE);
 615 }
 616
 617 static inline void ahash_unmap_ctx(struct device *dev,
 618                         struct ahash_edesc *edesc,
 619                         struct ahash_request *req, int dst_len, u32 flag)
 620 {
 621         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 622         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 623         struct caam_hash_state *state = ahash_request_ctx(req);
 624
 625         if (state->ctx_dma) {
 626                 dma_unmap_single(dev, state->ctx_dma, ctx->ctx_len, flag);
 627                 state->ctx_dma = 0;
 628         }
 629         ahash_unmap(dev, edesc, req, dst_len);
 630 }
 631
 632 static void ahash_done(struct device *jrdev, u32 *desc, u32 err,
 633                        void *context)
 634 {
 635         struct ahash_request *req = context;
 636         struct ahash_edesc *edesc;
 637         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 638         int digestsize = crypto_ahash_digestsize(ahash);
 639 #ifdef DEBUG
 640         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 641         struct caam_hash_state *state = ahash_request_ctx(req);
 642
 643         dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
 644 #endif
 645
 646         edesc = (struct ahash_edesc *)((char *)desc -
 647                  offsetof(struct ahash_edesc, hw_desc));
 648         if (err)
 649                 caam_jr_strstatus(jrdev, err);
 650
 651         ahash_unmap(jrdev, edesc, req, digestsize);
 652         kfree(edesc);
 653
 654 #ifdef DEBUG
 655         print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
 656                        DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
 657                        ctx->ctx_len, 1);
 658         if (req->result)
 659                 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
 660                                DUMP_PREFIX_ADDRESS, 16, 4, req->result,
 661                                digestsize, 1);
 662 #endif
 663
 664         req->base.complete(&req->base, err);
 665 }
 666
 667 static void ahash_done_bi(struct device *jrdev, u32 *desc, u32 err,
 668                             void *context)
 669 {
 670         struct ahash_request *req = context;
 671         struct ahash_edesc *edesc;
 672         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 673         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 674 #ifdef DEBUG
 675         struct caam_hash_state *state = ahash_request_ctx(req);
 676         int digestsize = crypto_ahash_digestsize(ahash);
 677
 678         dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
 679 #endif
 680
 681         edesc = (struct ahash_edesc *)((char *)desc -
 682                  offsetof(struct ahash_edesc, hw_desc));
 683         if (err)
 684                 caam_jr_strstatus(jrdev, err);
 685
 686         ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL);
 687         kfree(edesc);
 688
 689 #ifdef DEBUG
 690         print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
 691                        DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
 692                        ctx->ctx_len, 1);
 693         if (req->result)
 694                 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
 695                                DUMP_PREFIX_ADDRESS, 16, 4, req->result,
 696                                digestsize, 1);
 697 #endif
 698
 699         req->base.complete(&req->base, err);
 700 }
 701
 702 static void ahash_done_ctx_src(struct device *jrdev, u32 *desc, u32 err,
 703                                void *context)
 704 {
 705         struct ahash_request *req = context;
 706         struct ahash_edesc *edesc;
 707         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 708         int digestsize = crypto_ahash_digestsize(ahash);
 709 #ifdef DEBUG
 710         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 711         struct caam_hash_state *state = ahash_request_ctx(req);
 712
 713         dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
 714 #endif
 715
 716         edesc = (struct ahash_edesc *)((char *)desc -
 717                  offsetof(struct ahash_edesc, hw_desc));
 718         if (err)
 719                 caam_jr_strstatus(jrdev, err);
 720
 721         ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_TO_DEVICE);
 722         kfree(edesc);
 723
 724 #ifdef DEBUG
 725         print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
 726                        DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
 727                        ctx->ctx_len, 1);
 728         if (req->result)
 729                 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
 730                                DUMP_PREFIX_ADDRESS, 16, 4, req->result,
 731                                digestsize, 1);
 732 #endif
 733
 734         req->base.complete(&req->base, err);
 735 }
 736
 737 static void ahash_done_ctx_dst(struct device *jrdev, u32 *desc, u32 err,
 738                                void *context)
 739 {
 740         struct ahash_request *req = context;
 741         struct ahash_edesc *edesc;
 742         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 743         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 744 #ifdef DEBUG
 745         struct caam_hash_state *state = ahash_request_ctx(req);
 746         int digestsize = crypto_ahash_digestsize(ahash);
 747
 748         dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
 749 #endif
 750
 751         edesc = (struct ahash_edesc *)((char *)desc -
 752                  offsetof(struct ahash_edesc, hw_desc));
 753         if (err)
 754                 caam_jr_strstatus(jrdev, err);
 755
 756         ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_FROM_DEVICE);
 757         kfree(edesc);
 758
 759 #ifdef DEBUG
 760         print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
 761                        DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
 762                        ctx->ctx_len, 1);
 763         if (req->result)
 764                 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
 765                                DUMP_PREFIX_ADDRESS, 16, 4, req->result,
 766                                digestsize, 1);
 767 #endif
 768
 769         req->base.complete(&req->base, err);
 770 }
 771
 772 /*
 773  * Allocate an enhanced descriptor, which contains the hardware descriptor
 774  * and space for hardware scatter table containing sg_num entries.
 775  */
 776 static struct ahash_edesc *ahash_edesc_alloc(struct caam_hash_ctx *ctx,
 777                                              int sg_num, u32 *sh_desc,
 778                                              dma_addr_t sh_desc_dma,
 779                                              gfp_t flags)
 780 {
 781         struct ahash_edesc *edesc;
 782         unsigned int sg_size = sg_num * sizeof(struct sec4_sg_entry);
 783
 784         edesc = kzalloc(sizeof(*edesc) + sg_size, GFP_DMA | flags);
 785         if (!edesc) {
 786                 dev_err(ctx->jrdev, "could not allocate extended descriptor\n");
 787                 return NULL;
 788         }
 789
 790         init_job_desc_shared(edesc->hw_desc, sh_desc_dma, desc_len(sh_desc),
 791                              HDR_SHARE_DEFER | HDR_REVERSE);
 792
 793         return edesc;
 794 }
 795
 796 static int ahash_edesc_add_src(struct caam_hash_ctx *ctx,
 797                                struct ahash_edesc *edesc,
 798                                struct ahash_request *req, int nents,
 799                                unsigned int first_sg,
 800                                unsigned int first_bytes, size_t to_hash)
 801 {
 802         dma_addr_t src_dma;
 803         u32 options;
 804
 805         if (nents > 1 || first_sg) {
 806                 struct sec4_sg_entry *sg = edesc->sec4_sg;
 807                 unsigned int sgsize = sizeof(*sg) * (first_sg + nents);
 808
 809                 sg_to_sec4_sg_last(req->src, nents, sg + first_sg, 0);
 810
 811                 src_dma = dma_map_single(ctx->jrdev, sg, sgsize, DMA_TO_DEVICE);
 812                 if (dma_mapping_error(ctx->jrdev, src_dma)) {
 813                         dev_err(ctx->jrdev, "unable to map S/G table\n");
 814                         return -ENOMEM;
 815                 }
 816
 817                 edesc->sec4_sg_bytes = sgsize;
 818                 edesc->sec4_sg_dma = src_dma;
 819                 options = LDST_SGF;
 820         } else {
 821                 src_dma = sg_dma_address(req->src);
 822                 options = 0;
 823         }
 824
 825         append_seq_in_ptr(edesc->hw_desc, src_dma, first_bytes + to_hash,
 826                           options);
 827
 828         return 0;
 829 }
 830
 831 /* submit update job descriptor */
 832 static int ahash_update_ctx(struct ahash_request *req)
 833 {
 834         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 835         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 836         struct caam_hash_state *state = ahash_request_ctx(req);
 837         struct device *jrdev = ctx->jrdev;
 838         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
 839                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
 840         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
 841         int *buflen = state->current_buf ? &state->buflen_1 : &state->buflen_0;
 842         u8 *next_buf = state->current_buf ? state->buf_0 : state->buf_1;
 843         int *next_buflen = state->current_buf ? &state->buflen_0 :
 844                            &state->buflen_1, last_buflen;
 845         int in_len = *buflen + req->nbytes, to_hash;
 846         u32 *desc;
 847         int src_nents, mapped_nents, sec4_sg_bytes, sec4_sg_src_index;
 848         struct ahash_edesc *edesc;
 849         int ret = 0;
 850
 851         last_buflen = *next_buflen;
 852         *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
 853         to_hash = in_len - *next_buflen;
 854
 855         if (to_hash) {
 856                 src_nents = sg_nents_for_len(req->src,
 857                                              req->nbytes - (*next_buflen));
 858                 if (src_nents < 0) {
 859                         dev_err(jrdev, "Invalid number of src SG.\n");
 860                         return src_nents;
 861                 }
 862
 863                 if (src_nents) {
 864                         mapped_nents = dma_map_sg(jrdev, req->src, src_nents,
 865                                                   DMA_TO_DEVICE);
 866                         if (!mapped_nents) {
 867                                 dev_err(jrdev, "unable to DMA map source\n");
 868                                 return -ENOMEM;
 869                         }
 870                 } else {
 871                         mapped_nents = 0;
 872                 }
 873
 874                 sec4_sg_src_index = 1 + (*buflen ? 1 : 0);
 875                 sec4_sg_bytes = (sec4_sg_src_index + mapped_nents) *
 876                                  sizeof(struct sec4_sg_entry);
 877
 878                 /*
 879                  * allocate space for base edesc and hw desc commands,
 880                  * link tables
 881                  */
 882                 edesc = ahash_edesc_alloc(ctx, sec4_sg_src_index + mapped_nents,
 883                                           ctx->sh_desc_update,
 884                                           ctx->sh_desc_update_dma, flags);
 885                 if (!edesc) {
 886                         dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
 887                         return -ENOMEM;
 888                 }
 889
 890                 edesc->src_nents = src_nents;
 891                 edesc->sec4_sg_bytes = sec4_sg_bytes;
 892
 893                 ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
 894                                          edesc->sec4_sg, DMA_BIDIRECTIONAL);
 895                 if (ret)
 896                         goto unmap_ctx;
 897
 898                 state->buf_dma = try_buf_map_to_sec4_sg(jrdev,
 899                                                         edesc->sec4_sg + 1,
 900                                                         buf, state->buf_dma,
 901                                                         *buflen, last_buflen);
 902
 903                 if (mapped_nents) {
 904                         sg_to_sec4_sg_last(req->src, mapped_nents,
 905                                            edesc->sec4_sg + sec4_sg_src_index,
 906                                            0);
 907                         if (*next_buflen)
 908                                 scatterwalk_map_and_copy(next_buf, req->src,
 909                                                          to_hash - *buflen,
 910                                                          *next_buflen, 0);
 911                 } else {
 912                         (edesc->sec4_sg + sec4_sg_src_index - 1)->len |=
 913                                 cpu_to_caam32(SEC4_SG_LEN_FIN);
 914                 }
 915
 916                 state->current_buf = !state->current_buf;
 917
 918                 desc = edesc->hw_desc;
 919
 920                 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
 921                                                      sec4_sg_bytes,
 922                                                      DMA_TO_DEVICE);
 923                 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
 924                         dev_err(jrdev, "unable to map S/G table\n");
 925                         ret = -ENOMEM;
 926                         goto unmap_ctx;
 927                 }
 928
 929                 append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len +
 930                                        to_hash, LDST_SGF);
 931
 932                 append_seq_out_ptr(desc, state->ctx_dma, ctx->ctx_len, 0);
 933
 934 #ifdef DEBUG
 935                 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
 936                                DUMP_PREFIX_ADDRESS, 16, 4, desc,
 937                                desc_bytes(desc), 1);
 938 #endif
 939
 940                 ret = caam_jr_enqueue(jrdev, desc, ahash_done_bi, req);
 941                 if (ret)
 942                         goto unmap_ctx;
 943
 944                 ret = -EINPROGRESS;
 945         } else if (*next_buflen) {
 946                 scatterwalk_map_and_copy(buf + *buflen, req->src, 0,
 947                                          req->nbytes, 0);
 948                 *buflen = *next_buflen;
 949                 *next_buflen = last_buflen;
 950         }
 951 #ifdef DEBUG
 952         print_hex_dump(KERN_ERR, "buf@"__stringify(__LINE__)": ",
 953                        DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
 954         print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
 955                        DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
 956                        *next_buflen, 1);
 957 #endif
 958
 959         return ret;
 960  unmap_ctx:
 961         ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL);
 962         kfree(edesc);
 963         return ret;
 964 }
 965
 966 static int ahash_final_ctx(struct ahash_request *req)
 967 {
 968         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 969         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 970         struct caam_hash_state *state = ahash_request_ctx(req);
 971         struct device *jrdev = ctx->jrdev;
 972         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
 973                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
 974         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
 975         int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
 976         int last_buflen = state->current_buf ? state->buflen_0 :
 977                           state->buflen_1;
 978         u32 *desc;
 979         int sec4_sg_bytes, sec4_sg_src_index;
 980         int digestsize = crypto_ahash_digestsize(ahash);
 981         struct ahash_edesc *edesc;
 982         int ret;
 983
 984         sec4_sg_src_index = 1 + (buflen ? 1 : 0);
 985         sec4_sg_bytes = sec4_sg_src_index * sizeof(struct sec4_sg_entry);
 986
 987         /* allocate space for base edesc and hw desc commands, link tables */
 988         edesc = ahash_edesc_alloc(ctx, sec4_sg_src_index,
 989                                   ctx->sh_desc_fin, ctx->sh_desc_fin_dma,
 990                                   flags);
 991         if (!edesc)
 992                 return -ENOMEM;
 993
 994         desc = edesc->hw_desc;
 995
 996         edesc->sec4_sg_bytes = sec4_sg_bytes;
 997         edesc->src_nents = 0;
 998
 999         ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
1000                                  edesc->sec4_sg, DMA_TO_DEVICE);
1001         if (ret)
1002                 goto unmap_ctx;
1003
1004         state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1,
1005                                                 buf, state->buf_dma, buflen,
1006                                                 last_buflen);
1007         (edesc->sec4_sg + sec4_sg_src_index - 1)->len |=
1008                 cpu_to_caam32(SEC4_SG_LEN_FIN);
1009
1010         edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1011                                             sec4_sg_bytes, DMA_TO_DEVICE);
1012         if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1013                 dev_err(jrdev, "unable to map S/G table\n");
1014                 ret = -ENOMEM;
1015                 goto unmap_ctx;
1016         }
1017
1018         append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len + buflen,
1019                           LDST_SGF);
1020
1021         edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1022                                                 digestsize);
1023         if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1024                 dev_err(jrdev, "unable to map dst\n");
1025                 ret = -ENOMEM;
1026                 goto unmap_ctx;
1027         }
1028
1029 #ifdef DEBUG
1030         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1031                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1032 #endif
1033
1034         ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req);
1035         if (ret)
1036                 goto unmap_ctx;
1037
1038         return -EINPROGRESS;
1039  unmap_ctx:
1040         ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE);
1041         kfree(edesc);
1042         return ret;
1043 }
1044
1045 static int ahash_finup_ctx(struct ahash_request *req)
1046 {
1047         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1048         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1049         struct caam_hash_state *state = ahash_request_ctx(req);
1050         struct device *jrdev = ctx->jrdev;
1051         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1052                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1053         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
1054         int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
1055         int last_buflen = state->current_buf ? state->buflen_0 :
1056                           state->buflen_1;
1057         u32 *desc;
1058         int sec4_sg_src_index;
1059         int src_nents, mapped_nents;
1060         int digestsize = crypto_ahash_digestsize(ahash);
1061         struct ahash_edesc *edesc;
1062         int ret;
1063
1064         src_nents = sg_nents_for_len(req->src, req->nbytes);
1065         if (src_nents < 0) {
1066                 dev_err(jrdev, "Invalid number of src SG.\n");
1067                 return src_nents;
1068         }
1069
1070         if (src_nents) {
1071                 mapped_nents = dma_map_sg(jrdev, req->src, src_nents,
1072                                           DMA_TO_DEVICE);
1073                 if (!mapped_nents) {
1074                         dev_err(jrdev, "unable to DMA map source\n");
1075                         return -ENOMEM;
1076                 }
1077         } else {
1078                 mapped_nents = 0;
1079         }
1080
1081         sec4_sg_src_index = 1 + (buflen ? 1 : 0);
1082
1083         /* allocate space for base edesc and hw desc commands, link tables */
1084         edesc = ahash_edesc_alloc(ctx, sec4_sg_src_index + mapped_nents,
1085                                   ctx->sh_desc_finup, ctx->sh_desc_finup_dma,
1086                                   flags);
1087         if (!edesc) {
1088                 dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
1089                 return -ENOMEM;
1090         }
1091
1092         desc = edesc->hw_desc;
1093
1094         edesc->src_nents = src_nents;
1095
1096         ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
1097                                  edesc->sec4_sg, DMA_TO_DEVICE);
1098         if (ret)
1099                 goto unmap_ctx;
1100
1101         state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1,
1102                                                 buf, state->buf_dma, buflen,
1103                                                 last_buflen);
1104
1105         ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents,
1106                                   sec4_sg_src_index, ctx->ctx_len + buflen,
1107                                   req->nbytes);
1108         if (ret)
1109                 goto unmap_ctx;
1110
1111         edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1112                                                 digestsize);
1113         if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1114                 dev_err(jrdev, "unable to map dst\n");
1115                 ret = -ENOMEM;
1116                 goto unmap_ctx;
1117         }
1118
1119 #ifdef DEBUG
1120         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1121                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1122 #endif
1123
1124         ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req);
1125         if (ret)
1126                 goto unmap_ctx;
1127
1128         return -EINPROGRESS;
1129  unmap_ctx:
1130         ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE);
1131         kfree(edesc);
1132         return ret;
1133 }
1134
1135 static int ahash_digest(struct ahash_request *req)
1136 {
1137         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1138         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1139         struct device *jrdev = ctx->jrdev;
1140         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1141                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1142         u32 *desc;
1143         int digestsize = crypto_ahash_digestsize(ahash);
1144         int src_nents, mapped_nents;
1145         struct ahash_edesc *edesc;
1146         int ret;
1147
1148         src_nents = sg_nents_for_len(req->src, req->nbytes);
1149         if (src_nents < 0) {
1150                 dev_err(jrdev, "Invalid number of src SG.\n");
1151                 return src_nents;
1152         }
1153
1154         if (src_nents) {
1155                 mapped_nents = dma_map_sg(jrdev, req->src, src_nents,
1156                                           DMA_TO_DEVICE);
1157                 if (!mapped_nents) {
1158                         dev_err(jrdev, "unable to map source for DMA\n");
1159                         return -ENOMEM;
1160                 }
1161         } else {
1162                 mapped_nents = 0;
1163         }
1164
1165         /* allocate space for base edesc and hw desc commands, link tables */
1166         edesc = ahash_edesc_alloc(ctx, mapped_nents > 1 ? mapped_nents : 0,
1167                                   ctx->sh_desc_digest, ctx->sh_desc_digest_dma,
1168                                   flags);
1169         if (!edesc) {
1170                 dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
1171                 return -ENOMEM;
1172         }
1173
1174         edesc->src_nents = src_nents;
1175
1176         ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 0, 0,
1177                                   req->nbytes);
1178         if (ret) {
1179                 ahash_unmap(jrdev, edesc, req, digestsize);
1180                 kfree(edesc);
1181                 return ret;
1182         }
1183
1184         desc = edesc->hw_desc;
1185
1186         edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1187                                                 digestsize);
1188         if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1189                 dev_err(jrdev, "unable to map dst\n");
1190                 ahash_unmap(jrdev, edesc, req, digestsize);
1191                 kfree(edesc);
1192                 return -ENOMEM;
1193         }
1194
1195 #ifdef DEBUG
1196         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1197                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1198 #endif
1199
1200         ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
1201         if (!ret) {
1202                 ret = -EINPROGRESS;
1203         } else {
1204                 ahash_unmap(jrdev, edesc, req, digestsize);
1205                 kfree(edesc);
1206         }
1207
1208         return ret;
1209 }
1210
1211 /* submit ahash final if it the first job descriptor */
1212 static int ahash_final_no_ctx(struct ahash_request *req)
1213 {
1214         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1215         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1216         struct caam_hash_state *state = ahash_request_ctx(req);
1217         struct device *jrdev = ctx->jrdev;
1218         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1219                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1220         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
1221         int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
1222         u32 *desc;
1223         int digestsize = crypto_ahash_digestsize(ahash);
1224         struct ahash_edesc *edesc;
1225         int ret;
1226
1227         /* allocate space for base edesc and hw desc commands, link tables */
1228         edesc = ahash_edesc_alloc(ctx, 0, ctx->sh_desc_digest,
1229                                   ctx->sh_desc_digest_dma, flags);
1230         if (!edesc)
1231                 return -ENOMEM;
1232
1233         desc = edesc->hw_desc;
1234
1235         if (buflen) {
1236                 state->buf_dma = dma_map_single(jrdev, buf, buflen,
1237                                                 DMA_TO_DEVICE);
1238                 if (dma_mapping_error(jrdev, state->buf_dma)) {
1239                         dev_err(jrdev, "unable to map src\n");
1240                         goto unmap;
1241                 }
1242
1243                 append_seq_in_ptr(desc, state->buf_dma, buflen, 0);
1244         }
1245
1246         edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1247                                                 digestsize);
1248         if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1249                 dev_err(jrdev, "unable to map dst\n");
1250                 goto unmap;
1251         }
1252         edesc->src_nents = 0;
1253
1254 #ifdef DEBUG
1255         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1256                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1257 #endif
1258
1259         ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
1260         if (!ret) {
1261                 ret = -EINPROGRESS;
1262         } else {
1263                 ahash_unmap(jrdev, edesc, req, digestsize);
1264                 kfree(edesc);
1265         }
1266
1267         return ret;
1268  unmap:
1269         ahash_unmap(jrdev, edesc, req, digestsize);
1270         kfree(edesc);
1271         return -ENOMEM;
1272
1273 }
1274
1275 /* submit ahash update if it the first job descriptor after update */
1276 static int ahash_update_no_ctx(struct ahash_request *req)
1277 {
1278         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1279         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1280         struct caam_hash_state *state = ahash_request_ctx(req);
1281         struct device *jrdev = ctx->jrdev;
1282         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1283                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1284         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
1285         int *buflen = state->current_buf ? &state->buflen_1 : &state->buflen_0;
1286         u8 *next_buf = state->current_buf ? state->buf_0 : state->buf_1;
1287         int *next_buflen = state->current_buf ? &state->buflen_0 :
1288                            &state->buflen_1;
1289         int in_len = *buflen + req->nbytes, to_hash;
1290         int sec4_sg_bytes, src_nents, mapped_nents;
1291         struct ahash_edesc *edesc;
1292         u32 *desc;
1293         int ret = 0;
1294
1295         *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
1296         to_hash = in_len - *next_buflen;
1297
1298         if (to_hash) {
1299                 src_nents = sg_nents_for_len(req->src,
1300                                              req->nbytes - *next_buflen);
1301                 if (src_nents < 0) {
1302                         dev_err(jrdev, "Invalid number of src SG.\n");
1303                         return src_nents;
1304                 }
1305
1306                 if (src_nents) {
1307                         mapped_nents = dma_map_sg(jrdev, req->src, src_nents,
1308                                                   DMA_TO_DEVICE);
1309                         if (!mapped_nents) {
1310                                 dev_err(jrdev, "unable to DMA map source\n");
1311                                 return -ENOMEM;
1312                         }
1313                 } else {
1314                         mapped_nents = 0;
1315                 }
1316
1317                 sec4_sg_bytes = (1 + mapped_nents) *
1318                                 sizeof(struct sec4_sg_entry);
1319
1320                 /*
1321                  * allocate space for base edesc and hw desc commands,
1322                  * link tables
1323                  */
1324                 edesc = ahash_edesc_alloc(ctx, 1 + mapped_nents,
1325                                           ctx->sh_desc_update_first,
1326                                           ctx->sh_desc_update_first_dma,
1327                                           flags);
1328                 if (!edesc) {
1329                         dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
1330                         return -ENOMEM;
1331                 }
1332
1333                 edesc->src_nents = src_nents;
1334                 edesc->sec4_sg_bytes = sec4_sg_bytes;
1335                 edesc->dst_dma = 0;
1336
1337                 state->buf_dma = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg,
1338                                                     buf, *buflen);
1339                 sg_to_sec4_sg_last(req->src, mapped_nents,
1340                                    edesc->sec4_sg + 1, 0);
1341
1342                 if (*next_buflen) {
1343                         scatterwalk_map_and_copy(next_buf, req->src,
1344                                                  to_hash - *buflen,
1345                                                  *next_buflen, 0);
1346                 }
1347
1348                 state->current_buf = !state->current_buf;
1349
1350                 desc = edesc->hw_desc;
1351
1352                 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1353                                                     sec4_sg_bytes,
1354                                                     DMA_TO_DEVICE);
1355                 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1356                         dev_err(jrdev, "unable to map S/G table\n");
1357                         ret = -ENOMEM;
1358                         goto unmap_ctx;
1359                 }
1360
1361                 append_seq_in_ptr(desc, edesc->sec4_sg_dma, to_hash, LDST_SGF);
1362
1363                 ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
1364                 if (ret)
1365                         goto unmap_ctx;
1366
1367 #ifdef DEBUG
1368                 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1369                                DUMP_PREFIX_ADDRESS, 16, 4, desc,
1370                                desc_bytes(desc), 1);
1371 #endif
1372
1373                 ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst, req);
1374                 if (ret)
1375                         goto unmap_ctx;
1376
1377                 ret = -EINPROGRESS;
1378                 state->update = ahash_update_ctx;
1379                 state->finup = ahash_finup_ctx;
1380                 state->final = ahash_final_ctx;
1381         } else if (*next_buflen) {
1382                 scatterwalk_map_and_copy(buf + *buflen, req->src, 0,
1383                                          req->nbytes, 0);
1384                 *buflen = *next_buflen;
1385                 *next_buflen = 0;
1386         }
1387 #ifdef DEBUG
1388         print_hex_dump(KERN_ERR, "buf@"__stringify(__LINE__)": ",
1389                        DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
1390         print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
1391                        DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
1392                        *next_buflen, 1);
1393 #endif
1394
1395         return ret;
1396  unmap_ctx:
1397         ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE);
1398         kfree(edesc);
1399         return ret;
1400 }
1401
1402 /* submit ahash finup if it the first job descriptor after update */
1403 static int ahash_finup_no_ctx(struct ahash_request *req)
1404 {
1405         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1406         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1407         struct caam_hash_state *state = ahash_request_ctx(req);
1408         struct device *jrdev = ctx->jrdev;
1409         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1410                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1411         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
1412         int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
1413         int last_buflen = state->current_buf ? state->buflen_0 :
1414                           state->buflen_1;
1415         u32 *desc;
1416         int sec4_sg_bytes, sec4_sg_src_index, src_nents, mapped_nents;
1417         int digestsize = crypto_ahash_digestsize(ahash);
1418         struct ahash_edesc *edesc;
1419         int ret;
1420
1421         src_nents = sg_nents_for_len(req->src, req->nbytes);
1422         if (src_nents < 0) {
1423                 dev_err(jrdev, "Invalid number of src SG.\n");
1424                 return src_nents;
1425         }
1426
1427         if (src_nents) {
1428                 mapped_nents = dma_map_sg(jrdev, req->src, src_nents,
1429                                           DMA_TO_DEVICE);
1430                 if (!mapped_nents) {
1431                         dev_err(jrdev, "unable to DMA map source\n");
1432                         return -ENOMEM;
1433                 }
1434         } else {
1435                 mapped_nents = 0;
1436         }
1437
1438         sec4_sg_src_index = 2;
1439         sec4_sg_bytes = (sec4_sg_src_index + mapped_nents) *
1440                          sizeof(struct sec4_sg_entry);
1441
1442         /* allocate space for base edesc and hw desc commands, link tables */
1443         edesc = ahash_edesc_alloc(ctx, sec4_sg_src_index + mapped_nents,
1444                                   ctx->sh_desc_digest, ctx->sh_desc_digest_dma,
1445                                   flags);
1446         if (!edesc) {
1447                 dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
1448                 return -ENOMEM;
1449         }
1450
1451         desc = edesc->hw_desc;
1452
1453         edesc->src_nents = src_nents;
1454         edesc->sec4_sg_bytes = sec4_sg_bytes;
1455
1456         state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, buf,
1457                                                 state->buf_dma, buflen,
1458                                                 last_buflen);
1459
1460         ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 1, buflen,
1461                                   req->nbytes);
1462         if (ret) {
1463                 dev_err(jrdev, "unable to map S/G table\n");
1464                 goto unmap;
1465         }
1466
1467         edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1468                                                 digestsize);
1469         if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1470                 dev_err(jrdev, "unable to map dst\n");
1471                 goto unmap;
1472         }
1473
1474 #ifdef DEBUG
1475         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1476                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1477 #endif
1478
1479         ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
1480         if (!ret) {
1481                 ret = -EINPROGRESS;
1482         } else {
1483                 ahash_unmap(jrdev, edesc, req, digestsize);
1484                 kfree(edesc);
1485         }
1486
1487         return ret;
1488  unmap:
1489         ahash_unmap(jrdev, edesc, req, digestsize);
1490         kfree(edesc);
1491         return -ENOMEM;
1492
1493 }
1494
1495 /* submit first update job descriptor after init */
1496 static int ahash_update_first(struct ahash_request *req)
1497 {
1498         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1499         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1500         struct caam_hash_state *state = ahash_request_ctx(req);
1501         struct device *jrdev = ctx->jrdev;
1502         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1503                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1504         u8 *next_buf = state->current_buf ? state->buf_1 : state->buf_0;
1505         int *next_buflen = state->current_buf ?
1506                 &state->buflen_1 : &state->buflen_0;
1507         int to_hash;
1508         u32 *desc;
1509         int src_nents, mapped_nents;
1510         struct ahash_edesc *edesc;
1511         int ret = 0;
1512
1513         *next_buflen = req->nbytes & (crypto_tfm_alg_blocksize(&ahash->base) -
1514                                       1);
1515         to_hash = req->nbytes - *next_buflen;
1516
1517         if (to_hash) {
1518                 src_nents = sg_nents_for_len(req->src,
1519                                              req->nbytes - *next_buflen);
1520                 if (src_nents < 0) {
1521                         dev_err(jrdev, "Invalid number of src SG.\n");
1522                         return src_nents;
1523                 }
1524
1525                 if (src_nents) {
1526                         mapped_nents = dma_map_sg(jrdev, req->src, src_nents,
1527                                                   DMA_TO_DEVICE);
1528                         if (!mapped_nents) {
1529                                 dev_err(jrdev, "unable to map source for DMA\n");
1530                                 return -ENOMEM;
1531                         }
1532                 } else {
1533                         mapped_nents = 0;
1534                 }
1535
1536                 /*
1537                  * allocate space for base edesc and hw desc commands,
1538                  * link tables
1539                  */
1540                 edesc = ahash_edesc_alloc(ctx, mapped_nents > 1 ?
1541                                           mapped_nents : 0,
1542                                           ctx->sh_desc_update_first,
1543                                           ctx->sh_desc_update_first_dma,
1544                                           flags);
1545                 if (!edesc) {
1546                         dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
1547                         return -ENOMEM;
1548                 }
1549
1550                 edesc->src_nents = src_nents;
1551                 edesc->dst_dma = 0;
1552
1553                 ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 0, 0,
1554                                           to_hash);
1555                 if (ret)
1556                         goto unmap_ctx;
1557
1558                 if (*next_buflen)
1559                         scatterwalk_map_and_copy(next_buf, req->src, to_hash,
1560                                                  *next_buflen, 0);
1561
1562                 desc = edesc->hw_desc;
1563
1564                 ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
1565                 if (ret)
1566                         goto unmap_ctx;
1567
1568 #ifdef DEBUG
1569                 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1570                                DUMP_PREFIX_ADDRESS, 16, 4, desc,
1571                                desc_bytes(desc), 1);
1572 #endif
1573
1574                 ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst, req);
1575                 if (ret)
1576                         goto unmap_ctx;
1577
1578                 ret = -EINPROGRESS;
1579                 state->update = ahash_update_ctx;
1580                 state->finup = ahash_finup_ctx;
1581                 state->final = ahash_final_ctx;
1582         } else if (*next_buflen) {
1583                 state->update = ahash_update_no_ctx;
1584                 state->finup = ahash_finup_no_ctx;
1585                 state->final = ahash_final_no_ctx;
1586                 scatterwalk_map_and_copy(next_buf, req->src, 0,
1587                                          req->nbytes, 0);
1588         }
1589 #ifdef DEBUG
1590         print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
1591                        DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
1592                        *next_buflen, 1);
1593 #endif
1594
1595         return ret;
1596  unmap_ctx:
1597         ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE);
1598         kfree(edesc);
1599         return ret;
1600 }
1601
1602 static int ahash_finup_first(struct ahash_request *req)
1603 {
1604         return ahash_digest(req);
1605 }
1606
1607 static int ahash_init(struct ahash_request *req)
1608 {
1609         struct caam_hash_state *state = ahash_request_ctx(req);
1610
1611         state->update = ahash_update_first;
1612         state->finup = ahash_finup_first;
1613         state->final = ahash_final_no_ctx;
1614
1615         state->ctx_dma = 0;
1616         state->current_buf = 0;
1617         state->buf_dma = 0;
1618         state->buflen_0 = 0;
1619         state->buflen_1 = 0;
1620
1621         return 0;
1622 }
1623
1624 static int ahash_update(struct ahash_request *req)
1625 {
1626         struct caam_hash_state *state = ahash_request_ctx(req);
1627
1628         return state->update(req);
1629 }
1630
1631 static int ahash_finup(struct ahash_request *req)
1632 {
1633         struct caam_hash_state *state = ahash_request_ctx(req);
1634
1635         return state->finup(req);
1636 }
1637
1638 static int ahash_final(struct ahash_request *req)
1639 {
1640         struct caam_hash_state *state = ahash_request_ctx(req);
1641
1642         return state->final(req);
1643 }
1644
1645 static int ahash_export(struct ahash_request *req, void *out)
1646 {
1647         struct caam_hash_state *state = ahash_request_ctx(req);
1648         struct caam_export_state *export = out;
1649         int len;
1650         u8 *buf;
1651
1652         if (state->current_buf) {
1653                 buf = state->buf_1;
1654                 len = state->buflen_1;
1655         } else {
1656                 buf = state->buf_0;
1657                 len = state->buflen_0;
1658         }
1659
1660         memcpy(export->buf, buf, len);
1661         memcpy(export->caam_ctx, state->caam_ctx, sizeof(export->caam_ctx));
1662         export->buflen = len;
1663         export->update = state->update;
1664         export->final = state->final;
1665         export->finup = state->finup;
1666
1667         return 0;
1668 }
1669
1670 static int ahash_import(struct ahash_request *req, const void *in)
1671 {
1672         struct caam_hash_state *state = ahash_request_ctx(req);
1673         const struct caam_export_state *export = in;
1674
1675         memset(state, 0, sizeof(*state));
1676         memcpy(state->buf_0, export->buf, export->buflen);
1677         memcpy(state->caam_ctx, export->caam_ctx, sizeof(state->caam_ctx));
1678         state->buflen_0 = export->buflen;
1679         state->update = export->update;
1680         state->final = export->final;
1681         state->finup = export->finup;
1682
1683         return 0;
1684 }
1685
1686 struct caam_hash_template {
1687         char name[CRYPTO_MAX_ALG_NAME];
1688         char driver_name[CRYPTO_MAX_ALG_NAME];
1689         char hmac_name[CRYPTO_MAX_ALG_NAME];
1690         char hmac_driver_name[CRYPTO_MAX_ALG_NAME];
1691         unsigned int blocksize;
1692         struct ahash_alg template_ahash;
1693         u32 alg_type;
1694         u32 alg_op;
1695 };
1696
1697 /* ahash descriptors */
1698 static struct caam_hash_template driver_hash[] = {
1699         {
1700                 .name = "sha1",
1701                 .driver_name = "sha1-caam",
1702                 .hmac_name = "hmac(sha1)",
1703                 .hmac_driver_name = "hmac-sha1-caam",
1704                 .blocksize = SHA1_BLOCK_SIZE,
1705                 .template_ahash = {
1706                         .init = ahash_init,
1707                         .update = ahash_update,
1708                         .final = ahash_final,
1709                         .finup = ahash_finup,
1710                         .digest = ahash_digest,
1711                         .export = ahash_export,
1712                         .import = ahash_import,
1713                         .setkey = ahash_setkey,
1714                         .halg = {
1715                                 .digestsize = SHA1_DIGEST_SIZE,
1716                                 .statesize = sizeof(struct caam_export_state),
1717                         },
1718                 },
1719                 .alg_type = OP_ALG_ALGSEL_SHA1,
1720                 .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
1721         }, {
1722                 .name = "sha224",
1723                 .driver_name = "sha224-caam",
1724                 .hmac_name = "hmac(sha224)",
1725                 .hmac_driver_name = "hmac-sha224-caam",
1726                 .blocksize = SHA224_BLOCK_SIZE,
1727                 .template_ahash = {
1728                         .init = ahash_init,
1729                         .update = ahash_update,
1730                         .final = ahash_final,
1731                         .finup = ahash_finup,
1732                         .digest = ahash_digest,
1733                         .export = ahash_export,
1734                         .import = ahash_import,
1735                         .setkey = ahash_setkey,
1736                         .halg = {
1737                                 .digestsize = SHA224_DIGEST_SIZE,
1738                                 .statesize = sizeof(struct caam_export_state),
1739                         },
1740                 },
1741                 .alg_type = OP_ALG_ALGSEL_SHA224,
1742                 .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
1743         }, {
1744                 .name = "sha256",
1745                 .driver_name = "sha256-caam",
1746                 .hmac_name = "hmac(sha256)",
1747                 .hmac_driver_name = "hmac-sha256-caam",
1748                 .blocksize = SHA256_BLOCK_SIZE,
1749                 .template_ahash = {
1750                         .init = ahash_init,
1751                         .update = ahash_update,
1752                         .final = ahash_final,
1753                         .finup = ahash_finup,
1754                         .digest = ahash_digest,
1755                         .export = ahash_export,
1756                         .import = ahash_import,
1757                         .setkey = ahash_setkey,
1758                         .halg = {
1759                                 .digestsize = SHA256_DIGEST_SIZE,
1760                                 .statesize = sizeof(struct caam_export_state),
1761                         },
1762                 },
1763                 .alg_type = OP_ALG_ALGSEL_SHA256,
1764                 .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
1765         }, {
1766                 .name = "sha384",
1767                 .driver_name = "sha384-caam",
1768                 .hmac_name = "hmac(sha384)",
1769                 .hmac_driver_name = "hmac-sha384-caam",
1770                 .blocksize = SHA384_BLOCK_SIZE,
1771                 .template_ahash = {
1772                         .init = ahash_init,
1773                         .update = ahash_update,
1774                         .final = ahash_final,
1775                         .finup = ahash_finup,
1776                         .digest = ahash_digest,
1777                         .export = ahash_export,
1778                         .import = ahash_import,
1779                         .setkey = ahash_setkey,
1780                         .halg = {
1781                                 .digestsize = SHA384_DIGEST_SIZE,
1782                                 .statesize = sizeof(struct caam_export_state),
1783                         },
1784                 },
1785                 .alg_type = OP_ALG_ALGSEL_SHA384,
1786                 .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
1787         }, {
1788                 .name = "sha512",
1789                 .driver_name = "sha512-caam",
1790                 .hmac_name = "hmac(sha512)",
1791                 .hmac_driver_name = "hmac-sha512-caam",
1792                 .blocksize = SHA512_BLOCK_SIZE,
1793                 .template_ahash = {
1794                         .init = ahash_init,
1795                         .update = ahash_update,
1796                         .final = ahash_final,
1797                         .finup = ahash_finup,
1798                         .digest = ahash_digest,
1799                         .export = ahash_export,
1800                         .import = ahash_import,
1801                         .setkey = ahash_setkey,
1802                         .halg = {
1803                                 .digestsize = SHA512_DIGEST_SIZE,
1804                                 .statesize = sizeof(struct caam_export_state),
1805                         },
1806                 },
1807                 .alg_type = OP_ALG_ALGSEL_SHA512,
1808                 .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
1809         }, {
1810                 .name = "md5",
1811                 .driver_name = "md5-caam",
1812                 .hmac_name = "hmac(md5)",
1813                 .hmac_driver_name = "hmac-md5-caam",
1814                 .blocksize = MD5_BLOCK_WORDS * 4,
1815                 .template_ahash = {
1816                         .init = ahash_init,
1817                         .update = ahash_update,
1818                         .final = ahash_final,
1819                         .finup = ahash_finup,
1820                         .digest = ahash_digest,
1821                         .export = ahash_export,
1822                         .import = ahash_import,
1823                         .setkey = ahash_setkey,
1824                         .halg = {
1825                                 .digestsize = MD5_DIGEST_SIZE,
1826                                 .statesize = sizeof(struct caam_export_state),
1827                         },
1828                 },
1829                 .alg_type = OP_ALG_ALGSEL_MD5,
1830                 .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
1831         },
1832 };
1833
1834 struct caam_hash_alg {
1835         struct list_head entry;
1836         int alg_type;
1837         int alg_op;
1838         struct ahash_alg ahash_alg;
1839 };
1840
1841 static int caam_hash_cra_init(struct crypto_tfm *tfm)
1842 {
1843         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
1844         struct crypto_alg *base = tfm->__crt_alg;
1845         struct hash_alg_common *halg =
1846                  container_of(base, struct hash_alg_common, base);
1847         struct ahash_alg *alg =
1848                  container_of(halg, struct ahash_alg, halg);
1849         struct caam_hash_alg *caam_hash =
1850                  container_of(alg, struct caam_hash_alg, ahash_alg);
1851         struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
1852         /* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */
1853         static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE,
1854                                          HASH_MSG_LEN + SHA1_DIGEST_SIZE,
1855                                          HASH_MSG_LEN + 32,
1856                                          HASH_MSG_LEN + SHA256_DIGEST_SIZE,
1857                                          HASH_MSG_LEN + 64,
1858                                          HASH_MSG_LEN + SHA512_DIGEST_SIZE };
1859
1860         /*
1861          * Get a Job ring from Job Ring driver to ensure in-order
1862          * crypto request processing per tfm
1863          */
1864         ctx->jrdev = caam_jr_alloc();
1865         if (IS_ERR(ctx->jrdev)) {
1866                 pr_err("Job Ring Device allocation for transform failed\n");
1867                 return PTR_ERR(ctx->jrdev);
1868         }
1869         /* copy descriptor header template value */
1870         ctx->alg_type = OP_TYPE_CLASS2_ALG | caam_hash->alg_type;
1871         ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_hash->alg_op;
1872
1873         ctx->ctx_len = runninglen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
1874                                   OP_ALG_ALGSEL_SHIFT];
1875
1876         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1877                                  sizeof(struct caam_hash_state));
1878         return ahash_set_sh_desc(ahash);
1879 }
1880
1881 static void caam_hash_cra_exit(struct crypto_tfm *tfm)
1882 {
1883         struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
1884
1885         if (ctx->sh_desc_update_dma &&
1886             !dma_mapping_error(ctx->jrdev, ctx->sh_desc_update_dma))
1887                 dma_unmap_single(ctx->jrdev, ctx->sh_desc_update_dma,
1888                                  desc_bytes(ctx->sh_desc_update),
1889                                  DMA_TO_DEVICE);
1890         if (ctx->sh_desc_update_first_dma &&
1891             !dma_mapping_error(ctx->jrdev, ctx->sh_desc_update_first_dma))
1892                 dma_unmap_single(ctx->jrdev, ctx->sh_desc_update_first_dma,
1893                                  desc_bytes(ctx->sh_desc_update_first),
1894                                  DMA_TO_DEVICE);
1895         if (ctx->sh_desc_fin_dma &&
1896             !dma_mapping_error(ctx->jrdev, ctx->sh_desc_fin_dma))
1897                 dma_unmap_single(ctx->jrdev, ctx->sh_desc_fin_dma,
1898                                  desc_bytes(ctx->sh_desc_fin), DMA_TO_DEVICE);
1899         if (ctx->sh_desc_digest_dma &&
1900             !dma_mapping_error(ctx->jrdev, ctx->sh_desc_digest_dma))
1901                 dma_unmap_single(ctx->jrdev, ctx->sh_desc_digest_dma,
1902                                  desc_bytes(ctx->sh_desc_digest),
1903                                  DMA_TO_DEVICE);
1904         if (ctx->sh_desc_finup_dma &&
1905             !dma_mapping_error(ctx->jrdev, ctx->sh_desc_finup_dma))
1906                 dma_unmap_single(ctx->jrdev, ctx->sh_desc_finup_dma,
1907                                  desc_bytes(ctx->sh_desc_finup), DMA_TO_DEVICE);
1908
1909         caam_jr_free(ctx->jrdev);
1910 }
1911
1912 static void __exit caam_algapi_hash_exit(void)
1913 {
1914         struct caam_hash_alg *t_alg, *n;
1915
1916         if (!hash_list.next)
1917                 return;
1918
1919         list_for_each_entry_safe(t_alg, n, &hash_list, entry) {
1920                 crypto_unregister_ahash(&t_alg->ahash_alg);
1921                 list_del(&t_alg->entry);
1922                 kfree(t_alg);
1923         }
1924 }
1925
1926 static struct caam_hash_alg *
1927 caam_hash_alloc(struct caam_hash_template *template,
1928                 bool keyed)
1929 {
1930         struct caam_hash_alg *t_alg;
1931         struct ahash_alg *halg;
1932         struct crypto_alg *alg;
1933
1934         t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
1935         if (!t_alg) {
1936                 pr_err("failed to allocate t_alg\n");
1937                 return ERR_PTR(-ENOMEM);
1938         }
1939
1940         t_alg->ahash_alg = template->template_ahash;
1941         halg = &t_alg->ahash_alg;
1942         alg = &halg->halg.base;
1943
1944         if (keyed) {
1945                 snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
1946                          template->hmac_name);
1947                 snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1948                          template->hmac_driver_name);
1949         } else {
1950                 snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
1951                          template->name);
1952                 snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1953                          template->driver_name);
1954                 t_alg->ahash_alg.setkey = NULL;
1955         }
1956         alg->cra_module = THIS_MODULE;
1957         alg->cra_init = caam_hash_cra_init;
1958         alg->cra_exit = caam_hash_cra_exit;
1959         alg->cra_ctxsize = sizeof(struct caam_hash_ctx);
1960         alg->cra_priority = CAAM_CRA_PRIORITY;
1961         alg->cra_blocksize = template->blocksize;
1962         alg->cra_alignmask = 0;
1963         alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_TYPE_AHASH;
1964         alg->cra_type = &crypto_ahash_type;
1965
1966         t_alg->alg_type = template->alg_type;
1967         t_alg->alg_op = template->alg_op;
1968
1969         return t_alg;
1970 }
1971
1972 static int __init caam_algapi_hash_init(void)
1973 {
1974         struct device_node *dev_node;
1975         struct platform_device *pdev;
1976         struct device *ctrldev;
1977         int i = 0, err = 0;
1978         struct caam_drv_private *priv;
1979         unsigned int md_limit = SHA512_DIGEST_SIZE;
1980         u32 cha_inst, cha_vid;
1981
1982         dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
1983         if (!dev_node) {
1984                 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
1985                 if (!dev_node)
1986                         return -ENODEV;
1987         }
1988
1989         pdev = of_find_device_by_node(dev_node);
1990         if (!pdev) {
1991                 of_node_put(dev_node);
1992                 return -ENODEV;
1993         }
1994
1995         ctrldev = &pdev->dev;
1996         priv = dev_get_drvdata(ctrldev);
1997         of_node_put(dev_node);
1998
1999         /*
2000          * If priv is NULL, it's probably because the caam driver wasn't
2001          * properly initialized (e.g. RNG4 init failed). Thus, bail out here.
2002          */
2003         if (!priv)
2004                 return -ENODEV;
2005
2006         /*
2007          * Register crypto algorithms the device supports.  First, identify
2008          * presence and attributes of MD block.
2009          */
2010         cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
2011         cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
2012
2013         /*
2014          * Skip registration of any hashing algorithms if MD block
2015          * is not present.
2016          */
2017         if (!((cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT))
2018                 return -ENODEV;
2019
2020         /* Limit digest size based on LP256 */
2021         if ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256)
2022                 md_limit = SHA256_DIGEST_SIZE;
2023
2024         INIT_LIST_HEAD(&hash_list);
2025
2026         /* register crypto algorithms the device supports */
2027         for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
2028                 struct caam_hash_alg *t_alg;
2029                 struct caam_hash_template *alg = driver_hash + i;
2030
2031                 /* If MD size is not supported by device, skip registration */
2032                 if (alg->template_ahash.halg.digestsize > md_limit)
2033                         continue;
2034
2035                 /* register hmac version */
2036                 t_alg = caam_hash_alloc(alg, true);
2037                 if (IS_ERR(t_alg)) {
2038                         err = PTR_ERR(t_alg);
2039                         pr_warn("%s alg allocation failed\n", alg->driver_name);
2040                         continue;
2041                 }
2042
2043                 err = crypto_register_ahash(&t_alg->ahash_alg);
2044                 if (err) {
2045                         pr_warn("%s alg registration failed: %d\n",
2046                                 t_alg->ahash_alg.halg.base.cra_driver_name,
2047                                 err);
2048                         kfree(t_alg);
2049                 } else
2050                         list_add_tail(&t_alg->entry, &hash_list);
2051
2052                 /* register unkeyed version */
2053                 t_alg = caam_hash_alloc(alg, false);
2054                 if (IS_ERR(t_alg)) {
2055                         err = PTR_ERR(t_alg);
2056                         pr_warn("%s alg allocation failed\n", alg->driver_name);
2057                         continue;
2058                 }
2059
2060                 err = crypto_register_ahash(&t_alg->ahash_alg);
2061                 if (err) {
2062                         pr_warn("%s alg registration failed: %d\n",
2063                                 t_alg->ahash_alg.halg.base.cra_driver_name,
2064                                 err);
2065                         kfree(t_alg);
2066                 } else
2067                         list_add_tail(&t_alg->entry, &hash_list);
2068         }
2069
2070         return err;
2071 }
2072
2073 module_init(caam_algapi_hash_init);
2074 module_exit(caam_algapi_hash_exit);
2075
2076 MODULE_LICENSE("GPL");
2077 MODULE_DESCRIPTION("FSL CAAM support for ahash functions of crypto API");
2078 MODULE_AUTHOR("Freescale Semiconductor - NMG");