4 * Support for ATMEL AES HW acceleration.
6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
7 * Author: Nicolas Royer <nicolas@eukrea.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
13 * Some ideas are from omap-aes.c driver.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
23 #include <linux/hw_random.h>
24 #include <linux/platform_device.h>
26 #include <linux/device.h>
27 #include <linux/init.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/scatterlist.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/of_device.h>
34 #include <linux/delay.h>
35 #include <linux/crypto.h>
36 #include <crypto/scatterwalk.h>
37 #include <crypto/algapi.h>
38 #include <crypto/aes.h>
39 #include <crypto/gcm.h>
40 #include <crypto/xts.h>
41 #include <crypto/internal/aead.h>
42 #include <linux/platform_data/crypto-atmel.h>
43 #include <dt-bindings/dma/at91.h>
44 #include "atmel-aes-regs.h"
45 #include "atmel-authenc.h"
47 #define ATMEL_AES_PRIORITY 300
49 #define ATMEL_AES_BUFFER_ORDER 2
50 #define ATMEL_AES_BUFFER_SIZE (PAGE_SIZE << ATMEL_AES_BUFFER_ORDER)
52 #define CFB8_BLOCK_SIZE 1
53 #define CFB16_BLOCK_SIZE 2
54 #define CFB32_BLOCK_SIZE 4
55 #define CFB64_BLOCK_SIZE 8
57 #define SIZE_IN_WORDS(x) ((x) >> 2)
60 /* Reserve bits [18:16] [14:12] [1:0] for mode (same as for AES_MR) */
61 #define AES_FLAGS_ENCRYPT AES_MR_CYPHER_ENC
62 #define AES_FLAGS_GTAGEN AES_MR_GTAGEN
63 #define AES_FLAGS_OPMODE_MASK (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK)
64 #define AES_FLAGS_ECB AES_MR_OPMOD_ECB
65 #define AES_FLAGS_CBC AES_MR_OPMOD_CBC
66 #define AES_FLAGS_OFB AES_MR_OPMOD_OFB
67 #define AES_FLAGS_CFB128 (AES_MR_OPMOD_CFB | AES_MR_CFBS_128b)
68 #define AES_FLAGS_CFB64 (AES_MR_OPMOD_CFB | AES_MR_CFBS_64b)
69 #define AES_FLAGS_CFB32 (AES_MR_OPMOD_CFB | AES_MR_CFBS_32b)
70 #define AES_FLAGS_CFB16 (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b)
71 #define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)
72 #define AES_FLAGS_CTR AES_MR_OPMOD_CTR
73 #define AES_FLAGS_GCM AES_MR_OPMOD_GCM
74 #define AES_FLAGS_XTS AES_MR_OPMOD_XTS
76 #define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \
80 #define AES_FLAGS_BUSY BIT(3)
81 #define AES_FLAGS_DUMP_REG BIT(4)
82 #define AES_FLAGS_OWN_SHA BIT(5)
84 #define AES_FLAGS_PERSISTENT AES_FLAGS_BUSY
86 #define ATMEL_AES_QUEUE_LENGTH 50
88 #define ATMEL_AES_DMA_THRESHOLD 256
91 struct atmel_aes_caps {
100 struct atmel_aes_dev;
103 typedef int (*atmel_aes_fn_t)(struct atmel_aes_dev *);
106 struct atmel_aes_base_ctx {
107 struct atmel_aes_dev *dd;
108 atmel_aes_fn_t start;
110 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
115 struct atmel_aes_ctx {
116 struct atmel_aes_base_ctx base;
119 struct atmel_aes_ctr_ctx {
120 struct atmel_aes_base_ctx base;
122 u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
124 struct scatterlist src[2];
125 struct scatterlist dst[2];
128 struct atmel_aes_gcm_ctx {
129 struct atmel_aes_base_ctx base;
131 struct scatterlist src[2];
132 struct scatterlist dst[2];
134 u32 j0[AES_BLOCK_SIZE / sizeof(u32)];
135 u32 tag[AES_BLOCK_SIZE / sizeof(u32)];
136 u32 ghash[AES_BLOCK_SIZE / sizeof(u32)];
141 atmel_aes_fn_t ghash_resume;
144 struct atmel_aes_xts_ctx {
145 struct atmel_aes_base_ctx base;
147 u32 key2[AES_KEYSIZE_256 / sizeof(u32)];
150 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
151 struct atmel_aes_authenc_ctx {
152 struct atmel_aes_base_ctx base;
153 struct atmel_sha_authenc_ctx *auth;
157 struct atmel_aes_reqctx {
159 u32 lastc[AES_BLOCK_SIZE / sizeof(u32)];
162 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
163 struct atmel_aes_authenc_reqctx {
164 struct atmel_aes_reqctx base;
166 struct scatterlist src[2];
167 struct scatterlist dst[2];
169 u32 digest[SHA512_DIGEST_SIZE / sizeof(u32)];
171 /* auth_req MUST be place last. */
172 struct ahash_request auth_req;
176 struct atmel_aes_dma {
177 struct dma_chan *chan;
178 struct scatterlist *sg;
180 unsigned int remainder;
184 struct atmel_aes_dev {
185 struct list_head list;
186 unsigned long phys_base;
187 void __iomem *io_base;
189 struct crypto_async_request *areq;
190 struct atmel_aes_base_ctx *ctx;
193 atmel_aes_fn_t resume;
194 atmel_aes_fn_t cpu_transfer_complete;
203 struct crypto_queue queue;
205 struct tasklet_struct done_task;
206 struct tasklet_struct queue_task;
212 struct atmel_aes_dma src;
213 struct atmel_aes_dma dst;
217 struct scatterlist aligned_sg;
218 struct scatterlist *real_dst;
220 struct atmel_aes_caps caps;
225 struct atmel_aes_drv {
226 struct list_head dev_list;
230 static struct atmel_aes_drv atmel_aes = {
231 .dev_list = LIST_HEAD_INIT(atmel_aes.dev_list),
232 .lock = __SPIN_LOCK_UNLOCKED(atmel_aes.lock),
236 static const char *atmel_aes_reg_name(u32 offset, char *tmp, size_t sz)
265 snprintf(tmp, sz, "KEYWR[%u]", (offset - AES_KEYWR(0)) >> 2);
272 snprintf(tmp, sz, "IDATAR[%u]", (offset - AES_IDATAR(0)) >> 2);
279 snprintf(tmp, sz, "ODATAR[%u]", (offset - AES_ODATAR(0)) >> 2);
286 snprintf(tmp, sz, "IVR[%u]", (offset - AES_IVR(0)) >> 2);
299 snprintf(tmp, sz, "GHASHR[%u]", (offset - AES_GHASHR(0)) >> 2);
306 snprintf(tmp, sz, "TAGR[%u]", (offset - AES_TAGR(0)) >> 2);
316 snprintf(tmp, sz, "GCMHR[%u]", (offset - AES_GCMHR(0)) >> 2);
326 snprintf(tmp, sz, "TWR[%u]", (offset - AES_TWR(0)) >> 2);
333 snprintf(tmp, sz, "ALPHAR[%u]", (offset - AES_ALPHAR(0)) >> 2);
337 snprintf(tmp, sz, "0x%02x", offset);
343 #endif /* VERBOSE_DEBUG */
345 /* Shared functions */
347 static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset)
349 u32 value = readl_relaxed(dd->io_base + offset);
352 if (dd->flags & AES_FLAGS_DUMP_REG) {
355 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value,
356 atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
358 #endif /* VERBOSE_DEBUG */
363 static inline void atmel_aes_write(struct atmel_aes_dev *dd,
364 u32 offset, u32 value)
367 if (dd->flags & AES_FLAGS_DUMP_REG) {
370 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value,
371 atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
373 #endif /* VERBOSE_DEBUG */
375 writel_relaxed(value, dd->io_base + offset);
378 static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset,
379 u32 *value, int count)
381 for (; count--; value++, offset += 4)
382 *value = atmel_aes_read(dd, offset);
385 static void atmel_aes_write_n(struct atmel_aes_dev *dd, u32 offset,
386 const u32 *value, int count)
388 for (; count--; value++, offset += 4)
389 atmel_aes_write(dd, offset, *value);
392 static inline void atmel_aes_read_block(struct atmel_aes_dev *dd, u32 offset,
395 atmel_aes_read_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
398 static inline void atmel_aes_write_block(struct atmel_aes_dev *dd, u32 offset,
401 atmel_aes_write_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
404 static inline int atmel_aes_wait_for_data_ready(struct atmel_aes_dev *dd,
405 atmel_aes_fn_t resume)
407 u32 isr = atmel_aes_read(dd, AES_ISR);
409 if (unlikely(isr & AES_INT_DATARDY))
413 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
417 static inline size_t atmel_aes_padlen(size_t len, size_t block_size)
419 len &= block_size - 1;
420 return len ? block_size - len : 0;
423 static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_base_ctx *ctx)
425 struct atmel_aes_dev *aes_dd = NULL;
426 struct atmel_aes_dev *tmp;
428 spin_lock_bh(&atmel_aes.lock);
430 list_for_each_entry(tmp, &atmel_aes.dev_list, list) {
439 spin_unlock_bh(&atmel_aes.lock);
444 static int atmel_aes_hw_init(struct atmel_aes_dev *dd)
448 err = clk_enable(dd->iclk);
452 atmel_aes_write(dd, AES_CR, AES_CR_SWRST);
453 atmel_aes_write(dd, AES_MR, 0xE << AES_MR_CKEY_OFFSET);
458 static inline unsigned int atmel_aes_get_version(struct atmel_aes_dev *dd)
460 return atmel_aes_read(dd, AES_HW_VERSION) & 0x00000fff;
463 static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd)
467 err = atmel_aes_hw_init(dd);
471 dd->hw_version = atmel_aes_get_version(dd);
473 dev_info(dd->dev, "version: 0x%x\n", dd->hw_version);
475 clk_disable(dd->iclk);
479 static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd,
480 const struct atmel_aes_reqctx *rctx)
482 /* Clear all but persistent flags and set request flags. */
483 dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode;
486 static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd)
488 return (dd->flags & AES_FLAGS_ENCRYPT);
491 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
492 static void atmel_aes_authenc_complete(struct atmel_aes_dev *dd, int err);
495 static void atmel_aes_set_iv_as_last_ciphertext_block(struct atmel_aes_dev *dd)
497 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
498 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
499 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
500 unsigned int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
502 if (req->nbytes < ivsize)
505 if (rctx->mode & AES_FLAGS_ENCRYPT) {
506 scatterwalk_map_and_copy(req->info, req->dst,
507 req->nbytes - ivsize, ivsize, 0);
509 if (req->src == req->dst)
510 memcpy(req->info, rctx->lastc, ivsize);
512 scatterwalk_map_and_copy(req->info, req->src,
513 req->nbytes - ivsize,
518 static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
520 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
521 if (dd->ctx->is_aead)
522 atmel_aes_authenc_complete(dd, err);
525 clk_disable(dd->iclk);
526 dd->flags &= ~AES_FLAGS_BUSY;
528 if (!dd->ctx->is_aead)
529 atmel_aes_set_iv_as_last_ciphertext_block(dd);
532 dd->areq->complete(dd->areq, err);
534 tasklet_schedule(&dd->queue_task);
539 static void atmel_aes_write_ctrl_key(struct atmel_aes_dev *dd, bool use_dma,
540 const u32 *iv, const u32 *key, int keylen)
544 /* MR register must be set before IV registers */
545 if (keylen == AES_KEYSIZE_128)
546 valmr |= AES_MR_KEYSIZE_128;
547 else if (keylen == AES_KEYSIZE_192)
548 valmr |= AES_MR_KEYSIZE_192;
550 valmr |= AES_MR_KEYSIZE_256;
552 valmr |= dd->flags & AES_FLAGS_MODE_MASK;
555 valmr |= AES_MR_SMOD_IDATAR0;
556 if (dd->caps.has_dualbuff)
557 valmr |= AES_MR_DUALBUFF;
559 valmr |= AES_MR_SMOD_AUTO;
562 atmel_aes_write(dd, AES_MR, valmr);
564 atmel_aes_write_n(dd, AES_KEYWR(0), key, SIZE_IN_WORDS(keylen));
566 if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB)
567 atmel_aes_write_block(dd, AES_IVR(0), iv);
570 static inline void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
574 atmel_aes_write_ctrl_key(dd, use_dma, iv,
575 dd->ctx->key, dd->ctx->keylen);
580 static int atmel_aes_cpu_transfer(struct atmel_aes_dev *dd)
586 atmel_aes_read_block(dd, AES_ODATAR(0), dd->data);
588 dd->datalen -= AES_BLOCK_SIZE;
590 if (dd->datalen < AES_BLOCK_SIZE)
593 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
595 isr = atmel_aes_read(dd, AES_ISR);
596 if (!(isr & AES_INT_DATARDY)) {
597 dd->resume = atmel_aes_cpu_transfer;
598 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
603 if (!sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
608 return atmel_aes_complete(dd, err);
610 return dd->cpu_transfer_complete(dd);
613 static int atmel_aes_cpu_start(struct atmel_aes_dev *dd,
614 struct scatterlist *src,
615 struct scatterlist *dst,
617 atmel_aes_fn_t resume)
619 size_t padlen = atmel_aes_padlen(len, AES_BLOCK_SIZE);
621 if (unlikely(len == 0))
624 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
628 dd->cpu_transfer_complete = resume;
629 dd->datalen = len + padlen;
630 dd->data = (u32 *)dd->buf;
631 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
632 return atmel_aes_wait_for_data_ready(dd, atmel_aes_cpu_transfer);
638 static void atmel_aes_dma_callback(void *data);
640 static bool atmel_aes_check_aligned(struct atmel_aes_dev *dd,
641 struct scatterlist *sg,
643 struct atmel_aes_dma *dma)
647 if (!IS_ALIGNED(len, dd->ctx->block_size))
650 for (nents = 0; sg; sg = sg_next(sg), ++nents) {
651 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
654 if (len <= sg->length) {
655 if (!IS_ALIGNED(len, dd->ctx->block_size))
658 dma->nents = nents+1;
659 dma->remainder = sg->length - len;
664 if (!IS_ALIGNED(sg->length, dd->ctx->block_size))
673 static inline void atmel_aes_restore_sg(const struct atmel_aes_dma *dma)
675 struct scatterlist *sg = dma->sg;
676 int nents = dma->nents;
681 while (--nents > 0 && sg)
687 sg->length += dma->remainder;
690 static int atmel_aes_map(struct atmel_aes_dev *dd,
691 struct scatterlist *src,
692 struct scatterlist *dst,
695 bool src_aligned, dst_aligned;
703 src_aligned = atmel_aes_check_aligned(dd, src, len, &dd->src);
705 dst_aligned = src_aligned;
707 dst_aligned = atmel_aes_check_aligned(dd, dst, len, &dd->dst);
708 if (!src_aligned || !dst_aligned) {
709 padlen = atmel_aes_padlen(len, dd->ctx->block_size);
711 if (dd->buflen < len + padlen)
715 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
716 dd->src.sg = &dd->aligned_sg;
718 dd->src.remainder = 0;
722 dd->dst.sg = &dd->aligned_sg;
724 dd->dst.remainder = 0;
727 sg_init_table(&dd->aligned_sg, 1);
728 sg_set_buf(&dd->aligned_sg, dd->buf, len + padlen);
731 if (dd->src.sg == dd->dst.sg) {
732 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
734 dd->dst.sg_len = dd->src.sg_len;
738 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
743 dd->dst.sg_len = dma_map_sg(dd->dev, dd->dst.sg, dd->dst.nents,
745 if (!dd->dst.sg_len) {
746 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
755 static void atmel_aes_unmap(struct atmel_aes_dev *dd)
757 if (dd->src.sg == dd->dst.sg) {
758 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
761 if (dd->src.sg != &dd->aligned_sg)
762 atmel_aes_restore_sg(&dd->src);
764 dma_unmap_sg(dd->dev, dd->dst.sg, dd->dst.nents,
767 if (dd->dst.sg != &dd->aligned_sg)
768 atmel_aes_restore_sg(&dd->dst);
770 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
773 if (dd->src.sg != &dd->aligned_sg)
774 atmel_aes_restore_sg(&dd->src);
777 if (dd->dst.sg == &dd->aligned_sg)
778 sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
782 static int atmel_aes_dma_transfer_start(struct atmel_aes_dev *dd,
783 enum dma_slave_buswidth addr_width,
784 enum dma_transfer_direction dir,
787 struct dma_async_tx_descriptor *desc;
788 struct dma_slave_config config;
789 dma_async_tx_callback callback;
790 struct atmel_aes_dma *dma;
793 memset(&config, 0, sizeof(config));
794 config.direction = dir;
795 config.src_addr_width = addr_width;
796 config.dst_addr_width = addr_width;
797 config.src_maxburst = maxburst;
798 config.dst_maxburst = maxburst;
804 config.dst_addr = dd->phys_base + AES_IDATAR(0);
809 callback = atmel_aes_dma_callback;
810 config.src_addr = dd->phys_base + AES_ODATAR(0);
817 err = dmaengine_slave_config(dma->chan, &config);
821 desc = dmaengine_prep_slave_sg(dma->chan, dma->sg, dma->sg_len, dir,
822 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
826 desc->callback = callback;
827 desc->callback_param = dd;
828 dmaengine_submit(desc);
829 dma_async_issue_pending(dma->chan);
834 static void atmel_aes_dma_transfer_stop(struct atmel_aes_dev *dd,
835 enum dma_transfer_direction dir)
837 struct atmel_aes_dma *dma;
852 dmaengine_terminate_all(dma->chan);
855 static int atmel_aes_dma_start(struct atmel_aes_dev *dd,
856 struct scatterlist *src,
857 struct scatterlist *dst,
859 atmel_aes_fn_t resume)
861 enum dma_slave_buswidth addr_width;
865 switch (dd->ctx->block_size) {
866 case CFB8_BLOCK_SIZE:
867 addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
871 case CFB16_BLOCK_SIZE:
872 addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
876 case CFB32_BLOCK_SIZE:
877 case CFB64_BLOCK_SIZE:
878 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
883 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
884 maxburst = dd->caps.max_burst_size;
892 err = atmel_aes_map(dd, src, dst, len);
898 /* Set output DMA transfer first */
899 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_DEV_TO_MEM,
904 /* Then set input DMA transfer */
905 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_MEM_TO_DEV,
908 goto output_transfer_stop;
912 output_transfer_stop:
913 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
917 return atmel_aes_complete(dd, err);
920 static void atmel_aes_dma_stop(struct atmel_aes_dev *dd)
922 atmel_aes_dma_transfer_stop(dd, DMA_MEM_TO_DEV);
923 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
927 static void atmel_aes_dma_callback(void *data)
929 struct atmel_aes_dev *dd = data;
931 atmel_aes_dma_stop(dd);
933 (void)dd->resume(dd);
936 static int atmel_aes_handle_queue(struct atmel_aes_dev *dd,
937 struct crypto_async_request *new_areq)
939 struct crypto_async_request *areq, *backlog;
940 struct atmel_aes_base_ctx *ctx;
945 spin_lock_irqsave(&dd->lock, flags);
947 ret = crypto_enqueue_request(&dd->queue, new_areq);
948 if (dd->flags & AES_FLAGS_BUSY) {
949 spin_unlock_irqrestore(&dd->lock, flags);
952 backlog = crypto_get_backlog(&dd->queue);
953 areq = crypto_dequeue_request(&dd->queue);
955 dd->flags |= AES_FLAGS_BUSY;
956 spin_unlock_irqrestore(&dd->lock, flags);
962 backlog->complete(backlog, -EINPROGRESS);
964 ctx = crypto_tfm_ctx(areq->tfm);
968 start_async = (areq != new_areq);
969 dd->is_async = start_async;
971 /* WARNING: ctx->start() MAY change dd->is_async. */
972 err = ctx->start(dd);
973 return (start_async) ? ret : err;
977 /* AES async block ciphers */
979 static int atmel_aes_transfer_complete(struct atmel_aes_dev *dd)
981 return atmel_aes_complete(dd, 0);
984 static int atmel_aes_start(struct atmel_aes_dev *dd)
986 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
987 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
988 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD ||
989 dd->ctx->block_size != AES_BLOCK_SIZE);
992 atmel_aes_set_mode(dd, rctx);
994 err = atmel_aes_hw_init(dd);
996 return atmel_aes_complete(dd, err);
998 atmel_aes_write_ctrl(dd, use_dma, req->info);
1000 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
1001 atmel_aes_transfer_complete);
1003 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
1004 atmel_aes_transfer_complete);
1007 static inline struct atmel_aes_ctr_ctx *
1008 atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx *ctx)
1010 return container_of(ctx, struct atmel_aes_ctr_ctx, base);
1013 static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
1015 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
1016 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1017 struct scatterlist *src, *dst;
1020 u16 blocks, start, end;
1021 bool use_dma, fragmented = false;
1023 /* Check for transfer completion. */
1024 ctx->offset += dd->total;
1025 if (ctx->offset >= req->nbytes)
1026 return atmel_aes_transfer_complete(dd);
1028 /* Compute data length. */
1029 datalen = req->nbytes - ctx->offset;
1030 blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
1031 ctr = be32_to_cpu(ctx->iv[3]);
1033 /* Check 16bit counter overflow. */
1034 start = ctr & 0xffff;
1035 end = start + blocks - 1;
1037 if (blocks >> 16 || end < start) {
1039 datalen = AES_BLOCK_SIZE * (0x10000 - start);
1043 use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);
1045 /* Jump to offset. */
1046 src = scatterwalk_ffwd(ctx->src, req->src, ctx->offset);
1047 dst = ((req->src == req->dst) ? src :
1048 scatterwalk_ffwd(ctx->dst, req->dst, ctx->offset));
1050 /* Configure hardware. */
1051 atmel_aes_write_ctrl(dd, use_dma, ctx->iv);
1052 if (unlikely(fragmented)) {
1054 * Increment the counter manually to cope with the hardware
1057 ctx->iv[3] = cpu_to_be32(ctr);
1058 crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE);
1062 return atmel_aes_dma_start(dd, src, dst, datalen,
1063 atmel_aes_ctr_transfer);
1065 return atmel_aes_cpu_start(dd, src, dst, datalen,
1066 atmel_aes_ctr_transfer);
1069 static int atmel_aes_ctr_start(struct atmel_aes_dev *dd)
1071 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
1072 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1073 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
1076 atmel_aes_set_mode(dd, rctx);
1078 err = atmel_aes_hw_init(dd);
1080 return atmel_aes_complete(dd, err);
1082 memcpy(ctx->iv, req->info, AES_BLOCK_SIZE);
1085 return atmel_aes_ctr_transfer(dd);
1088 static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
1090 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
1091 struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
1092 struct atmel_aes_reqctx *rctx;
1093 struct atmel_aes_dev *dd;
1095 switch (mode & AES_FLAGS_OPMODE_MASK) {
1096 case AES_FLAGS_CFB8:
1097 ctx->block_size = CFB8_BLOCK_SIZE;
1100 case AES_FLAGS_CFB16:
1101 ctx->block_size = CFB16_BLOCK_SIZE;
1104 case AES_FLAGS_CFB32:
1105 ctx->block_size = CFB32_BLOCK_SIZE;
1108 case AES_FLAGS_CFB64:
1109 ctx->block_size = CFB64_BLOCK_SIZE;
1113 ctx->block_size = AES_BLOCK_SIZE;
1116 ctx->is_aead = false;
1118 dd = atmel_aes_find_dev(ctx);
1122 rctx = ablkcipher_request_ctx(req);
1125 if (!(mode & AES_FLAGS_ENCRYPT) && (req->src == req->dst)) {
1126 unsigned int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
1128 if (req->nbytes >= ivsize)
1129 scatterwalk_map_and_copy(rctx->lastc, req->src,
1130 req->nbytes - ivsize,
1134 return atmel_aes_handle_queue(dd, &req->base);
1137 static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1138 unsigned int keylen)
1140 struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1142 if (keylen != AES_KEYSIZE_128 &&
1143 keylen != AES_KEYSIZE_192 &&
1144 keylen != AES_KEYSIZE_256) {
1145 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1149 memcpy(ctx->key, key, keylen);
1150 ctx->keylen = keylen;
1155 static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req)
1157 return atmel_aes_crypt(req, AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1160 static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req)
1162 return atmel_aes_crypt(req, AES_FLAGS_ECB);
1165 static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req)
1167 return atmel_aes_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT);
1170 static int atmel_aes_cbc_decrypt(struct ablkcipher_request *req)
1172 return atmel_aes_crypt(req, AES_FLAGS_CBC);
1175 static int atmel_aes_ofb_encrypt(struct ablkcipher_request *req)
1177 return atmel_aes_crypt(req, AES_FLAGS_OFB | AES_FLAGS_ENCRYPT);
1180 static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req)
1182 return atmel_aes_crypt(req, AES_FLAGS_OFB);
1185 static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req)
1187 return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT);
1190 static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req)
1192 return atmel_aes_crypt(req, AES_FLAGS_CFB128);
1195 static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req)
1197 return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT);
1200 static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req)
1202 return atmel_aes_crypt(req, AES_FLAGS_CFB64);
1205 static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req)
1207 return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT);
1210 static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req)
1212 return atmel_aes_crypt(req, AES_FLAGS_CFB32);
1215 static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req)
1217 return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT);
1220 static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req)
1222 return atmel_aes_crypt(req, AES_FLAGS_CFB16);
1225 static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req)
1227 return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT);
1230 static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req)
1232 return atmel_aes_crypt(req, AES_FLAGS_CFB8);
1235 static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req)
1237 return atmel_aes_crypt(req, AES_FLAGS_CTR | AES_FLAGS_ENCRYPT);
1240 static int atmel_aes_ctr_decrypt(struct ablkcipher_request *req)
1242 return atmel_aes_crypt(req, AES_FLAGS_CTR);
1245 static int atmel_aes_cra_init(struct crypto_tfm *tfm)
1247 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1249 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1250 ctx->base.start = atmel_aes_start;
1255 static int atmel_aes_ctr_cra_init(struct crypto_tfm *tfm)
1257 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1259 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1260 ctx->base.start = atmel_aes_ctr_start;
1265 static struct crypto_alg aes_algs[] = {
1267 .cra_name = "ecb(aes)",
1268 .cra_driver_name = "atmel-ecb-aes",
1269 .cra_priority = ATMEL_AES_PRIORITY,
1270 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1271 .cra_blocksize = AES_BLOCK_SIZE,
1272 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1273 .cra_alignmask = 0xf,
1274 .cra_type = &crypto_ablkcipher_type,
1275 .cra_module = THIS_MODULE,
1276 .cra_init = atmel_aes_cra_init,
1277 .cra_u.ablkcipher = {
1278 .min_keysize = AES_MIN_KEY_SIZE,
1279 .max_keysize = AES_MAX_KEY_SIZE,
1280 .setkey = atmel_aes_setkey,
1281 .encrypt = atmel_aes_ecb_encrypt,
1282 .decrypt = atmel_aes_ecb_decrypt,
1286 .cra_name = "cbc(aes)",
1287 .cra_driver_name = "atmel-cbc-aes",
1288 .cra_priority = ATMEL_AES_PRIORITY,
1289 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1290 .cra_blocksize = AES_BLOCK_SIZE,
1291 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1292 .cra_alignmask = 0xf,
1293 .cra_type = &crypto_ablkcipher_type,
1294 .cra_module = THIS_MODULE,
1295 .cra_init = atmel_aes_cra_init,
1296 .cra_u.ablkcipher = {
1297 .min_keysize = AES_MIN_KEY_SIZE,
1298 .max_keysize = AES_MAX_KEY_SIZE,
1299 .ivsize = AES_BLOCK_SIZE,
1300 .setkey = atmel_aes_setkey,
1301 .encrypt = atmel_aes_cbc_encrypt,
1302 .decrypt = atmel_aes_cbc_decrypt,
1306 .cra_name = "ofb(aes)",
1307 .cra_driver_name = "atmel-ofb-aes",
1308 .cra_priority = ATMEL_AES_PRIORITY,
1309 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1310 .cra_blocksize = AES_BLOCK_SIZE,
1311 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1312 .cra_alignmask = 0xf,
1313 .cra_type = &crypto_ablkcipher_type,
1314 .cra_module = THIS_MODULE,
1315 .cra_init = atmel_aes_cra_init,
1316 .cra_u.ablkcipher = {
1317 .min_keysize = AES_MIN_KEY_SIZE,
1318 .max_keysize = AES_MAX_KEY_SIZE,
1319 .ivsize = AES_BLOCK_SIZE,
1320 .setkey = atmel_aes_setkey,
1321 .encrypt = atmel_aes_ofb_encrypt,
1322 .decrypt = atmel_aes_ofb_decrypt,
1326 .cra_name = "cfb(aes)",
1327 .cra_driver_name = "atmel-cfb-aes",
1328 .cra_priority = ATMEL_AES_PRIORITY,
1329 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1330 .cra_blocksize = AES_BLOCK_SIZE,
1331 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1332 .cra_alignmask = 0xf,
1333 .cra_type = &crypto_ablkcipher_type,
1334 .cra_module = THIS_MODULE,
1335 .cra_init = atmel_aes_cra_init,
1336 .cra_u.ablkcipher = {
1337 .min_keysize = AES_MIN_KEY_SIZE,
1338 .max_keysize = AES_MAX_KEY_SIZE,
1339 .ivsize = AES_BLOCK_SIZE,
1340 .setkey = atmel_aes_setkey,
1341 .encrypt = atmel_aes_cfb_encrypt,
1342 .decrypt = atmel_aes_cfb_decrypt,
1346 .cra_name = "cfb32(aes)",
1347 .cra_driver_name = "atmel-cfb32-aes",
1348 .cra_priority = ATMEL_AES_PRIORITY,
1349 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1350 .cra_blocksize = CFB32_BLOCK_SIZE,
1351 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1352 .cra_alignmask = 0x3,
1353 .cra_type = &crypto_ablkcipher_type,
1354 .cra_module = THIS_MODULE,
1355 .cra_init = atmel_aes_cra_init,
1356 .cra_u.ablkcipher = {
1357 .min_keysize = AES_MIN_KEY_SIZE,
1358 .max_keysize = AES_MAX_KEY_SIZE,
1359 .ivsize = AES_BLOCK_SIZE,
1360 .setkey = atmel_aes_setkey,
1361 .encrypt = atmel_aes_cfb32_encrypt,
1362 .decrypt = atmel_aes_cfb32_decrypt,
1366 .cra_name = "cfb16(aes)",
1367 .cra_driver_name = "atmel-cfb16-aes",
1368 .cra_priority = ATMEL_AES_PRIORITY,
1369 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1370 .cra_blocksize = CFB16_BLOCK_SIZE,
1371 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1372 .cra_alignmask = 0x1,
1373 .cra_type = &crypto_ablkcipher_type,
1374 .cra_module = THIS_MODULE,
1375 .cra_init = atmel_aes_cra_init,
1376 .cra_u.ablkcipher = {
1377 .min_keysize = AES_MIN_KEY_SIZE,
1378 .max_keysize = AES_MAX_KEY_SIZE,
1379 .ivsize = AES_BLOCK_SIZE,
1380 .setkey = atmel_aes_setkey,
1381 .encrypt = atmel_aes_cfb16_encrypt,
1382 .decrypt = atmel_aes_cfb16_decrypt,
1386 .cra_name = "cfb8(aes)",
1387 .cra_driver_name = "atmel-cfb8-aes",
1388 .cra_priority = ATMEL_AES_PRIORITY,
1389 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1390 .cra_blocksize = CFB8_BLOCK_SIZE,
1391 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1392 .cra_alignmask = 0x0,
1393 .cra_type = &crypto_ablkcipher_type,
1394 .cra_module = THIS_MODULE,
1395 .cra_init = atmel_aes_cra_init,
1396 .cra_u.ablkcipher = {
1397 .min_keysize = AES_MIN_KEY_SIZE,
1398 .max_keysize = AES_MAX_KEY_SIZE,
1399 .ivsize = AES_BLOCK_SIZE,
1400 .setkey = atmel_aes_setkey,
1401 .encrypt = atmel_aes_cfb8_encrypt,
1402 .decrypt = atmel_aes_cfb8_decrypt,
1406 .cra_name = "ctr(aes)",
1407 .cra_driver_name = "atmel-ctr-aes",
1408 .cra_priority = ATMEL_AES_PRIORITY,
1409 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1411 .cra_ctxsize = sizeof(struct atmel_aes_ctr_ctx),
1412 .cra_alignmask = 0xf,
1413 .cra_type = &crypto_ablkcipher_type,
1414 .cra_module = THIS_MODULE,
1415 .cra_init = atmel_aes_ctr_cra_init,
1416 .cra_u.ablkcipher = {
1417 .min_keysize = AES_MIN_KEY_SIZE,
1418 .max_keysize = AES_MAX_KEY_SIZE,
1419 .ivsize = AES_BLOCK_SIZE,
1420 .setkey = atmel_aes_setkey,
1421 .encrypt = atmel_aes_ctr_encrypt,
1422 .decrypt = atmel_aes_ctr_decrypt,
1427 static struct crypto_alg aes_cfb64_alg = {
1428 .cra_name = "cfb64(aes)",
1429 .cra_driver_name = "atmel-cfb64-aes",
1430 .cra_priority = ATMEL_AES_PRIORITY,
1431 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1432 .cra_blocksize = CFB64_BLOCK_SIZE,
1433 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1434 .cra_alignmask = 0x7,
1435 .cra_type = &crypto_ablkcipher_type,
1436 .cra_module = THIS_MODULE,
1437 .cra_init = atmel_aes_cra_init,
1438 .cra_u.ablkcipher = {
1439 .min_keysize = AES_MIN_KEY_SIZE,
1440 .max_keysize = AES_MAX_KEY_SIZE,
1441 .ivsize = AES_BLOCK_SIZE,
1442 .setkey = atmel_aes_setkey,
1443 .encrypt = atmel_aes_cfb64_encrypt,
1444 .decrypt = atmel_aes_cfb64_decrypt,
1449 /* gcm aead functions */
1451 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1452 const u32 *data, size_t datalen,
1453 const u32 *ghash_in, u32 *ghash_out,
1454 atmel_aes_fn_t resume);
1455 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd);
1456 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd);
1458 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd);
1459 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd);
1460 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd);
1461 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd);
1462 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd);
1463 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd);
1464 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd);
1466 static inline struct atmel_aes_gcm_ctx *
1467 atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx *ctx)
1469 return container_of(ctx, struct atmel_aes_gcm_ctx, base);
1472 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1473 const u32 *data, size_t datalen,
1474 const u32 *ghash_in, u32 *ghash_out,
1475 atmel_aes_fn_t resume)
1477 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1479 dd->data = (u32 *)data;
1480 dd->datalen = datalen;
1481 ctx->ghash_in = ghash_in;
1482 ctx->ghash_out = ghash_out;
1483 ctx->ghash_resume = resume;
1485 atmel_aes_write_ctrl(dd, false, NULL);
1486 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_ghash_init);
1489 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd)
1491 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1493 /* Set the data length. */
1494 atmel_aes_write(dd, AES_AADLENR, dd->total);
1495 atmel_aes_write(dd, AES_CLENR, 0);
1497 /* If needed, overwrite the GCM Intermediate Hash Word Registers */
1499 atmel_aes_write_block(dd, AES_GHASHR(0), ctx->ghash_in);
1501 return atmel_aes_gcm_ghash_finalize(dd);
1504 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd)
1506 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1509 /* Write data into the Input Data Registers. */
1510 while (dd->datalen > 0) {
1511 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1513 dd->datalen -= AES_BLOCK_SIZE;
1515 isr = atmel_aes_read(dd, AES_ISR);
1516 if (!(isr & AES_INT_DATARDY)) {
1517 dd->resume = atmel_aes_gcm_ghash_finalize;
1518 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1519 return -EINPROGRESS;
1523 /* Read the computed hash from GHASHRx. */
1524 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash_out);
1526 return ctx->ghash_resume(dd);
1530 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd)
1532 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1533 struct aead_request *req = aead_request_cast(dd->areq);
1534 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1535 struct atmel_aes_reqctx *rctx = aead_request_ctx(req);
1536 size_t ivsize = crypto_aead_ivsize(tfm);
1537 size_t datalen, padlen;
1538 const void *iv = req->iv;
1542 atmel_aes_set_mode(dd, rctx);
1544 err = atmel_aes_hw_init(dd);
1546 return atmel_aes_complete(dd, err);
1548 if (likely(ivsize == GCM_AES_IV_SIZE)) {
1549 memcpy(ctx->j0, iv, ivsize);
1550 ctx->j0[3] = cpu_to_be32(1);
1551 return atmel_aes_gcm_process(dd);
1554 padlen = atmel_aes_padlen(ivsize, AES_BLOCK_SIZE);
1555 datalen = ivsize + padlen + AES_BLOCK_SIZE;
1556 if (datalen > dd->buflen)
1557 return atmel_aes_complete(dd, -EINVAL);
1559 memcpy(data, iv, ivsize);
1560 memset(data + ivsize, 0, padlen + sizeof(u64));
1561 ((u64 *)(data + datalen))[-1] = cpu_to_be64(ivsize * 8);
1563 return atmel_aes_gcm_ghash(dd, (const u32 *)data, datalen,
1564 NULL, ctx->j0, atmel_aes_gcm_process);
1567 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd)
1569 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1570 struct aead_request *req = aead_request_cast(dd->areq);
1571 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1572 bool enc = atmel_aes_is_encrypt(dd);
1575 /* Compute text length. */
1576 authsize = crypto_aead_authsize(tfm);
1577 ctx->textlen = req->cryptlen - (enc ? 0 : authsize);
1580 * According to tcrypt test suite, the GCM Automatic Tag Generation
1581 * fails when both the message and its associated data are empty.
1583 if (likely(req->assoclen != 0 || ctx->textlen != 0))
1584 dd->flags |= AES_FLAGS_GTAGEN;
1586 atmel_aes_write_ctrl(dd, false, NULL);
1587 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_length);
1590 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd)
1592 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1593 struct aead_request *req = aead_request_cast(dd->areq);
1594 u32 j0_lsw, *j0 = ctx->j0;
1597 /* Write incr32(J0) into IV. */
1599 j0[3] = cpu_to_be32(be32_to_cpu(j0[3]) + 1);
1600 atmel_aes_write_block(dd, AES_IVR(0), j0);
1603 /* Set aad and text lengths. */
1604 atmel_aes_write(dd, AES_AADLENR, req->assoclen);
1605 atmel_aes_write(dd, AES_CLENR, ctx->textlen);
1607 /* Check whether AAD are present. */
1608 if (unlikely(req->assoclen == 0)) {
1610 return atmel_aes_gcm_data(dd);
1613 /* Copy assoc data and add padding. */
1614 padlen = atmel_aes_padlen(req->assoclen, AES_BLOCK_SIZE);
1615 if (unlikely(req->assoclen + padlen > dd->buflen))
1616 return atmel_aes_complete(dd, -EINVAL);
1617 sg_copy_to_buffer(req->src, sg_nents(req->src), dd->buf, req->assoclen);
1619 /* Write assoc data into the Input Data register. */
1620 dd->data = (u32 *)dd->buf;
1621 dd->datalen = req->assoclen + padlen;
1622 return atmel_aes_gcm_data(dd);
1625 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd)
1627 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1628 struct aead_request *req = aead_request_cast(dd->areq);
1629 bool use_dma = (ctx->textlen >= ATMEL_AES_DMA_THRESHOLD);
1630 struct scatterlist *src, *dst;
1633 /* Write AAD first. */
1634 while (dd->datalen > 0) {
1635 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1637 dd->datalen -= AES_BLOCK_SIZE;
1639 isr = atmel_aes_read(dd, AES_ISR);
1640 if (!(isr & AES_INT_DATARDY)) {
1641 dd->resume = atmel_aes_gcm_data;
1642 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1643 return -EINPROGRESS;
1648 if (unlikely(ctx->textlen == 0))
1649 return atmel_aes_gcm_tag_init(dd);
1651 /* Prepare src and dst scatter lists to transfer cipher/plain texts */
1652 src = scatterwalk_ffwd(ctx->src, req->src, req->assoclen);
1653 dst = ((req->src == req->dst) ? src :
1654 scatterwalk_ffwd(ctx->dst, req->dst, req->assoclen));
1657 /* Update the Mode Register for DMA transfers. */
1658 mr = atmel_aes_read(dd, AES_MR);
1659 mr &= ~(AES_MR_SMOD_MASK | AES_MR_DUALBUFF);
1660 mr |= AES_MR_SMOD_IDATAR0;
1661 if (dd->caps.has_dualbuff)
1662 mr |= AES_MR_DUALBUFF;
1663 atmel_aes_write(dd, AES_MR, mr);
1665 return atmel_aes_dma_start(dd, src, dst, ctx->textlen,
1666 atmel_aes_gcm_tag_init);
1669 return atmel_aes_cpu_start(dd, src, dst, ctx->textlen,
1670 atmel_aes_gcm_tag_init);
1673 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd)
1675 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1676 struct aead_request *req = aead_request_cast(dd->areq);
1677 u64 *data = dd->buf;
1679 if (likely(dd->flags & AES_FLAGS_GTAGEN)) {
1680 if (!(atmel_aes_read(dd, AES_ISR) & AES_INT_TAGRDY)) {
1681 dd->resume = atmel_aes_gcm_tag_init;
1682 atmel_aes_write(dd, AES_IER, AES_INT_TAGRDY);
1683 return -EINPROGRESS;
1686 return atmel_aes_gcm_finalize(dd);
1689 /* Read the GCM Intermediate Hash Word Registers. */
1690 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash);
1692 data[0] = cpu_to_be64(req->assoclen * 8);
1693 data[1] = cpu_to_be64(ctx->textlen * 8);
1695 return atmel_aes_gcm_ghash(dd, (const u32 *)data, AES_BLOCK_SIZE,
1696 ctx->ghash, ctx->ghash, atmel_aes_gcm_tag);
1699 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd)
1701 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1702 unsigned long flags;
1705 * Change mode to CTR to complete the tag generation.
1706 * Use J0 as Initialization Vector.
1709 dd->flags &= ~(AES_FLAGS_OPMODE_MASK | AES_FLAGS_GTAGEN);
1710 dd->flags |= AES_FLAGS_CTR;
1711 atmel_aes_write_ctrl(dd, false, ctx->j0);
1714 atmel_aes_write_block(dd, AES_IDATAR(0), ctx->ghash);
1715 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_finalize);
1718 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd)
1720 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1721 struct aead_request *req = aead_request_cast(dd->areq);
1722 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1723 bool enc = atmel_aes_is_encrypt(dd);
1724 u32 offset, authsize, itag[4], *otag = ctx->tag;
1727 /* Read the computed tag. */
1728 if (likely(dd->flags & AES_FLAGS_GTAGEN))
1729 atmel_aes_read_block(dd, AES_TAGR(0), ctx->tag);
1731 atmel_aes_read_block(dd, AES_ODATAR(0), ctx->tag);
1733 offset = req->assoclen + ctx->textlen;
1734 authsize = crypto_aead_authsize(tfm);
1736 scatterwalk_map_and_copy(otag, req->dst, offset, authsize, 1);
1739 scatterwalk_map_and_copy(itag, req->src, offset, authsize, 0);
1740 err = crypto_memneq(itag, otag, authsize) ? -EBADMSG : 0;
1743 return atmel_aes_complete(dd, err);
1746 static int atmel_aes_gcm_crypt(struct aead_request *req,
1749 struct atmel_aes_base_ctx *ctx;
1750 struct atmel_aes_reqctx *rctx;
1751 struct atmel_aes_dev *dd;
1753 ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
1754 ctx->block_size = AES_BLOCK_SIZE;
1755 ctx->is_aead = true;
1757 dd = atmel_aes_find_dev(ctx);
1761 rctx = aead_request_ctx(req);
1762 rctx->mode = AES_FLAGS_GCM | mode;
1764 return atmel_aes_handle_queue(dd, &req->base);
1767 static int atmel_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
1768 unsigned int keylen)
1770 struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
1772 if (keylen != AES_KEYSIZE_256 &&
1773 keylen != AES_KEYSIZE_192 &&
1774 keylen != AES_KEYSIZE_128) {
1775 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1779 memcpy(ctx->key, key, keylen);
1780 ctx->keylen = keylen;
1785 static int atmel_aes_gcm_setauthsize(struct crypto_aead *tfm,
1786 unsigned int authsize)
1788 /* Same as crypto_gcm_authsize() from crypto/gcm.c */
1805 static int atmel_aes_gcm_encrypt(struct aead_request *req)
1807 return atmel_aes_gcm_crypt(req, AES_FLAGS_ENCRYPT);
1810 static int atmel_aes_gcm_decrypt(struct aead_request *req)
1812 return atmel_aes_gcm_crypt(req, 0);
1815 static int atmel_aes_gcm_init(struct crypto_aead *tfm)
1817 struct atmel_aes_gcm_ctx *ctx = crypto_aead_ctx(tfm);
1819 crypto_aead_set_reqsize(tfm, sizeof(struct atmel_aes_reqctx));
1820 ctx->base.start = atmel_aes_gcm_start;
1825 static struct aead_alg aes_gcm_alg = {
1826 .setkey = atmel_aes_gcm_setkey,
1827 .setauthsize = atmel_aes_gcm_setauthsize,
1828 .encrypt = atmel_aes_gcm_encrypt,
1829 .decrypt = atmel_aes_gcm_decrypt,
1830 .init = atmel_aes_gcm_init,
1831 .ivsize = GCM_AES_IV_SIZE,
1832 .maxauthsize = AES_BLOCK_SIZE,
1835 .cra_name = "gcm(aes)",
1836 .cra_driver_name = "atmel-gcm-aes",
1837 .cra_priority = ATMEL_AES_PRIORITY,
1838 .cra_flags = CRYPTO_ALG_ASYNC,
1840 .cra_ctxsize = sizeof(struct atmel_aes_gcm_ctx),
1841 .cra_alignmask = 0xf,
1842 .cra_module = THIS_MODULE,
1849 static inline struct atmel_aes_xts_ctx *
1850 atmel_aes_xts_ctx_cast(struct atmel_aes_base_ctx *ctx)
1852 return container_of(ctx, struct atmel_aes_xts_ctx, base);
1855 static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd);
1857 static int atmel_aes_xts_start(struct atmel_aes_dev *dd)
1859 struct atmel_aes_xts_ctx *ctx = atmel_aes_xts_ctx_cast(dd->ctx);
1860 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1861 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
1862 unsigned long flags;
1865 atmel_aes_set_mode(dd, rctx);
1867 err = atmel_aes_hw_init(dd);
1869 return atmel_aes_complete(dd, err);
1871 /* Compute the tweak value from req->info with ecb(aes). */
1873 dd->flags &= ~AES_FLAGS_MODE_MASK;
1874 dd->flags |= (AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1875 atmel_aes_write_ctrl_key(dd, false, NULL,
1876 ctx->key2, ctx->base.keylen);
1879 atmel_aes_write_block(dd, AES_IDATAR(0), req->info);
1880 return atmel_aes_wait_for_data_ready(dd, atmel_aes_xts_process_data);
1883 static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd)
1885 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1886 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD);
1887 u32 tweak[AES_BLOCK_SIZE / sizeof(u32)];
1888 static const u32 one[AES_BLOCK_SIZE / sizeof(u32)] = {cpu_to_le32(1), };
1889 u8 *tweak_bytes = (u8 *)tweak;
1892 /* Read the computed ciphered tweak value. */
1893 atmel_aes_read_block(dd, AES_ODATAR(0), tweak);
1896 * the order of the ciphered tweak bytes need to be reversed before
1897 * writing them into the ODATARx registers.
1899 for (i = 0; i < AES_BLOCK_SIZE/2; ++i) {
1900 u8 tmp = tweak_bytes[AES_BLOCK_SIZE - 1 - i];
1902 tweak_bytes[AES_BLOCK_SIZE - 1 - i] = tweak_bytes[i];
1903 tweak_bytes[i] = tmp;
1906 /* Process the data. */
1907 atmel_aes_write_ctrl(dd, use_dma, NULL);
1908 atmel_aes_write_block(dd, AES_TWR(0), tweak);
1909 atmel_aes_write_block(dd, AES_ALPHAR(0), one);
1911 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
1912 atmel_aes_transfer_complete);
1914 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
1915 atmel_aes_transfer_complete);
1918 static int atmel_aes_xts_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1919 unsigned int keylen)
1921 struct atmel_aes_xts_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1924 err = xts_check_key(crypto_ablkcipher_tfm(tfm), key, keylen);
1928 memcpy(ctx->base.key, key, keylen/2);
1929 memcpy(ctx->key2, key + keylen/2, keylen/2);
1930 ctx->base.keylen = keylen/2;
1935 static int atmel_aes_xts_encrypt(struct ablkcipher_request *req)
1937 return atmel_aes_crypt(req, AES_FLAGS_XTS | AES_FLAGS_ENCRYPT);
1940 static int atmel_aes_xts_decrypt(struct ablkcipher_request *req)
1942 return atmel_aes_crypt(req, AES_FLAGS_XTS);
1945 static int atmel_aes_xts_cra_init(struct crypto_tfm *tfm)
1947 struct atmel_aes_xts_ctx *ctx = crypto_tfm_ctx(tfm);
1949 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1950 ctx->base.start = atmel_aes_xts_start;
1955 static struct crypto_alg aes_xts_alg = {
1956 .cra_name = "xts(aes)",
1957 .cra_driver_name = "atmel-xts-aes",
1958 .cra_priority = ATMEL_AES_PRIORITY,
1959 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1960 .cra_blocksize = AES_BLOCK_SIZE,
1961 .cra_ctxsize = sizeof(struct atmel_aes_xts_ctx),
1962 .cra_alignmask = 0xf,
1963 .cra_type = &crypto_ablkcipher_type,
1964 .cra_module = THIS_MODULE,
1965 .cra_init = atmel_aes_xts_cra_init,
1966 .cra_u.ablkcipher = {
1967 .min_keysize = 2 * AES_MIN_KEY_SIZE,
1968 .max_keysize = 2 * AES_MAX_KEY_SIZE,
1969 .ivsize = AES_BLOCK_SIZE,
1970 .setkey = atmel_aes_xts_setkey,
1971 .encrypt = atmel_aes_xts_encrypt,
1972 .decrypt = atmel_aes_xts_decrypt,
1976 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
1977 /* authenc aead functions */
1979 static int atmel_aes_authenc_start(struct atmel_aes_dev *dd);
1980 static int atmel_aes_authenc_init(struct atmel_aes_dev *dd, int err,
1982 static int atmel_aes_authenc_transfer(struct atmel_aes_dev *dd, int err,
1984 static int atmel_aes_authenc_digest(struct atmel_aes_dev *dd);
1985 static int atmel_aes_authenc_final(struct atmel_aes_dev *dd, int err,
1988 static void atmel_aes_authenc_complete(struct atmel_aes_dev *dd, int err)
1990 struct aead_request *req = aead_request_cast(dd->areq);
1991 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
1993 if (err && (dd->flags & AES_FLAGS_OWN_SHA))
1994 atmel_sha_authenc_abort(&rctx->auth_req);
1995 dd->flags &= ~AES_FLAGS_OWN_SHA;
1998 static int atmel_aes_authenc_start(struct atmel_aes_dev *dd)
2000 struct aead_request *req = aead_request_cast(dd->areq);
2001 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2002 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
2003 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2006 atmel_aes_set_mode(dd, &rctx->base);
2008 err = atmel_aes_hw_init(dd);
2010 return atmel_aes_complete(dd, err);
2012 return atmel_sha_authenc_schedule(&rctx->auth_req, ctx->auth,
2013 atmel_aes_authenc_init, dd);
2016 static int atmel_aes_authenc_init(struct atmel_aes_dev *dd, int err,
2019 struct aead_request *req = aead_request_cast(dd->areq);
2020 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2023 dd->is_async = true;
2025 return atmel_aes_complete(dd, err);
2027 /* If here, we've got the ownership of the SHA device. */
2028 dd->flags |= AES_FLAGS_OWN_SHA;
2030 /* Configure the SHA device. */
2031 return atmel_sha_authenc_init(&rctx->auth_req,
2032 req->src, req->assoclen,
2034 atmel_aes_authenc_transfer, dd);
2037 static int atmel_aes_authenc_transfer(struct atmel_aes_dev *dd, int err,
2040 struct aead_request *req = aead_request_cast(dd->areq);
2041 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2042 bool enc = atmel_aes_is_encrypt(dd);
2043 struct scatterlist *src, *dst;
2044 u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
2048 dd->is_async = true;
2050 return atmel_aes_complete(dd, err);
2052 /* Prepare src and dst scatter-lists to transfer cipher/plain texts. */
2053 src = scatterwalk_ffwd(rctx->src, req->src, req->assoclen);
2056 if (req->src != req->dst)
2057 dst = scatterwalk_ffwd(rctx->dst, req->dst, req->assoclen);
2059 /* Configure the AES device. */
2060 memcpy(iv, req->iv, sizeof(iv));
2063 * Here we always set the 2nd parameter of atmel_aes_write_ctrl() to
2064 * 'true' even if the data transfer is actually performed by the CPU (so
2065 * not by the DMA) because we must force the AES_MR_SMOD bitfield to the
2066 * value AES_MR_SMOD_IDATAR0. Indeed, both AES_MR_SMOD and SHA_MR_SMOD
2067 * must be set to *_MR_SMOD_IDATAR0.
2069 atmel_aes_write_ctrl(dd, true, iv);
2070 emr = AES_EMR_PLIPEN;
2072 emr |= AES_EMR_PLIPD;
2073 atmel_aes_write(dd, AES_EMR, emr);
2075 /* Transfer data. */
2076 return atmel_aes_dma_start(dd, src, dst, rctx->textlen,
2077 atmel_aes_authenc_digest);
2080 static int atmel_aes_authenc_digest(struct atmel_aes_dev *dd)
2082 struct aead_request *req = aead_request_cast(dd->areq);
2083 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2085 /* atmel_sha_authenc_final() releases the SHA device. */
2086 dd->flags &= ~AES_FLAGS_OWN_SHA;
2087 return atmel_sha_authenc_final(&rctx->auth_req,
2088 rctx->digest, sizeof(rctx->digest),
2089 atmel_aes_authenc_final, dd);
2092 static int atmel_aes_authenc_final(struct atmel_aes_dev *dd, int err,
2095 struct aead_request *req = aead_request_cast(dd->areq);
2096 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2097 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
2098 bool enc = atmel_aes_is_encrypt(dd);
2099 u32 idigest[SHA512_DIGEST_SIZE / sizeof(u32)], *odigest = rctx->digest;
2103 dd->is_async = true;
2107 offs = req->assoclen + rctx->textlen;
2108 authsize = crypto_aead_authsize(tfm);
2110 scatterwalk_map_and_copy(odigest, req->dst, offs, authsize, 1);
2112 scatterwalk_map_and_copy(idigest, req->src, offs, authsize, 0);
2113 if (crypto_memneq(idigest, odigest, authsize))
2118 return atmel_aes_complete(dd, err);
2121 static int atmel_aes_authenc_setkey(struct crypto_aead *tfm, const u8 *key,
2122 unsigned int keylen)
2124 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2125 struct crypto_authenc_keys keys;
2129 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
2132 if (keys.enckeylen > sizeof(ctx->base.key))
2135 /* Save auth key. */
2136 flags = crypto_aead_get_flags(tfm);
2137 err = atmel_sha_authenc_setkey(ctx->auth,
2138 keys.authkey, keys.authkeylen,
2140 crypto_aead_set_flags(tfm, flags & CRYPTO_TFM_RES_MASK);
2142 memzero_explicit(&keys, sizeof(keys));
2147 ctx->base.keylen = keys.enckeylen;
2148 memcpy(ctx->base.key, keys.enckey, keys.enckeylen);
2150 memzero_explicit(&keys, sizeof(keys));
2154 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
2155 memzero_explicit(&keys, sizeof(keys));
2159 static int atmel_aes_authenc_init_tfm(struct crypto_aead *tfm,
2160 unsigned long auth_mode)
2162 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2163 unsigned int auth_reqsize = atmel_sha_authenc_get_reqsize();
2165 ctx->auth = atmel_sha_authenc_spawn(auth_mode);
2166 if (IS_ERR(ctx->auth))
2167 return PTR_ERR(ctx->auth);
2169 crypto_aead_set_reqsize(tfm, (sizeof(struct atmel_aes_authenc_reqctx) +
2171 ctx->base.start = atmel_aes_authenc_start;
2176 static int atmel_aes_authenc_hmac_sha1_init_tfm(struct crypto_aead *tfm)
2178 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA1);
2181 static int atmel_aes_authenc_hmac_sha224_init_tfm(struct crypto_aead *tfm)
2183 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA224);
2186 static int atmel_aes_authenc_hmac_sha256_init_tfm(struct crypto_aead *tfm)
2188 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA256);
2191 static int atmel_aes_authenc_hmac_sha384_init_tfm(struct crypto_aead *tfm)
2193 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA384);
2196 static int atmel_aes_authenc_hmac_sha512_init_tfm(struct crypto_aead *tfm)
2198 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA512);
2201 static void atmel_aes_authenc_exit_tfm(struct crypto_aead *tfm)
2203 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2205 atmel_sha_authenc_free(ctx->auth);
2208 static int atmel_aes_authenc_crypt(struct aead_request *req,
2211 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2212 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
2213 struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
2214 u32 authsize = crypto_aead_authsize(tfm);
2215 bool enc = (mode & AES_FLAGS_ENCRYPT);
2216 struct atmel_aes_dev *dd;
2218 /* Compute text length. */
2219 if (!enc && req->cryptlen < authsize)
2221 rctx->textlen = req->cryptlen - (enc ? 0 : authsize);
2224 * Currently, empty messages are not supported yet:
2225 * the SHA auto-padding can be used only on non-empty messages.
2226 * Hence a special case needs to be implemented for empty message.
2228 if (!rctx->textlen && !req->assoclen)
2231 rctx->base.mode = mode;
2232 ctx->block_size = AES_BLOCK_SIZE;
2233 ctx->is_aead = true;
2235 dd = atmel_aes_find_dev(ctx);
2239 return atmel_aes_handle_queue(dd, &req->base);
2242 static int atmel_aes_authenc_cbc_aes_encrypt(struct aead_request *req)
2244 return atmel_aes_authenc_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT);
2247 static int atmel_aes_authenc_cbc_aes_decrypt(struct aead_request *req)
2249 return atmel_aes_authenc_crypt(req, AES_FLAGS_CBC);
2252 static struct aead_alg aes_authenc_algs[] = {
2254 .setkey = atmel_aes_authenc_setkey,
2255 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2256 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2257 .init = atmel_aes_authenc_hmac_sha1_init_tfm,
2258 .exit = atmel_aes_authenc_exit_tfm,
2259 .ivsize = AES_BLOCK_SIZE,
2260 .maxauthsize = SHA1_DIGEST_SIZE,
2263 .cra_name = "authenc(hmac(sha1),cbc(aes))",
2264 .cra_driver_name = "atmel-authenc-hmac-sha1-cbc-aes",
2265 .cra_priority = ATMEL_AES_PRIORITY,
2266 .cra_flags = CRYPTO_ALG_ASYNC,
2267 .cra_blocksize = AES_BLOCK_SIZE,
2268 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2269 .cra_alignmask = 0xf,
2270 .cra_module = THIS_MODULE,
2274 .setkey = atmel_aes_authenc_setkey,
2275 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2276 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2277 .init = atmel_aes_authenc_hmac_sha224_init_tfm,
2278 .exit = atmel_aes_authenc_exit_tfm,
2279 .ivsize = AES_BLOCK_SIZE,
2280 .maxauthsize = SHA224_DIGEST_SIZE,
2283 .cra_name = "authenc(hmac(sha224),cbc(aes))",
2284 .cra_driver_name = "atmel-authenc-hmac-sha224-cbc-aes",
2285 .cra_priority = ATMEL_AES_PRIORITY,
2286 .cra_flags = CRYPTO_ALG_ASYNC,
2287 .cra_blocksize = AES_BLOCK_SIZE,
2288 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2289 .cra_alignmask = 0xf,
2290 .cra_module = THIS_MODULE,
2294 .setkey = atmel_aes_authenc_setkey,
2295 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2296 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2297 .init = atmel_aes_authenc_hmac_sha256_init_tfm,
2298 .exit = atmel_aes_authenc_exit_tfm,
2299 .ivsize = AES_BLOCK_SIZE,
2300 .maxauthsize = SHA256_DIGEST_SIZE,
2303 .cra_name = "authenc(hmac(sha256),cbc(aes))",
2304 .cra_driver_name = "atmel-authenc-hmac-sha256-cbc-aes",
2305 .cra_priority = ATMEL_AES_PRIORITY,
2306 .cra_flags = CRYPTO_ALG_ASYNC,
2307 .cra_blocksize = AES_BLOCK_SIZE,
2308 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2309 .cra_alignmask = 0xf,
2310 .cra_module = THIS_MODULE,
2314 .setkey = atmel_aes_authenc_setkey,
2315 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2316 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2317 .init = atmel_aes_authenc_hmac_sha384_init_tfm,
2318 .exit = atmel_aes_authenc_exit_tfm,
2319 .ivsize = AES_BLOCK_SIZE,
2320 .maxauthsize = SHA384_DIGEST_SIZE,
2323 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2324 .cra_driver_name = "atmel-authenc-hmac-sha384-cbc-aes",
2325 .cra_priority = ATMEL_AES_PRIORITY,
2326 .cra_flags = CRYPTO_ALG_ASYNC,
2327 .cra_blocksize = AES_BLOCK_SIZE,
2328 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2329 .cra_alignmask = 0xf,
2330 .cra_module = THIS_MODULE,
2334 .setkey = atmel_aes_authenc_setkey,
2335 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2336 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2337 .init = atmel_aes_authenc_hmac_sha512_init_tfm,
2338 .exit = atmel_aes_authenc_exit_tfm,
2339 .ivsize = AES_BLOCK_SIZE,
2340 .maxauthsize = SHA512_DIGEST_SIZE,
2343 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2344 .cra_driver_name = "atmel-authenc-hmac-sha512-cbc-aes",
2345 .cra_priority = ATMEL_AES_PRIORITY,
2346 .cra_flags = CRYPTO_ALG_ASYNC,
2347 .cra_blocksize = AES_BLOCK_SIZE,
2348 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2349 .cra_alignmask = 0xf,
2350 .cra_module = THIS_MODULE,
2354 #endif /* CONFIG_CRYPTO_DEV_ATMEL_AUTHENC */
2356 /* Probe functions */
2358 static int atmel_aes_buff_init(struct atmel_aes_dev *dd)
2360 dd->buf = (void *)__get_free_pages(GFP_KERNEL, ATMEL_AES_BUFFER_ORDER);
2361 dd->buflen = ATMEL_AES_BUFFER_SIZE;
2362 dd->buflen &= ~(AES_BLOCK_SIZE - 1);
2365 dev_err(dd->dev, "unable to alloc pages.\n");
2372 static void atmel_aes_buff_cleanup(struct atmel_aes_dev *dd)
2374 free_page((unsigned long)dd->buf);
2377 static bool atmel_aes_filter(struct dma_chan *chan, void *slave)
2379 struct at_dma_slave *sl = slave;
2381 if (sl && sl->dma_dev == chan->device->dev) {
2389 static int atmel_aes_dma_init(struct atmel_aes_dev *dd,
2390 struct crypto_platform_data *pdata)
2392 struct at_dma_slave *slave;
2393 dma_cap_mask_t mask;
2396 dma_cap_set(DMA_SLAVE, mask);
2398 /* Try to grab 2 DMA channels */
2399 slave = &pdata->dma_slave->rxdata;
2400 dd->src.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
2401 slave, dd->dev, "tx");
2405 slave = &pdata->dma_slave->txdata;
2406 dd->dst.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
2407 slave, dd->dev, "rx");
2414 dma_release_channel(dd->src.chan);
2416 dev_warn(dd->dev, "no DMA channel available\n");
2420 static void atmel_aes_dma_cleanup(struct atmel_aes_dev *dd)
2422 dma_release_channel(dd->dst.chan);
2423 dma_release_channel(dd->src.chan);
2426 static void atmel_aes_queue_task(unsigned long data)
2428 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
2430 atmel_aes_handle_queue(dd, NULL);
2433 static void atmel_aes_done_task(unsigned long data)
2435 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
2437 dd->is_async = true;
2438 (void)dd->resume(dd);
2441 static irqreturn_t atmel_aes_irq(int irq, void *dev_id)
2443 struct atmel_aes_dev *aes_dd = dev_id;
2446 reg = atmel_aes_read(aes_dd, AES_ISR);
2447 if (reg & atmel_aes_read(aes_dd, AES_IMR)) {
2448 atmel_aes_write(aes_dd, AES_IDR, reg);
2449 if (AES_FLAGS_BUSY & aes_dd->flags)
2450 tasklet_schedule(&aes_dd->done_task);
2452 dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n");
2459 static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)
2463 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
2464 if (dd->caps.has_authenc)
2465 for (i = 0; i < ARRAY_SIZE(aes_authenc_algs); i++)
2466 crypto_unregister_aead(&aes_authenc_algs[i]);
2469 if (dd->caps.has_xts)
2470 crypto_unregister_alg(&aes_xts_alg);
2472 if (dd->caps.has_gcm)
2473 crypto_unregister_aead(&aes_gcm_alg);
2475 if (dd->caps.has_cfb64)
2476 crypto_unregister_alg(&aes_cfb64_alg);
2478 for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
2479 crypto_unregister_alg(&aes_algs[i]);
2482 static int atmel_aes_register_algs(struct atmel_aes_dev *dd)
2486 for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
2487 err = crypto_register_alg(&aes_algs[i]);
2492 if (dd->caps.has_cfb64) {
2493 err = crypto_register_alg(&aes_cfb64_alg);
2495 goto err_aes_cfb64_alg;
2498 if (dd->caps.has_gcm) {
2499 err = crypto_register_aead(&aes_gcm_alg);
2501 goto err_aes_gcm_alg;
2504 if (dd->caps.has_xts) {
2505 err = crypto_register_alg(&aes_xts_alg);
2507 goto err_aes_xts_alg;
2510 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
2511 if (dd->caps.has_authenc) {
2512 for (i = 0; i < ARRAY_SIZE(aes_authenc_algs); i++) {
2513 err = crypto_register_aead(&aes_authenc_algs[i]);
2515 goto err_aes_authenc_alg;
2522 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
2523 /* i = ARRAY_SIZE(aes_authenc_algs); */
2524 err_aes_authenc_alg:
2525 for (j = 0; j < i; j++)
2526 crypto_unregister_aead(&aes_authenc_algs[j]);
2527 crypto_unregister_alg(&aes_xts_alg);
2530 crypto_unregister_aead(&aes_gcm_alg);
2532 crypto_unregister_alg(&aes_cfb64_alg);
2534 i = ARRAY_SIZE(aes_algs);
2536 for (j = 0; j < i; j++)
2537 crypto_unregister_alg(&aes_algs[j]);
2542 static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
2544 dd->caps.has_dualbuff = 0;
2545 dd->caps.has_cfb64 = 0;
2546 dd->caps.has_gcm = 0;
2547 dd->caps.has_xts = 0;
2548 dd->caps.has_authenc = 0;
2549 dd->caps.max_burst_size = 1;
2551 /* keep only major version number */
2552 switch (dd->hw_version & 0xff0) {
2554 dd->caps.has_dualbuff = 1;
2555 dd->caps.has_cfb64 = 1;
2556 dd->caps.has_gcm = 1;
2557 dd->caps.has_xts = 1;
2558 dd->caps.has_authenc = 1;
2559 dd->caps.max_burst_size = 4;
2562 dd->caps.has_dualbuff = 1;
2563 dd->caps.has_cfb64 = 1;
2564 dd->caps.has_gcm = 1;
2565 dd->caps.max_burst_size = 4;
2568 dd->caps.has_dualbuff = 1;
2569 dd->caps.has_cfb64 = 1;
2570 dd->caps.max_burst_size = 4;
2576 "Unmanaged aes version, set minimum capabilities\n");
2581 #if defined(CONFIG_OF)
2582 static const struct of_device_id atmel_aes_dt_ids[] = {
2583 { .compatible = "atmel,at91sam9g46-aes" },
2586 MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids);
2588 static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
2590 struct device_node *np = pdev->dev.of_node;
2591 struct crypto_platform_data *pdata;
2594 dev_err(&pdev->dev, "device node not found\n");
2595 return ERR_PTR(-EINVAL);
2598 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
2600 return ERR_PTR(-ENOMEM);
2602 pdata->dma_slave = devm_kzalloc(&pdev->dev,
2603 sizeof(*(pdata->dma_slave)),
2605 if (!pdata->dma_slave) {
2606 devm_kfree(&pdev->dev, pdata);
2607 return ERR_PTR(-ENOMEM);
2613 static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
2615 return ERR_PTR(-EINVAL);
2619 static int atmel_aes_probe(struct platform_device *pdev)
2621 struct atmel_aes_dev *aes_dd;
2622 struct crypto_platform_data *pdata;
2623 struct device *dev = &pdev->dev;
2624 struct resource *aes_res;
2627 pdata = pdev->dev.platform_data;
2629 pdata = atmel_aes_of_init(pdev);
2630 if (IS_ERR(pdata)) {
2631 err = PTR_ERR(pdata);
2636 if (!pdata->dma_slave) {
2641 aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL);
2642 if (aes_dd == NULL) {
2649 platform_set_drvdata(pdev, aes_dd);
2651 INIT_LIST_HEAD(&aes_dd->list);
2652 spin_lock_init(&aes_dd->lock);
2654 tasklet_init(&aes_dd->done_task, atmel_aes_done_task,
2655 (unsigned long)aes_dd);
2656 tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task,
2657 (unsigned long)aes_dd);
2659 crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH);
2661 /* Get the base address */
2662 aes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2664 dev_err(dev, "no MEM resource info\n");
2668 aes_dd->phys_base = aes_res->start;
2671 aes_dd->irq = platform_get_irq(pdev, 0);
2672 if (aes_dd->irq < 0) {
2673 dev_err(dev, "no IRQ resource info\n");
2678 err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq,
2679 IRQF_SHARED, "atmel-aes", aes_dd);
2681 dev_err(dev, "unable to request aes irq.\n");
2685 /* Initializing the clock */
2686 aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk");
2687 if (IS_ERR(aes_dd->iclk)) {
2688 dev_err(dev, "clock initialization failed.\n");
2689 err = PTR_ERR(aes_dd->iclk);
2693 aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res);
2694 if (IS_ERR(aes_dd->io_base)) {
2695 dev_err(dev, "can't ioremap\n");
2696 err = PTR_ERR(aes_dd->io_base);
2700 err = clk_prepare(aes_dd->iclk);
2704 err = atmel_aes_hw_version_init(aes_dd);
2706 goto iclk_unprepare;
2708 atmel_aes_get_cap(aes_dd);
2710 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
2711 if (aes_dd->caps.has_authenc && !atmel_sha_authenc_is_ready()) {
2712 err = -EPROBE_DEFER;
2713 goto iclk_unprepare;
2717 err = atmel_aes_buff_init(aes_dd);
2721 err = atmel_aes_dma_init(aes_dd, pdata);
2725 spin_lock(&atmel_aes.lock);
2726 list_add_tail(&aes_dd->list, &atmel_aes.dev_list);
2727 spin_unlock(&atmel_aes.lock);
2729 err = atmel_aes_register_algs(aes_dd);
2733 dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n",
2734 dma_chan_name(aes_dd->src.chan),
2735 dma_chan_name(aes_dd->dst.chan));
2740 spin_lock(&atmel_aes.lock);
2741 list_del(&aes_dd->list);
2742 spin_unlock(&atmel_aes.lock);
2743 atmel_aes_dma_cleanup(aes_dd);
2745 atmel_aes_buff_cleanup(aes_dd);
2748 clk_unprepare(aes_dd->iclk);
2750 tasklet_kill(&aes_dd->done_task);
2751 tasklet_kill(&aes_dd->queue_task);
2753 if (err != -EPROBE_DEFER)
2754 dev_err(dev, "initialization failed.\n");
2759 static int atmel_aes_remove(struct platform_device *pdev)
2761 struct atmel_aes_dev *aes_dd;
2763 aes_dd = platform_get_drvdata(pdev);
2766 spin_lock(&atmel_aes.lock);
2767 list_del(&aes_dd->list);
2768 spin_unlock(&atmel_aes.lock);
2770 atmel_aes_unregister_algs(aes_dd);
2772 tasklet_kill(&aes_dd->done_task);
2773 tasklet_kill(&aes_dd->queue_task);
2775 atmel_aes_dma_cleanup(aes_dd);
2776 atmel_aes_buff_cleanup(aes_dd);
2778 clk_unprepare(aes_dd->iclk);
2783 static struct platform_driver atmel_aes_driver = {
2784 .probe = atmel_aes_probe,
2785 .remove = atmel_aes_remove,
2787 .name = "atmel_aes",
2788 .of_match_table = of_match_ptr(atmel_aes_dt_ids),
2792 module_platform_driver(atmel_aes_driver);
2794 MODULE_DESCRIPTION("Atmel AES hw acceleration support.");
2795 MODULE_LICENSE("GPL v2");
2796 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");