drivers/crypto/amcc/crypto4xx_core.c

   1 /**
   2  * AMCC SoC PPC4xx Crypto Driver
   3  *
   4  * Copyright (c) 2008 Applied Micro Circuits Corporation.
   5  * All rights reserved. James Hsiao <jhsiao@amcc.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * This file implements AMCC crypto offload Linux device driver for use with
  18  * Linux CryptoAPI.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/spinlock_types.h>
  24 #include <linux/random.h>
  25 #include <linux/scatterlist.h>
  26 #include <linux/crypto.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/init.h>
  30 #include <linux/module.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/slab.h>
  35 #include <asm/dcr.h>
  36 #include <asm/dcr-regs.h>
  37 #include <asm/cacheflush.h>
  38 #include <crypto/aes.h>
  39 #include <crypto/sha.h>
  40 #include "crypto4xx_reg_def.h"
  41 #include "crypto4xx_core.h"
  42 #include "crypto4xx_sa.h"
  43 #include "crypto4xx_trng.h"
  44
  45 #define PPC4XX_SEC_VERSION_STR                  "0.5"
  46
  47 /**
  48  * PPC4xx Crypto Engine Initialization Routine
  49  */
  50 static void crypto4xx_hw_init(struct crypto4xx_device *dev)
  51 {
  52         union ce_ring_size ring_size;
  53         union ce_ring_control ring_ctrl;
  54         union ce_part_ring_size part_ring_size;
  55         union ce_io_threshold io_threshold;
  56         u32 rand_num;
  57         union ce_pe_dma_cfg pe_dma_cfg;
  58         u32 device_ctrl;
  59
  60         writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG);
  61         /* setup pe dma, include reset sg, pdr and pe, then release reset */
  62         pe_dma_cfg.w = 0;
  63         pe_dma_cfg.bf.bo_sgpd_en = 1;
  64         pe_dma_cfg.bf.bo_data_en = 0;
  65         pe_dma_cfg.bf.bo_sa_en = 1;
  66         pe_dma_cfg.bf.bo_pd_en = 1;
  67         pe_dma_cfg.bf.dynamic_sa_en = 1;
  68         pe_dma_cfg.bf.reset_sg = 1;
  69         pe_dma_cfg.bf.reset_pdr = 1;
  70         pe_dma_cfg.bf.reset_pe = 1;
  71         writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
  72         /* un reset pe,sg and pdr */
  73         pe_dma_cfg.bf.pe_mode = 0;
  74         pe_dma_cfg.bf.reset_sg = 0;
  75         pe_dma_cfg.bf.reset_pdr = 0;
  76         pe_dma_cfg.bf.reset_pe = 0;
  77         pe_dma_cfg.bf.bo_td_en = 0;
  78         writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
  79         writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_PDR_BASE);
  80         writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_RDR_BASE);
  81         writel(PPC4XX_PRNG_CTRL_AUTO_EN, dev->ce_base + CRYPTO4XX_PRNG_CTRL);
  82         get_random_bytes(&rand_num, sizeof(rand_num));
  83         writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_L);
  84         get_random_bytes(&rand_num, sizeof(rand_num));
  85         writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_H);
  86         ring_size.w = 0;
  87         ring_size.bf.ring_offset = PPC4XX_PD_SIZE;
  88         ring_size.bf.ring_size   = PPC4XX_NUM_PD;
  89         writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE);
  90         ring_ctrl.w = 0;
  91         writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL);
  92         device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
  93         device_ctrl |= PPC4XX_DC_3DES_EN;
  94         writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
  95         writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE);
  96         writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE);
  97         part_ring_size.w = 0;
  98         part_ring_size.bf.sdr_size = PPC4XX_SDR_SIZE;
  99         part_ring_size.bf.gdr_size = PPC4XX_GDR_SIZE;
 100         writel(part_ring_size.w, dev->ce_base + CRYPTO4XX_PART_RING_SIZE);
 101         writel(PPC4XX_SD_BUFFER_SIZE, dev->ce_base + CRYPTO4XX_PART_RING_CFG);
 102         io_threshold.w = 0;
 103         io_threshold.bf.output_threshold = PPC4XX_OUTPUT_THRESHOLD;
 104         io_threshold.bf.input_threshold  = PPC4XX_INPUT_THRESHOLD;
 105         writel(io_threshold.w, dev->ce_base + CRYPTO4XX_IO_THRESHOLD);
 106         writel(0, dev->ce_base + CRYPTO4XX_PDR_BASE_UADDR);
 107         writel(0, dev->ce_base + CRYPTO4XX_RDR_BASE_UADDR);
 108         writel(0, dev->ce_base + CRYPTO4XX_PKT_SRC_UADDR);
 109         writel(0, dev->ce_base + CRYPTO4XX_PKT_DEST_UADDR);
 110         writel(0, dev->ce_base + CRYPTO4XX_SA_UADDR);
 111         writel(0, dev->ce_base + CRYPTO4XX_GATH_RING_BASE_UADDR);
 112         writel(0, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE_UADDR);
 113         /* un reset pe,sg and pdr */
 114         pe_dma_cfg.bf.pe_mode = 1;
 115         pe_dma_cfg.bf.reset_sg = 0;
 116         pe_dma_cfg.bf.reset_pdr = 0;
 117         pe_dma_cfg.bf.reset_pe = 0;
 118         pe_dma_cfg.bf.bo_td_en = 0;
 119         writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
 120         /*clear all pending interrupt*/
 121         writel(PPC4XX_INTERRUPT_CLR, dev->ce_base + CRYPTO4XX_INT_CLR);
 122         writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
 123         writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
 124         writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG);
 125         writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN);
 126 }
 127
 128 int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size)
 129 {
 130         ctx->sa_in = dma_alloc_coherent(ctx->dev->core_dev->device, size * 4,
 131                                         &ctx->sa_in_dma_addr, GFP_ATOMIC);
 132         if (ctx->sa_in == NULL)
 133                 return -ENOMEM;
 134
 135         ctx->sa_out = dma_alloc_coherent(ctx->dev->core_dev->device, size * 4,
 136                                          &ctx->sa_out_dma_addr, GFP_ATOMIC);
 137         if (ctx->sa_out == NULL) {
 138                 dma_free_coherent(ctx->dev->core_dev->device, size * 4,
 139                                   ctx->sa_in, ctx->sa_in_dma_addr);
 140                 return -ENOMEM;
 141         }
 142
 143         memset(ctx->sa_in, 0, size * 4);
 144         memset(ctx->sa_out, 0, size * 4);
 145         ctx->sa_len = size;
 146
 147         return 0;
 148 }
 149
 150 void crypto4xx_free_sa(struct crypto4xx_ctx *ctx)
 151 {
 152         if (ctx->sa_in != NULL)
 153                 dma_free_coherent(ctx->dev->core_dev->device, ctx->sa_len * 4,
 154                                   ctx->sa_in, ctx->sa_in_dma_addr);
 155         if (ctx->sa_out != NULL)
 156                 dma_free_coherent(ctx->dev->core_dev->device, ctx->sa_len * 4,
 157                                   ctx->sa_out, ctx->sa_out_dma_addr);
 158
 159         ctx->sa_in_dma_addr = 0;
 160         ctx->sa_out_dma_addr = 0;
 161         ctx->sa_len = 0;
 162 }
 163
 164 u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx)
 165 {
 166         ctx->state_record = dma_alloc_coherent(ctx->dev->core_dev->device,
 167                                 sizeof(struct sa_state_record),
 168                                 &ctx->state_record_dma_addr, GFP_ATOMIC);
 169         if (!ctx->state_record_dma_addr)
 170                 return -ENOMEM;
 171         memset(ctx->state_record, 0, sizeof(struct sa_state_record));
 172
 173         return 0;
 174 }
 175
 176 void crypto4xx_free_state_record(struct crypto4xx_ctx *ctx)
 177 {
 178         if (ctx->state_record != NULL)
 179                 dma_free_coherent(ctx->dev->core_dev->device,
 180                                   sizeof(struct sa_state_record),
 181                                   ctx->state_record,
 182                                   ctx->state_record_dma_addr);
 183         ctx->state_record_dma_addr = 0;
 184 }
 185
 186 /**
 187  * alloc memory for the gather ring
 188  * no need to alloc buf for the ring
 189  * gdr_tail, gdr_head and gdr_count are initialized by this function
 190  */
 191 static u32 crypto4xx_build_pdr(struct crypto4xx_device *dev)
 192 {
 193         int i;
 194         struct pd_uinfo *pd_uinfo;
 195         dev->pdr = dma_alloc_coherent(dev->core_dev->device,
 196                                       sizeof(struct ce_pd) * PPC4XX_NUM_PD,
 197                                       &dev->pdr_pa, GFP_ATOMIC);
 198         if (!dev->pdr)
 199                 return -ENOMEM;
 200
 201         dev->pdr_uinfo = kzalloc(sizeof(struct pd_uinfo) * PPC4XX_NUM_PD,
 202                                 GFP_KERNEL);
 203         if (!dev->pdr_uinfo) {
 204                 dma_free_coherent(dev->core_dev->device,
 205                                   sizeof(struct ce_pd) * PPC4XX_NUM_PD,
 206                                   dev->pdr,
 207                                   dev->pdr_pa);
 208                 return -ENOMEM;
 209         }
 210         memset(dev->pdr, 0, sizeof(struct ce_pd) * PPC4XX_NUM_PD);
 211         dev->shadow_sa_pool = dma_alloc_coherent(dev->core_dev->device,
 212                                    256 * PPC4XX_NUM_PD,
 213                                    &dev->shadow_sa_pool_pa,
 214                                    GFP_ATOMIC);
 215         if (!dev->shadow_sa_pool)
 216                 return -ENOMEM;
 217
 218         dev->shadow_sr_pool = dma_alloc_coherent(dev->core_dev->device,
 219                          sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
 220                          &dev->shadow_sr_pool_pa, GFP_ATOMIC);
 221         if (!dev->shadow_sr_pool)
 222                 return -ENOMEM;
 223         for (i = 0; i < PPC4XX_NUM_PD; i++) {
 224                 pd_uinfo = (struct pd_uinfo *) (dev->pdr_uinfo +
 225                                                 sizeof(struct pd_uinfo) * i);
 226
 227                 /* alloc 256 bytes which is enough for any kind of dynamic sa */
 228                 pd_uinfo->sa_va = dev->shadow_sa_pool + 256 * i;
 229                 pd_uinfo->sa_pa = dev->shadow_sa_pool_pa + 256 * i;
 230
 231                 /* alloc state record */
 232                 pd_uinfo->sr_va = dev->shadow_sr_pool +
 233                     sizeof(struct sa_state_record) * i;
 234                 pd_uinfo->sr_pa = dev->shadow_sr_pool_pa +
 235                     sizeof(struct sa_state_record) * i;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static void crypto4xx_destroy_pdr(struct crypto4xx_device *dev)
 242 {
 243         if (dev->pdr)
 244                 dma_free_coherent(dev->core_dev->device,
 245                                   sizeof(struct ce_pd) * PPC4XX_NUM_PD,
 246                                   dev->pdr, dev->pdr_pa);
 247
 248         if (dev->shadow_sa_pool)
 249                 dma_free_coherent(dev->core_dev->device, 256 * PPC4XX_NUM_PD,
 250                                   dev->shadow_sa_pool, dev->shadow_sa_pool_pa);
 251
 252         if (dev->shadow_sr_pool)
 253                 dma_free_coherent(dev->core_dev->device,
 254                         sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
 255                         dev->shadow_sr_pool, dev->shadow_sr_pool_pa);
 256
 257         kfree(dev->pdr_uinfo);
 258 }
 259
 260 static u32 crypto4xx_get_pd_from_pdr_nolock(struct crypto4xx_device *dev)
 261 {
 262         u32 retval;
 263         u32 tmp;
 264
 265         retval = dev->pdr_head;
 266         tmp = (dev->pdr_head + 1) % PPC4XX_NUM_PD;
 267
 268         if (tmp == dev->pdr_tail)
 269                 return ERING_WAS_FULL;
 270
 271         dev->pdr_head = tmp;
 272
 273         return retval;
 274 }
 275
 276 static u32 crypto4xx_put_pd_to_pdr(struct crypto4xx_device *dev, u32 idx)
 277 {
 278         struct pd_uinfo *pd_uinfo;
 279         unsigned long flags;
 280
 281         pd_uinfo = (struct pd_uinfo *)(dev->pdr_uinfo +
 282                                        sizeof(struct pd_uinfo) * idx);
 283         spin_lock_irqsave(&dev->core_dev->lock, flags);
 284         if (dev->pdr_tail != PPC4XX_LAST_PD)
 285                 dev->pdr_tail++;
 286         else
 287                 dev->pdr_tail = 0;
 288         pd_uinfo->state = PD_ENTRY_FREE;
 289         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 290
 291         return 0;
 292 }
 293
 294 static struct ce_pd *crypto4xx_get_pdp(struct crypto4xx_device *dev,
 295                                        dma_addr_t *pd_dma, u32 idx)
 296 {
 297         *pd_dma = dev->pdr_pa + sizeof(struct ce_pd) * idx;
 298
 299         return dev->pdr + sizeof(struct ce_pd) * idx;
 300 }
 301
 302 /**
 303  * alloc memory for the gather ring
 304  * no need to alloc buf for the ring
 305  * gdr_tail, gdr_head and gdr_count are initialized by this function
 306  */
 307 static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev)
 308 {
 309         dev->gdr = dma_alloc_coherent(dev->core_dev->device,
 310                                       sizeof(struct ce_gd) * PPC4XX_NUM_GD,
 311                                       &dev->gdr_pa, GFP_ATOMIC);
 312         if (!dev->gdr)
 313                 return -ENOMEM;
 314
 315         memset(dev->gdr, 0, sizeof(struct ce_gd) * PPC4XX_NUM_GD);
 316
 317         return 0;
 318 }
 319
 320 static inline void crypto4xx_destroy_gdr(struct crypto4xx_device *dev)
 321 {
 322         dma_free_coherent(dev->core_dev->device,
 323                           sizeof(struct ce_gd) * PPC4XX_NUM_GD,
 324                           dev->gdr, dev->gdr_pa);
 325 }
 326
 327 /*
 328  * when this function is called.
 329  * preemption or interrupt must be disabled
 330  */
 331 u32 crypto4xx_get_n_gd(struct crypto4xx_device *dev, int n)
 332 {
 333         u32 retval;
 334         u32 tmp;
 335         if (n >= PPC4XX_NUM_GD)
 336                 return ERING_WAS_FULL;
 337
 338         retval = dev->gdr_head;
 339         tmp = (dev->gdr_head + n) % PPC4XX_NUM_GD;
 340         if (dev->gdr_head > dev->gdr_tail) {
 341                 if (tmp < dev->gdr_head && tmp >= dev->gdr_tail)
 342                         return ERING_WAS_FULL;
 343         } else if (dev->gdr_head < dev->gdr_tail) {
 344                 if (tmp < dev->gdr_head || tmp >= dev->gdr_tail)
 345                         return ERING_WAS_FULL;
 346         }
 347         dev->gdr_head = tmp;
 348
 349         return retval;
 350 }
 351
 352 static u32 crypto4xx_put_gd_to_gdr(struct crypto4xx_device *dev)
 353 {
 354         unsigned long flags;
 355
 356         spin_lock_irqsave(&dev->core_dev->lock, flags);
 357         if (dev->gdr_tail == dev->gdr_head) {
 358                 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 359                 return 0;
 360         }
 361
 362         if (dev->gdr_tail != PPC4XX_LAST_GD)
 363                 dev->gdr_tail++;
 364         else
 365                 dev->gdr_tail = 0;
 366
 367         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 368
 369         return 0;
 370 }
 371
 372 static inline struct ce_gd *crypto4xx_get_gdp(struct crypto4xx_device *dev,
 373                                               dma_addr_t *gd_dma, u32 idx)
 374 {
 375         *gd_dma = dev->gdr_pa + sizeof(struct ce_gd) * idx;
 376
 377         return (struct ce_gd *) (dev->gdr + sizeof(struct ce_gd) * idx);
 378 }
 379
 380 /**
 381  * alloc memory for the scatter ring
 382  * need to alloc buf for the ring
 383  * sdr_tail, sdr_head and sdr_count are initialized by this function
 384  */
 385 static u32 crypto4xx_build_sdr(struct crypto4xx_device *dev)
 386 {
 387         int i;
 388         struct ce_sd *sd_array;
 389
 390         /* alloc memory for scatter descriptor ring */
 391         dev->sdr = dma_alloc_coherent(dev->core_dev->device,
 392                                       sizeof(struct ce_sd) * PPC4XX_NUM_SD,
 393                                       &dev->sdr_pa, GFP_ATOMIC);
 394         if (!dev->sdr)
 395                 return -ENOMEM;
 396
 397         dev->scatter_buffer_size = PPC4XX_SD_BUFFER_SIZE;
 398         dev->scatter_buffer_va =
 399                 dma_alloc_coherent(dev->core_dev->device,
 400                         dev->scatter_buffer_size * PPC4XX_NUM_SD,
 401                         &dev->scatter_buffer_pa, GFP_ATOMIC);
 402         if (!dev->scatter_buffer_va)
 403                 return -ENOMEM;
 404
 405         sd_array = dev->sdr;
 406
 407         for (i = 0; i < PPC4XX_NUM_SD; i++) {
 408                 sd_array[i].ptr = dev->scatter_buffer_pa +
 409                                   dev->scatter_buffer_size * i;
 410         }
 411
 412         return 0;
 413 }
 414
 415 static void crypto4xx_destroy_sdr(struct crypto4xx_device *dev)
 416 {
 417         if (dev->sdr)
 418                 dma_free_coherent(dev->core_dev->device,
 419                                   sizeof(struct ce_sd) * PPC4XX_NUM_SD,
 420                                   dev->sdr, dev->sdr_pa);
 421
 422         if (dev->scatter_buffer_va)
 423                 dma_free_coherent(dev->core_dev->device,
 424                                   dev->scatter_buffer_size * PPC4XX_NUM_SD,
 425                                   dev->scatter_buffer_va,
 426                                   dev->scatter_buffer_pa);
 427 }
 428
 429 /*
 430  * when this function is called.
 431  * preemption or interrupt must be disabled
 432  */
 433 static u32 crypto4xx_get_n_sd(struct crypto4xx_device *dev, int n)
 434 {
 435         u32 retval;
 436         u32 tmp;
 437
 438         if (n >= PPC4XX_NUM_SD)
 439                 return ERING_WAS_FULL;
 440
 441         retval = dev->sdr_head;
 442         tmp = (dev->sdr_head + n) % PPC4XX_NUM_SD;
 443         if (dev->sdr_head > dev->gdr_tail) {
 444                 if (tmp < dev->sdr_head && tmp >= dev->sdr_tail)
 445                         return ERING_WAS_FULL;
 446         } else if (dev->sdr_head < dev->sdr_tail) {
 447                 if (tmp < dev->sdr_head || tmp >= dev->sdr_tail)
 448                         return ERING_WAS_FULL;
 449         } /* the head = tail, or empty case is already take cared */
 450         dev->sdr_head = tmp;
 451
 452         return retval;
 453 }
 454
 455 static u32 crypto4xx_put_sd_to_sdr(struct crypto4xx_device *dev)
 456 {
 457         unsigned long flags;
 458
 459         spin_lock_irqsave(&dev->core_dev->lock, flags);
 460         if (dev->sdr_tail == dev->sdr_head) {
 461                 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 462                 return 0;
 463         }
 464         if (dev->sdr_tail != PPC4XX_LAST_SD)
 465                 dev->sdr_tail++;
 466         else
 467                 dev->sdr_tail = 0;
 468         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 469
 470         return 0;
 471 }
 472
 473 static inline struct ce_sd *crypto4xx_get_sdp(struct crypto4xx_device *dev,
 474                                               dma_addr_t *sd_dma, u32 idx)
 475 {
 476         *sd_dma = dev->sdr_pa + sizeof(struct ce_sd) * idx;
 477
 478         return  (struct ce_sd *)(dev->sdr + sizeof(struct ce_sd) * idx);
 479 }
 480
 481 static u32 crypto4xx_fill_one_page(struct crypto4xx_device *dev,
 482                                    dma_addr_t *addr, u32 *length,
 483                                    u32 *idx, u32 *offset, u32 *nbytes)
 484 {
 485         u32 len;
 486
 487         if (*length > dev->scatter_buffer_size) {
 488                 memcpy(phys_to_virt(*addr),
 489                         dev->scatter_buffer_va +
 490                         *idx * dev->scatter_buffer_size + *offset,
 491                         dev->scatter_buffer_size);
 492                 *offset = 0;
 493                 *length -= dev->scatter_buffer_size;
 494                 *nbytes -= dev->scatter_buffer_size;
 495                 if (*idx == PPC4XX_LAST_SD)
 496                         *idx = 0;
 497                 else
 498                         (*idx)++;
 499                 *addr = *addr +  dev->scatter_buffer_size;
 500                 return 1;
 501         } else if (*length < dev->scatter_buffer_size) {
 502                 memcpy(phys_to_virt(*addr),
 503                         dev->scatter_buffer_va +
 504                         *idx * dev->scatter_buffer_size + *offset, *length);
 505                 if ((*offset + *length) == dev->scatter_buffer_size) {
 506                         if (*idx == PPC4XX_LAST_SD)
 507                                 *idx = 0;
 508                         else
 509                                 (*idx)++;
 510                         *nbytes -= *length;
 511                         *offset = 0;
 512                 } else {
 513                         *nbytes -= *length;
 514                         *offset += *length;
 515                 }
 516
 517                 return 0;
 518         } else {
 519                 len = (*nbytes <= dev->scatter_buffer_size) ?
 520                                 (*nbytes) : dev->scatter_buffer_size;
 521                 memcpy(phys_to_virt(*addr),
 522                         dev->scatter_buffer_va +
 523                         *idx * dev->scatter_buffer_size + *offset,
 524                         len);
 525                 *offset = 0;
 526                 *nbytes -= len;
 527
 528                 if (*idx == PPC4XX_LAST_SD)
 529                         *idx = 0;
 530                 else
 531                         (*idx)++;
 532
 533                 return 0;
 534     }
 535 }
 536
 537 static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev,
 538                                       struct ce_pd *pd,
 539                                       struct pd_uinfo *pd_uinfo,
 540                                       u32 nbytes,
 541                                       struct scatterlist *dst)
 542 {
 543         dma_addr_t addr;
 544         u32 this_sd;
 545         u32 offset;
 546         u32 len;
 547         u32 i;
 548         u32 sg_len;
 549         struct scatterlist *sg;
 550
 551         this_sd = pd_uinfo->first_sd;
 552         offset = 0;
 553         i = 0;
 554
 555         while (nbytes) {
 556                 sg = &dst[i];
 557                 sg_len = sg->length;
 558                 addr = dma_map_page(dev->core_dev->device, sg_page(sg),
 559                                 sg->offset, sg->length, DMA_TO_DEVICE);
 560
 561                 if (offset == 0) {
 562                         len = (nbytes <= sg->length) ? nbytes : sg->length;
 563                         while (crypto4xx_fill_one_page(dev, &addr, &len,
 564                                 &this_sd, &offset, &nbytes))
 565                                 ;
 566                         if (!nbytes)
 567                                 return;
 568                         i++;
 569                 } else {
 570                         len = (nbytes <= (dev->scatter_buffer_size - offset)) ?
 571                                 nbytes : (dev->scatter_buffer_size - offset);
 572                         len = (sg->length < len) ? sg->length : len;
 573                         while (crypto4xx_fill_one_page(dev, &addr, &len,
 574                                                &this_sd, &offset, &nbytes))
 575                                 ;
 576                         if (!nbytes)
 577                                 return;
 578                         sg_len -= len;
 579                         if (sg_len) {
 580                                 addr += len;
 581                                 while (crypto4xx_fill_one_page(dev, &addr,
 582                                         &sg_len, &this_sd, &offset, &nbytes))
 583                                         ;
 584                         }
 585                         i++;
 586                 }
 587         }
 588 }
 589
 590 static u32 crypto4xx_copy_digest_to_dst(struct pd_uinfo *pd_uinfo,
 591                                         struct crypto4xx_ctx *ctx)
 592 {
 593         struct dynamic_sa_ctl *sa = (struct dynamic_sa_ctl *) ctx->sa_in;
 594         struct sa_state_record *state_record =
 595                                 (struct sa_state_record *) pd_uinfo->sr_va;
 596
 597         if (sa->sa_command_0.bf.hash_alg == SA_HASH_ALG_SHA1) {
 598                 memcpy((void *) pd_uinfo->dest_va, state_record->save_digest,
 599                        SA_HASH_ALG_SHA1_DIGEST_SIZE);
 600         }
 601
 602         return 0;
 603 }
 604
 605 static void crypto4xx_ret_sg_desc(struct crypto4xx_device *dev,
 606                                   struct pd_uinfo *pd_uinfo)
 607 {
 608         int i;
 609         if (pd_uinfo->num_gd) {
 610                 for (i = 0; i < pd_uinfo->num_gd; i++)
 611                         crypto4xx_put_gd_to_gdr(dev);
 612                 pd_uinfo->first_gd = 0xffffffff;
 613                 pd_uinfo->num_gd = 0;
 614         }
 615         if (pd_uinfo->num_sd) {
 616                 for (i = 0; i < pd_uinfo->num_sd; i++)
 617                         crypto4xx_put_sd_to_sdr(dev);
 618
 619                 pd_uinfo->first_sd = 0xffffffff;
 620                 pd_uinfo->num_sd = 0;
 621         }
 622 }
 623
 624 static u32 crypto4xx_ablkcipher_done(struct crypto4xx_device *dev,
 625                                      struct pd_uinfo *pd_uinfo,
 626                                      struct ce_pd *pd)
 627 {
 628         struct crypto4xx_ctx *ctx;
 629         struct ablkcipher_request *ablk_req;
 630         struct scatterlist *dst;
 631         dma_addr_t addr;
 632
 633         ablk_req = ablkcipher_request_cast(pd_uinfo->async_req);
 634         ctx  = crypto_tfm_ctx(ablk_req->base.tfm);
 635
 636         if (pd_uinfo->using_sd) {
 637                 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo, ablk_req->nbytes,
 638                                           ablk_req->dst);
 639         } else {
 640                 dst = pd_uinfo->dest_va;
 641                 addr = dma_map_page(dev->core_dev->device, sg_page(dst),
 642                                     dst->offset, dst->length, DMA_FROM_DEVICE);
 643         }
 644
 645         if (pd_uinfo->sa_va->sa_command_0.bf.save_iv == SA_SAVE_IV) {
 646                 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
 647
 648                 crypto4xx_memcpy_from_le32((u32 *)req->iv,
 649                         pd_uinfo->sr_va->save_iv,
 650                         crypto_skcipher_ivsize(skcipher));
 651         }
 652
 653         crypto4xx_ret_sg_desc(dev, pd_uinfo);
 654         if (ablk_req->base.complete != NULL)
 655                 ablk_req->base.complete(&ablk_req->base, 0);
 656
 657         return 0;
 658 }
 659
 660 static u32 crypto4xx_ahash_done(struct crypto4xx_device *dev,
 661                                 struct pd_uinfo *pd_uinfo)
 662 {
 663         struct crypto4xx_ctx *ctx;
 664         struct ahash_request *ahash_req;
 665
 666         ahash_req = ahash_request_cast(pd_uinfo->async_req);
 667         ctx  = crypto_tfm_ctx(ahash_req->base.tfm);
 668
 669         crypto4xx_copy_digest_to_dst(pd_uinfo,
 670                                      crypto_tfm_ctx(ahash_req->base.tfm));
 671         crypto4xx_ret_sg_desc(dev, pd_uinfo);
 672         /* call user provided callback function x */
 673         if (ahash_req->base.complete != NULL)
 674                 ahash_req->base.complete(&ahash_req->base, 0);
 675
 676         return 0;
 677 }
 678
 679 static u32 crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
 680 {
 681         struct ce_pd *pd;
 682         struct pd_uinfo *pd_uinfo;
 683
 684         pd =  dev->pdr + sizeof(struct ce_pd)*idx;
 685         pd_uinfo = dev->pdr_uinfo + sizeof(struct pd_uinfo)*idx;
 686         if (crypto_tfm_alg_type(pd_uinfo->async_req->tfm) ==
 687                         CRYPTO_ALG_TYPE_ABLKCIPHER)
 688                 return crypto4xx_ablkcipher_done(dev, pd_uinfo, pd);
 689         else
 690                 return crypto4xx_ahash_done(dev, pd_uinfo);
 691 }
 692
 693 /**
 694  * Note: Only use this function to copy items that is word aligned.
 695  */
 696 void crypto4xx_memcpy_le(unsigned int *dst,
 697                          const unsigned char *buf,
 698                          int len)
 699 {
 700         u8 *tmp;
 701         for (; len >= 4; buf += 4, len -= 4)
 702                 *dst++ = cpu_to_le32(*(unsigned int *) buf);
 703
 704         tmp = (u8 *)dst;
 705         switch (len) {
 706         case 3:
 707                 *tmp++ = 0;
 708                 *tmp++ = *(buf+2);
 709                 *tmp++ = *(buf+1);
 710                 *tmp++ = *buf;
 711                 break;
 712         case 2:
 713                 *tmp++ = 0;
 714                 *tmp++ = 0;
 715                 *tmp++ = *(buf+1);
 716                 *tmp++ = *buf;
 717                 break;
 718         case 1:
 719                 *tmp++ = 0;
 720                 *tmp++ = 0;
 721                 *tmp++ = 0;
 722                 *tmp++ = *buf;
 723                 break;
 724         default:
 725                 break;
 726         }
 727 }
 728
 729 static void crypto4xx_stop_all(struct crypto4xx_core_device *core_dev)
 730 {
 731         crypto4xx_destroy_pdr(core_dev->dev);
 732         crypto4xx_destroy_gdr(core_dev->dev);
 733         crypto4xx_destroy_sdr(core_dev->dev);
 734         iounmap(core_dev->dev->ce_base);
 735         kfree(core_dev->dev);
 736         kfree(core_dev);
 737 }
 738
 739 void crypto4xx_return_pd(struct crypto4xx_device *dev,
 740                          u32 pd_entry, struct ce_pd *pd,
 741                          struct pd_uinfo *pd_uinfo)
 742 {
 743         /* irq should be already disabled */
 744         dev->pdr_head = pd_entry;
 745         pd->pd_ctl.w = 0;
 746         pd->pd_ctl_len.w = 0;
 747         pd_uinfo->state = PD_ENTRY_FREE;
 748 }
 749
 750 static u32 get_next_gd(u32 current)
 751 {
 752         if (current != PPC4XX_LAST_GD)
 753                 return current + 1;
 754         else
 755                 return 0;
 756 }
 757
 758 static u32 get_next_sd(u32 current)
 759 {
 760         if (current != PPC4XX_LAST_SD)
 761                 return current + 1;
 762         else
 763                 return 0;
 764 }
 765
 766 u32 crypto4xx_build_pd(struct crypto_async_request *req,
 767                        struct crypto4xx_ctx *ctx,
 768                        struct scatterlist *src,
 769                        struct scatterlist *dst,
 770                        unsigned int datalen,
 771                        void *iv, u32 iv_len)
 772 {
 773         struct crypto4xx_device *dev = ctx->dev;
 774         dma_addr_t addr, pd_dma, sd_dma, gd_dma;
 775         struct dynamic_sa_ctl *sa;
 776         struct scatterlist *sg;
 777         struct ce_gd *gd;
 778         struct ce_pd *pd;
 779         u32 num_gd, num_sd;
 780         u32 fst_gd = 0xffffffff;
 781         u32 fst_sd = 0xffffffff;
 782         u32 pd_entry;
 783         unsigned long flags;
 784         struct pd_uinfo *pd_uinfo = NULL;
 785         unsigned int nbytes = datalen, idx;
 786         unsigned int ivlen = 0;
 787         u32 gd_idx = 0;
 788
 789         /* figure how many gd is needed */
 790         num_gd = sg_nents_for_len(src, datalen);
 791         if ((int)num_gd < 0) {
 792                 dev_err(dev->core_dev->device, "Invalid number of src SG.\n");
 793                 return -EINVAL;
 794         }
 795         if (num_gd == 1)
 796                 num_gd = 0;
 797
 798         /* figure how many sd is needed */
 799         if (sg_is_last(dst) || ctx->is_hash) {
 800                 num_sd = 0;
 801         } else {
 802                 if (datalen > PPC4XX_SD_BUFFER_SIZE) {
 803                         num_sd = datalen / PPC4XX_SD_BUFFER_SIZE;
 804                         if (datalen % PPC4XX_SD_BUFFER_SIZE)
 805                                 num_sd++;
 806                 } else {
 807                         num_sd = 1;
 808                 }
 809         }
 810
 811         /*
 812          * The follow section of code needs to be protected
 813          * The gather ring and scatter ring needs to be consecutive
 814          * In case of run out of any kind of descriptor, the descriptor
 815          * already got must be return the original place.
 816          */
 817         spin_lock_irqsave(&dev->core_dev->lock, flags);
 818         if (num_gd) {
 819                 fst_gd = crypto4xx_get_n_gd(dev, num_gd);
 820                 if (fst_gd == ERING_WAS_FULL) {
 821                         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 822                         return -EAGAIN;
 823                 }
 824         }
 825         if (num_sd) {
 826                 fst_sd = crypto4xx_get_n_sd(dev, num_sd);
 827                 if (fst_sd == ERING_WAS_FULL) {
 828                         if (num_gd)
 829                                 dev->gdr_head = fst_gd;
 830                         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 831                         return -EAGAIN;
 832                 }
 833         }
 834         pd_entry = crypto4xx_get_pd_from_pdr_nolock(dev);
 835         if (pd_entry == ERING_WAS_FULL) {
 836                 if (num_gd)
 837                         dev->gdr_head = fst_gd;
 838                 if (num_sd)
 839                         dev->sdr_head = fst_sd;
 840                 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 841                 return -EAGAIN;
 842         }
 843         spin_unlock_irqrestore(&dev->core_dev->lock, flags);
 844
 845         pd_uinfo = (struct pd_uinfo *)(dev->pdr_uinfo +
 846                                        sizeof(struct pd_uinfo) * pd_entry);
 847         pd = crypto4xx_get_pdp(dev, &pd_dma, pd_entry);
 848         pd_uinfo->async_req = req;
 849         pd_uinfo->num_gd = num_gd;
 850         pd_uinfo->num_sd = num_sd;
 851
 852         if (iv_len || ctx->is_hash) {
 853                 ivlen = iv_len;
 854                 pd->sa = pd_uinfo->sa_pa;
 855                 sa = (struct dynamic_sa_ctl *) pd_uinfo->sa_va;
 856                 if (ctx->direction == DIR_INBOUND)
 857                         memcpy(sa, ctx->sa_in, ctx->sa_len * 4);
 858                 else
 859                         memcpy(sa, ctx->sa_out, ctx->sa_len * 4);
 860
 861                 memcpy((void *) sa + ctx->offset_to_sr_ptr,
 862                         &pd_uinfo->sr_pa, 4);
 863
 864                 if (iv_len)
 865                         crypto4xx_memcpy_le(pd_uinfo->sr_va, iv, iv_len);
 866         } else {
 867                 if (ctx->direction == DIR_INBOUND) {
 868                         pd->sa = ctx->sa_in_dma_addr;
 869                         sa = (struct dynamic_sa_ctl *) ctx->sa_in;
 870                 } else {
 871                         pd->sa = ctx->sa_out_dma_addr;
 872                         sa = (struct dynamic_sa_ctl *) ctx->sa_out;
 873                 }
 874         }
 875         pd->sa_len = ctx->sa_len;
 876         if (num_gd) {
 877                 /* get first gd we are going to use */
 878                 gd_idx = fst_gd;
 879                 pd_uinfo->first_gd = fst_gd;
 880                 pd_uinfo->num_gd = num_gd;
 881                 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
 882                 pd->src = gd_dma;
 883                 /* enable gather */
 884                 sa->sa_command_0.bf.gather = 1;
 885                 idx = 0;
 886                 src = &src[0];
 887                 /* walk the sg, and setup gather array */
 888                 while (nbytes) {
 889                         sg = &src[idx];
 890                         addr = dma_map_page(dev->core_dev->device, sg_page(sg),
 891                                     sg->offset, sg->length, DMA_TO_DEVICE);
 892                         gd->ptr = addr;
 893                         gd->ctl_len.len = sg->length;
 894                         gd->ctl_len.done = 0;
 895                         gd->ctl_len.ready = 1;
 896                         if (sg->length >= nbytes)
 897                                 break;
 898                         nbytes -= sg->length;
 899                         gd_idx = get_next_gd(gd_idx);
 900                         gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
 901                         idx++;
 902                 }
 903         } else {
 904                 pd->src = (u32)dma_map_page(dev->core_dev->device, sg_page(src),
 905                                 src->offset, src->length, DMA_TO_DEVICE);
 906                 /*
 907                  * Disable gather in sa command
 908                  */
 909                 sa->sa_command_0.bf.gather = 0;
 910                 /*
 911                  * Indicate gather array is not used
 912                  */
 913                 pd_uinfo->first_gd = 0xffffffff;
 914                 pd_uinfo->num_gd = 0;
 915         }
 916         if (ctx->is_hash || sg_is_last(dst)) {
 917                 /*
 918                  * we know application give us dst a whole piece of memory
 919                  * no need to use scatter ring.
 920                  * In case of is_hash, the icv is always at end of src data.
 921                  */
 922                 pd_uinfo->using_sd = 0;
 923                 pd_uinfo->first_sd = 0xffffffff;
 924                 pd_uinfo->num_sd = 0;
 925                 pd_uinfo->dest_va = dst;
 926                 sa->sa_command_0.bf.scatter = 0;
 927                 if (ctx->is_hash)
 928                         pd->dest = virt_to_phys((void *)dst);
 929                 else
 930                         pd->dest = (u32)dma_map_page(dev->core_dev->device,
 931                                         sg_page(dst), dst->offset,
 932                                         dst->length, DMA_TO_DEVICE);
 933         } else {
 934                 struct ce_sd *sd = NULL;
 935                 u32 sd_idx = fst_sd;
 936                 nbytes = datalen;
 937                 sa->sa_command_0.bf.scatter = 1;
 938                 pd_uinfo->using_sd = 1;
 939                 pd_uinfo->dest_va = dst;
 940                 pd_uinfo->first_sd = fst_sd;
 941                 pd_uinfo->num_sd = num_sd;
 942                 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
 943                 pd->dest = sd_dma;
 944                 /* setup scatter descriptor */
 945                 sd->ctl.done = 0;
 946                 sd->ctl.rdy = 1;
 947                 /* sd->ptr should be setup by sd_init routine*/
 948                 idx = 0;
 949                 if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
 950                         nbytes -= PPC4XX_SD_BUFFER_SIZE;
 951                 else
 952                         nbytes = 0;
 953                 while (nbytes) {
 954                         sd_idx = get_next_sd(sd_idx);
 955                         sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
 956                         /* setup scatter descriptor */
 957                         sd->ctl.done = 0;
 958                         sd->ctl.rdy = 1;
 959                         if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
 960                                 nbytes -= PPC4XX_SD_BUFFER_SIZE;
 961                         else
 962                                 /*
 963                                  * SD entry can hold PPC4XX_SD_BUFFER_SIZE,
 964                                  * which is more than nbytes, so done.
 965                                  */
 966                                 nbytes = 0;
 967                 }
 968         }
 969
 970         sa->sa_command_1.bf.hash_crypto_offset = 0;
 971         pd->pd_ctl.w = ctx->pd_ctl;
 972         pd->pd_ctl_len.w = 0x00400000 | (ctx->bypass << 24) | datalen;
 973         pd_uinfo->state = PD_ENTRY_INUSE;
 974         wmb();
 975         /* write any value to push engine to read a pd */
 976         writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
 977         return -EINPROGRESS;
 978 }
 979
 980 /**
 981  * Algorithm Registration Functions
 982  */
 983 static int crypto4xx_alg_init(struct crypto_tfm *tfm)
 984 {
 985         struct crypto_alg *alg = tfm->__crt_alg;
 986         struct crypto4xx_alg *amcc_alg = crypto_alg_to_crypto4xx_alg(alg);
 987         struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
 988
 989         ctx->dev = amcc_alg->dev;
 990         ctx->sa_in = NULL;
 991         ctx->sa_out = NULL;
 992         ctx->sa_in_dma_addr = 0;
 993         ctx->sa_out_dma_addr = 0;
 994         ctx->sa_len = 0;
 995
 996         switch (alg->cra_flags & CRYPTO_ALG_TYPE_MASK) {
 997         default:
 998                 tfm->crt_ablkcipher.reqsize = sizeof(struct crypto4xx_ctx);
 999                 break;
1000         case CRYPTO_ALG_TYPE_AHASH:
1001                 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1002                                          sizeof(struct crypto4xx_ctx));
1003                 break;
1004         }
1005
1006         return 0;
1007 }
1008
1009 static void crypto4xx_alg_exit(struct crypto_tfm *tfm)
1010 {
1011         struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
1012
1013         crypto4xx_free_sa(ctx);
1014         crypto4xx_free_state_record(ctx);
1015 }
1016
1017 int crypto4xx_register_alg(struct crypto4xx_device *sec_dev,
1018                            struct crypto4xx_alg_common *crypto_alg,
1019                            int array_size)
1020 {
1021         struct crypto4xx_alg *alg;
1022         int i;
1023         int rc = 0;
1024
1025         for (i = 0; i < array_size; i++) {
1026                 alg = kzalloc(sizeof(struct crypto4xx_alg), GFP_KERNEL);
1027                 if (!alg)
1028                         return -ENOMEM;
1029
1030                 alg->alg = crypto_alg[i];
1031                 alg->dev = sec_dev;
1032
1033                 switch (alg->alg.type) {
1034                 case CRYPTO_ALG_TYPE_AHASH:
1035                         rc = crypto_register_ahash(&alg->alg.u.hash);
1036                         break;
1037
1038                 default:
1039                         rc = crypto_register_alg(&alg->alg.u.cipher);
1040                         break;
1041                 }
1042
1043                 if (rc)
1044                         kfree(alg);
1045                 else
1046                         list_add_tail(&alg->entry, &sec_dev->alg_list);
1047         }
1048
1049         return 0;
1050 }
1051
1052 static void crypto4xx_unregister_alg(struct crypto4xx_device *sec_dev)
1053 {
1054         struct crypto4xx_alg *alg, *tmp;
1055
1056         list_for_each_entry_safe(alg, tmp, &sec_dev->alg_list, entry) {
1057                 list_del(&alg->entry);
1058                 switch (alg->alg.type) {
1059                 case CRYPTO_ALG_TYPE_AHASH:
1060                         crypto_unregister_ahash(&alg->alg.u.hash);
1061                         break;
1062
1063                 default:
1064                         crypto_unregister_alg(&alg->alg.u.cipher);
1065                 }
1066                 kfree(alg);
1067         }
1068 }
1069
1070 static void crypto4xx_bh_tasklet_cb(unsigned long data)
1071 {
1072         struct device *dev = (struct device *)data;
1073         struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1074         struct pd_uinfo *pd_uinfo;
1075         struct ce_pd *pd;
1076         u32 tail;
1077
1078         while (core_dev->dev->pdr_head != core_dev->dev->pdr_tail) {
1079                 tail = core_dev->dev->pdr_tail;
1080                 pd_uinfo = core_dev->dev->pdr_uinfo +
1081                         sizeof(struct pd_uinfo)*tail;
1082                 pd =  core_dev->dev->pdr + sizeof(struct ce_pd) * tail;
1083                 if ((pd_uinfo->state == PD_ENTRY_INUSE) &&
1084                                    pd->pd_ctl.bf.pe_done &&
1085                                    !pd->pd_ctl.bf.host_ready) {
1086                         pd->pd_ctl.bf.pe_done = 0;
1087                         crypto4xx_pd_done(core_dev->dev, tail);
1088                         crypto4xx_put_pd_to_pdr(core_dev->dev, tail);
1089                         pd_uinfo->state = PD_ENTRY_FREE;
1090                 } else {
1091                         /* if tail not done, break */
1092                         break;
1093                 }
1094         }
1095 }
1096
1097 /**
1098  * Top Half of isr.
1099  */
1100 static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data)
1101 {
1102         struct device *dev = (struct device *)data;
1103         struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1104
1105         if (!core_dev->dev->ce_base)
1106                 return 0;
1107
1108         writel(PPC4XX_INTERRUPT_CLR,
1109                core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
1110         tasklet_schedule(&core_dev->tasklet);
1111
1112         return IRQ_HANDLED;
1113 }
1114
1115 /**
1116  * Supported Crypto Algorithms
1117  */
1118 struct crypto4xx_alg_common crypto4xx_alg[] = {
1119         /* Crypto AES modes */
1120         { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = {
1121                 .cra_name       = "cbc(aes)",
1122                 .cra_driver_name = "cbc-aes-ppc4xx",
1123                 .cra_priority   = CRYPTO4XX_CRYPTO_PRIORITY,
1124                 .cra_flags      = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1125                 .cra_blocksize  = AES_BLOCK_SIZE,
1126                 .cra_ctxsize    = sizeof(struct crypto4xx_ctx),
1127                 .cra_type       = &crypto_ablkcipher_type,
1128                 .cra_init       = crypto4xx_alg_init,
1129                 .cra_exit       = crypto4xx_alg_exit,
1130                 .cra_module     = THIS_MODULE,
1131                 .cra_u          = {
1132                         .ablkcipher = {
1133                                 .min_keysize    = AES_MIN_KEY_SIZE,
1134                                 .max_keysize    = AES_MAX_KEY_SIZE,
1135                                 .ivsize         = AES_IV_SIZE,
1136                                 .setkey         = crypto4xx_setkey_aes_cbc,
1137                                 .encrypt        = crypto4xx_encrypt,
1138                                 .decrypt        = crypto4xx_decrypt,
1139                         }
1140                 }
1141         }},
1142 };
1143
1144 /**
1145  * Module Initialization Routine
1146  */
1147 static int crypto4xx_probe(struct platform_device *ofdev)
1148 {
1149         int rc;
1150         struct resource res;
1151         struct device *dev = &ofdev->dev;
1152         struct crypto4xx_core_device *core_dev;
1153
1154         rc = of_address_to_resource(ofdev->dev.of_node, 0, &res);
1155         if (rc)
1156                 return -ENODEV;
1157
1158         if (of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-crypto")) {
1159                 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1160                        mfdcri(SDR0, PPC460EX_SDR0_SRST) | PPC460EX_CE_RESET);
1161                 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1162                        mfdcri(SDR0, PPC460EX_SDR0_SRST) & ~PPC460EX_CE_RESET);
1163         } else if (of_find_compatible_node(NULL, NULL,
1164                         "amcc,ppc405ex-crypto")) {
1165                 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1166                        mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET);
1167                 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1168                        mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET);
1169         } else if (of_find_compatible_node(NULL, NULL,
1170                         "amcc,ppc460sx-crypto")) {
1171                 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1172                        mfdcri(SDR0, PPC460SX_SDR0_SRST) | PPC460SX_CE_RESET);
1173                 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1174                        mfdcri(SDR0, PPC460SX_SDR0_SRST) & ~PPC460SX_CE_RESET);
1175         } else {
1176                 printk(KERN_ERR "Crypto Function Not supported!\n");
1177                 return -EINVAL;
1178         }
1179
1180         core_dev = kzalloc(sizeof(struct crypto4xx_core_device), GFP_KERNEL);
1181         if (!core_dev)
1182                 return -ENOMEM;
1183
1184         dev_set_drvdata(dev, core_dev);
1185         core_dev->ofdev = ofdev;
1186         core_dev->dev = kzalloc(sizeof(struct crypto4xx_device), GFP_KERNEL);
1187         rc = -ENOMEM;
1188         if (!core_dev->dev)
1189                 goto err_alloc_dev;
1190
1191         core_dev->dev->core_dev = core_dev;
1192         core_dev->device = dev;
1193         spin_lock_init(&core_dev->lock);
1194         INIT_LIST_HEAD(&core_dev->dev->alg_list);
1195         rc = crypto4xx_build_pdr(core_dev->dev);
1196         if (rc)
1197                 goto err_build_pdr;
1198
1199         rc = crypto4xx_build_gdr(core_dev->dev);
1200         if (rc)
1201                 goto err_build_pdr;
1202
1203         rc = crypto4xx_build_sdr(core_dev->dev);
1204         if (rc)
1205                 goto err_build_sdr;
1206
1207         /* Init tasklet for bottom half processing */
1208         tasklet_init(&core_dev->tasklet, crypto4xx_bh_tasklet_cb,
1209                      (unsigned long) dev);
1210
1211         /* Register for Crypto isr, Crypto Engine IRQ */
1212         core_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1213         rc = request_irq(core_dev->irq, crypto4xx_ce_interrupt_handler, 0,
1214                          core_dev->dev->name, dev);
1215         if (rc)
1216                 goto err_request_irq;
1217
1218         core_dev->dev->ce_base = of_iomap(ofdev->dev.of_node, 0);
1219         if (!core_dev->dev->ce_base) {
1220                 dev_err(dev, "failed to of_iomap\n");
1221                 rc = -ENOMEM;
1222                 goto err_iomap;
1223         }
1224
1225         /* need to setup pdr, rdr, gdr and sdr before this */
1226         crypto4xx_hw_init(core_dev->dev);
1227
1228         /* Register security algorithms with Linux CryptoAPI */
1229         rc = crypto4xx_register_alg(core_dev->dev, crypto4xx_alg,
1230                                ARRAY_SIZE(crypto4xx_alg));
1231         if (rc)
1232                 goto err_start_dev;
1233
1234         ppc4xx_trng_probe(core_dev);
1235         return 0;
1236
1237 err_start_dev:
1238         iounmap(core_dev->dev->ce_base);
1239 err_iomap:
1240         free_irq(core_dev->irq, dev);
1241 err_request_irq:
1242         irq_dispose_mapping(core_dev->irq);
1243         tasklet_kill(&core_dev->tasklet);
1244 err_build_sdr:
1245         crypto4xx_destroy_sdr(core_dev->dev);
1246         crypto4xx_destroy_gdr(core_dev->dev);
1247 err_build_pdr:
1248         crypto4xx_destroy_pdr(core_dev->dev);
1249         kfree(core_dev->dev);
1250 err_alloc_dev:
1251         kfree(core_dev);
1252
1253         return rc;
1254 }
1255
1256 static int crypto4xx_remove(struct platform_device *ofdev)
1257 {
1258         struct device *dev = &ofdev->dev;
1259         struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1260
1261         ppc4xx_trng_remove(core_dev);
1262
1263         free_irq(core_dev->irq, dev);
1264         irq_dispose_mapping(core_dev->irq);
1265
1266         tasklet_kill(&core_dev->tasklet);
1267         /* Un-register with Linux CryptoAPI */
1268         crypto4xx_unregister_alg(core_dev->dev);
1269         /* Free all allocated memory */
1270         crypto4xx_stop_all(core_dev);
1271
1272         return 0;
1273 }
1274
1275 static const struct of_device_id crypto4xx_match[] = {
1276         { .compatible      = "amcc,ppc4xx-crypto",},
1277         { },
1278 };
1279 MODULE_DEVICE_TABLE(of, crypto4xx_match);
1280
1281 static struct platform_driver crypto4xx_driver = {
1282         .driver = {
1283                 .name = MODULE_NAME,
1284                 .of_match_table = crypto4xx_match,
1285         },
1286         .probe          = crypto4xx_probe,
1287         .remove         = crypto4xx_remove,
1288 };
1289
1290 module_platform_driver(crypto4xx_driver);
1291
1292 MODULE_LICENSE("GPL");
1293 MODULE_AUTHOR("James Hsiao <jhsiao@amcc.com>");
1294 MODULE_DESCRIPTION("Driver for AMCC PPC4xx crypto accelerator");