drivers/cpufreq/qcom-cpufreq-nvmem.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 /*
   7  * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
   8  * the CPU frequency subset and voltage value of each OPP varies
   9  * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
  10  * defines the voltage and frequency value based on the msm-id in SMEM
  11  * and speedbin blown in the efuse combination.
  12  * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
  13  * to provide the OPP framework with required information.
  14  * This is used to determine the voltage and frequency value for each OPP of
  15  * operating-points-v2 table when it is parsed by the OPP framework.
  16  */
  17
  18 #include <linux/cpu.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/nvmem-consumer.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_domain.h>
  28 #include <linux/pm_opp.h>
  29 #include <linux/slab.h>
  30 #include <linux/soc/qcom/smem.h>
  31
  32 #define MSM_ID_SMEM     137
  33
  34 enum _msm_id {
  35         MSM8996V3 = 0xF6ul,
  36         APQ8096V3 = 0x123ul,
  37         MSM8996SG = 0x131ul,
  38         APQ8096SG = 0x138ul,
  39 };
  40
  41 enum _msm8996_version {
  42         MSM8996_V3,
  43         MSM8996_SG,
  44         NUM_OF_MSM8996_VERSIONS,
  45 };
  46
  47 struct qcom_cpufreq_drv;
  48
  49 struct qcom_cpufreq_match_data {
  50         int (*get_version)(struct device *cpu_dev,
  51                            struct nvmem_cell *speedbin_nvmem,
  52                            char **pvs_name,
  53                            struct qcom_cpufreq_drv *drv);
  54         const char **genpd_names;
  55 };
  56
  57 struct qcom_cpufreq_drv {
  58         struct opp_table **names_opp_tables;
  59         struct opp_table **hw_opp_tables;
  60         struct opp_table **genpd_opp_tables;
  61         u32 versions;
  62         const struct qcom_cpufreq_match_data *data;
  63 };
  64
  65 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
  66
  67 static void get_krait_bin_format_a(struct device *cpu_dev,
  68                                           int *speed, int *pvs, int *pvs_ver,
  69                                           struct nvmem_cell *pvs_nvmem, u8 *buf)
  70 {
  71         u32 pte_efuse;
  72
  73         pte_efuse = *((u32 *)buf);
  74
  75         *speed = pte_efuse & 0xf;
  76         if (*speed == 0xf)
  77                 *speed = (pte_efuse >> 4) & 0xf;
  78
  79         if (*speed == 0xf) {
  80                 *speed = 0;
  81                 dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
  82         } else {
  83                 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
  84         }
  85
  86         *pvs = (pte_efuse >> 10) & 0x7;
  87         if (*pvs == 0x7)
  88                 *pvs = (pte_efuse >> 13) & 0x7;
  89
  90         if (*pvs == 0x7) {
  91                 *pvs = 0;
  92                 dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
  93         } else {
  94                 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
  95         }
  96 }
  97
  98 static void get_krait_bin_format_b(struct device *cpu_dev,
  99                                           int *speed, int *pvs, int *pvs_ver,
 100                                           struct nvmem_cell *pvs_nvmem, u8 *buf)
 101 {
 102         u32 pte_efuse, redundant_sel;
 103
 104         pte_efuse = *((u32 *)buf);
 105         redundant_sel = (pte_efuse >> 24) & 0x7;
 106
 107         *pvs_ver = (pte_efuse >> 4) & 0x3;
 108
 109         switch (redundant_sel) {
 110         case 1:
 111                 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
 112                 *speed = (pte_efuse >> 27) & 0xf;
 113                 break;
 114         case 2:
 115                 *pvs = (pte_efuse >> 27) & 0xf;
 116                 *speed = pte_efuse & 0x7;
 117                 break;
 118         default:
 119                 /* 4 bits of PVS are in efuse register bits 31, 8-6. */
 120                 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
 121                 *speed = pte_efuse & 0x7;
 122         }
 123
 124         /* Check SPEED_BIN_BLOW_STATUS */
 125         if (pte_efuse & BIT(3)) {
 126                 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
 127         } else {
 128                 dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
 129                 *speed = 0;
 130         }
 131
 132         /* Check PVS_BLOW_STATUS */
 133         pte_efuse = *(((u32 *)buf) + 1);
 134         pte_efuse &= BIT(21);
 135         if (pte_efuse) {
 136                 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
 137         } else {
 138                 dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
 139                 *pvs = 0;
 140         }
 141
 142         dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
 143 }
 144
 145 static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
 146 {
 147         size_t len;
 148         u32 *msm_id;
 149         enum _msm8996_version version;
 150
 151         msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len);
 152         if (IS_ERR(msm_id))
 153                 return NUM_OF_MSM8996_VERSIONS;
 154
 155         /* The first 4 bytes are format, next to them is the actual msm-id */
 156         msm_id++;
 157
 158         switch ((enum _msm_id)*msm_id) {
 159         case MSM8996V3:
 160         case APQ8096V3:
 161                 version = MSM8996_V3;
 162                 break;
 163         case MSM8996SG:
 164         case APQ8096SG:
 165                 version = MSM8996_SG;
 166                 break;
 167         default:
 168                 version = NUM_OF_MSM8996_VERSIONS;
 169         }
 170
 171         return version;
 172 }
 173
 174 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
 175                                           struct nvmem_cell *speedbin_nvmem,
 176                                           char **pvs_name,
 177                                           struct qcom_cpufreq_drv *drv)
 178 {
 179         size_t len;
 180         u8 *speedbin;
 181         enum _msm8996_version msm8996_version;
 182         *pvs_name = NULL;
 183
 184         msm8996_version = qcom_cpufreq_get_msm_id();
 185         if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
 186                 dev_err(cpu_dev, "Not Snapdragon 820/821!");
 187                 return -ENODEV;
 188         }
 189
 190         speedbin = nvmem_cell_read(speedbin_nvmem, &len);
 191         if (IS_ERR(speedbin))
 192                 return PTR_ERR(speedbin);
 193
 194         switch (msm8996_version) {
 195         case MSM8996_V3:
 196                 drv->versions = 1 << (unsigned int)(*speedbin);
 197                 break;
 198         case MSM8996_SG:
 199                 drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
 200                 break;
 201         default:
 202                 BUG();
 203                 break;
 204         }
 205
 206         kfree(speedbin);
 207         return 0;
 208 }
 209
 210 static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
 211                                            struct nvmem_cell *speedbin_nvmem,
 212                                            char **pvs_name,
 213                                            struct qcom_cpufreq_drv *drv)
 214 {
 215         int speed = 0, pvs = 0, pvs_ver = 0;
 216         u8 *speedbin;
 217         size_t len;
 218         int ret = 0;
 219
 220         speedbin = nvmem_cell_read(speedbin_nvmem, &len);
 221
 222         if (IS_ERR(speedbin))
 223                 return PTR_ERR(speedbin);
 224
 225         switch (len) {
 226         case 4:
 227                 get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
 228                                        speedbin_nvmem, speedbin);
 229                 break;
 230         case 8:
 231                 get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
 232                                        speedbin_nvmem, speedbin);
 233                 break;
 234         default:
 235                 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
 236                 ret = -ENODEV;
 237                 goto len_error;
 238         }
 239
 240         snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
 241                  speed, pvs, pvs_ver);
 242
 243         drv->versions = (1 << speed);
 244
 245 len_error:
 246         kfree(speedbin);
 247         return ret;
 248 }
 249
 250 static const struct qcom_cpufreq_match_data match_data_kryo = {
 251         .get_version = qcom_cpufreq_kryo_name_version,
 252 };
 253
 254 static const struct qcom_cpufreq_match_data match_data_krait = {
 255         .get_version = qcom_cpufreq_krait_name_version,
 256 };
 257
 258 static const char *qcs404_genpd_names[] = { "cpr", NULL };
 259
 260 static const struct qcom_cpufreq_match_data match_data_qcs404 = {
 261         .genpd_names = qcs404_genpd_names,
 262 };
 263
 264 static int qcom_cpufreq_probe(struct platform_device *pdev)
 265 {
 266         struct qcom_cpufreq_drv *drv;
 267         struct nvmem_cell *speedbin_nvmem;
 268         struct device_node *np;
 269         struct device *cpu_dev;
 270         char pvs_name_buffer[] = "speedXX-pvsXX-vXX";
 271         char *pvs_name = pvs_name_buffer;
 272         unsigned cpu;
 273         const struct of_device_id *match;
 274         int ret;
 275
 276         cpu_dev = get_cpu_device(0);
 277         if (!cpu_dev)
 278                 return -ENODEV;
 279
 280         np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
 281         if (!np)
 282                 return -ENOENT;
 283
 284         ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
 285         if (!ret) {
 286                 of_node_put(np);
 287                 return -ENOENT;
 288         }
 289
 290         drv = kzalloc(sizeof(*drv), GFP_KERNEL);
 291         if (!drv)
 292                 return -ENOMEM;
 293
 294         match = pdev->dev.platform_data;
 295         drv->data = match->data;
 296         if (!drv->data) {
 297                 ret = -ENODEV;
 298                 goto free_drv;
 299         }
 300
 301         if (drv->data->get_version) {
 302                 speedbin_nvmem = of_nvmem_cell_get(np, NULL);
 303                 if (IS_ERR(speedbin_nvmem)) {
 304                         if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER)
 305                                 dev_err(cpu_dev,
 306                                         "Could not get nvmem cell: %ld\n",
 307                                         PTR_ERR(speedbin_nvmem));
 308                         ret = PTR_ERR(speedbin_nvmem);
 309                         goto free_drv;
 310                 }
 311
 312                 ret = drv->data->get_version(cpu_dev,
 313                                                         speedbin_nvmem, &pvs_name, drv);
 314                 if (ret) {
 315                         nvmem_cell_put(speedbin_nvmem);
 316                         goto free_drv;
 317                 }
 318                 nvmem_cell_put(speedbin_nvmem);
 319         }
 320         of_node_put(np);
 321
 322         drv->names_opp_tables = kcalloc(num_possible_cpus(),
 323                                   sizeof(*drv->names_opp_tables),
 324                                   GFP_KERNEL);
 325         if (!drv->names_opp_tables) {
 326                 ret = -ENOMEM;
 327                 goto free_drv;
 328         }
 329         drv->hw_opp_tables = kcalloc(num_possible_cpus(),
 330                                   sizeof(*drv->hw_opp_tables),
 331                                   GFP_KERNEL);
 332         if (!drv->hw_opp_tables) {
 333                 ret = -ENOMEM;
 334                 goto free_opp_names;
 335         }
 336
 337         drv->genpd_opp_tables = kcalloc(num_possible_cpus(),
 338                                         sizeof(*drv->genpd_opp_tables),
 339                                         GFP_KERNEL);
 340         if (!drv->genpd_opp_tables) {
 341                 ret = -ENOMEM;
 342                 goto free_opp;
 343         }
 344
 345         for_each_possible_cpu(cpu) {
 346                 cpu_dev = get_cpu_device(cpu);
 347                 if (NULL == cpu_dev) {
 348                         ret = -ENODEV;
 349                         goto free_genpd_opp;
 350                 }
 351
 352                 if (drv->data->get_version) {
 353
 354                         if (pvs_name) {
 355                                 drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name(
 356                                                                      cpu_dev,
 357                                                                      pvs_name);
 358                                 if (IS_ERR(drv->names_opp_tables[cpu])) {
 359                                         ret = PTR_ERR(drv->names_opp_tables[cpu]);
 360                                         dev_err(cpu_dev, "Failed to add OPP name %s\n",
 361                                                 pvs_name);
 362                                         goto free_opp;
 363                                 }
 364                         }
 365
 366                         drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw(
 367                                                                          cpu_dev, &drv->versions, 1);
 368                         if (IS_ERR(drv->hw_opp_tables[cpu])) {
 369                                 ret = PTR_ERR(drv->hw_opp_tables[cpu]);
 370                                 dev_err(cpu_dev,
 371                                         "Failed to set supported hardware\n");
 372                                 goto free_genpd_opp;
 373                         }
 374                 }
 375
 376                 if (drv->data->genpd_names) {
 377                         drv->genpd_opp_tables[cpu] =
 378                                 dev_pm_opp_attach_genpd(cpu_dev,
 379                                                         drv->data->genpd_names,
 380                                                         NULL);
 381                         if (IS_ERR(drv->genpd_opp_tables[cpu])) {
 382                                 ret = PTR_ERR(drv->genpd_opp_tables[cpu]);
 383                                 if (ret != -EPROBE_DEFER)
 384                                         dev_err(cpu_dev,
 385                                                 "Could not attach to pm_domain: %d\n",
 386                                                 ret);
 387                                 goto free_genpd_opp;
 388                         }
 389                 }
 390         }
 391
 392         cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
 393                                                           NULL, 0);
 394         if (!IS_ERR(cpufreq_dt_pdev)) {
 395                 platform_set_drvdata(pdev, drv);
 396                 return 0;
 397         }
 398
 399         ret = PTR_ERR(cpufreq_dt_pdev);
 400         dev_err(cpu_dev, "Failed to register platform device\n");
 401
 402 free_genpd_opp:
 403         for_each_possible_cpu(cpu) {
 404                 if (IS_ERR_OR_NULL(drv->genpd_opp_tables[cpu]))
 405                         break;
 406                 dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
 407         }
 408         kfree(drv->genpd_opp_tables);
 409 free_opp:
 410         for_each_possible_cpu(cpu) {
 411                 if (IS_ERR_OR_NULL(drv->names_opp_tables[cpu]))
 412                         break;
 413                 dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]);
 414         }
 415         for_each_possible_cpu(cpu) {
 416                 if (IS_ERR_OR_NULL(drv->hw_opp_tables[cpu]))
 417                         break;
 418                 dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
 419         }
 420         kfree(drv->hw_opp_tables);
 421 free_opp_names:
 422         kfree(drv->names_opp_tables);
 423 free_drv:
 424         kfree(drv);
 425
 426         return ret;
 427 }
 428
 429 static int qcom_cpufreq_remove(struct platform_device *pdev)
 430 {
 431         struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
 432         unsigned int cpu;
 433
 434         platform_device_unregister(cpufreq_dt_pdev);
 435
 436         for_each_possible_cpu(cpu) {
 437                 if (drv->names_opp_tables[cpu])
 438                         dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]);
 439                 if (drv->hw_opp_tables[cpu])
 440                         dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
 441                 if (drv->genpd_opp_tables[cpu])
 442                         dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
 443         }
 444
 445         kfree(drv->names_opp_tables);
 446         kfree(drv->hw_opp_tables);
 447         kfree(drv->genpd_opp_tables);
 448         kfree(drv);
 449
 450         return 0;
 451 }
 452
 453 static struct platform_driver qcom_cpufreq_driver = {
 454         .probe = qcom_cpufreq_probe,
 455         .remove = qcom_cpufreq_remove,
 456         .driver = {
 457                 .name = "qcom-cpufreq-nvmem",
 458         },
 459 };
 460
 461 static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
 462         { .compatible = "qcom,apq8096", .data = &match_data_kryo },
 463         { .compatible = "qcom,msm8996", .data = &match_data_kryo },
 464         { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
 465         { .compatible = "qcom,ipq8064", .data = &match_data_krait },
 466         { .compatible = "qcom,apq8064", .data = &match_data_krait },
 467         { .compatible = "qcom,msm8974", .data = &match_data_krait },
 468         { .compatible = "qcom,msm8960", .data = &match_data_krait },
 469         {},
 470 };
 471 MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
 472
 473 /*
 474  * Since the driver depends on smem and nvmem drivers, which may
 475  * return EPROBE_DEFER, all the real activity is done in the probe,
 476  * which may be defered as well. The init here is only registering
 477  * the driver and the platform device.
 478  */
 479 static int __init qcom_cpufreq_init(void)
 480 {
 481         struct device_node *np = of_find_node_by_path("/");
 482         const struct of_device_id *match;
 483         int ret;
 484
 485         if (!np)
 486                 return -ENODEV;
 487
 488         match = of_match_node(qcom_cpufreq_match_list, np);
 489         of_node_put(np);
 490         if (!match)
 491                 return -ENODEV;
 492
 493         ret = platform_driver_register(&qcom_cpufreq_driver);
 494         if (unlikely(ret < 0))
 495                 return ret;
 496
 497         cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
 498                                                      -1, match, sizeof(*match));
 499         ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
 500         if (0 == ret)
 501                 return 0;
 502
 503         platform_driver_unregister(&qcom_cpufreq_driver);
 504         return ret;
 505 }
 506 module_init(qcom_cpufreq_init);
 507
 508 static void __exit qcom_cpufreq_exit(void)
 509 {
 510         platform_device_unregister(cpufreq_pdev);
 511         platform_driver_unregister(&qcom_cpufreq_driver);
 512 }
 513 module_exit(qcom_cpufreq_exit);
 514
 515 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
 516 MODULE_LICENSE("GPL v2");