1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 #include <linux/bitfield.h>
7 #include <linux/cpufreq.h>
8 #include <linux/init.h>
9 #include <linux/interconnect.h>
10 #include <linux/interrupt.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_opp.h>
16 #include <linux/slab.h>
17 #include <linux/spinlock.h>
19 #define LUT_MAX_ENTRIES 40U
20 #define LUT_SRC GENMASK(31, 30)
21 #define LUT_L_VAL GENMASK(7, 0)
22 #define LUT_CORE_COUNT GENMASK(18, 16)
23 #define LUT_VOLT GENMASK(11, 0)
25 #define LUT_TURBO_IND 1
27 #define GT_IRQ_STATUS BIT(2)
29 #define HZ_PER_KHZ 1000
31 struct qcom_cpufreq_soc_data {
42 struct qcom_cpufreq_data {
45 const struct qcom_cpufreq_soc_data *soc_data;
48 * Mutex to synchronize between de-init sequence and re-starting LMh
51 struct mutex throttle_lock;
54 struct delayed_work throttle_work;
55 struct cpufreq_policy *policy;
58 static unsigned long cpu_hw_rate, xo_rate;
59 static bool icc_scaling_enabled;
61 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
62 unsigned long freq_khz)
64 unsigned long freq_hz = freq_khz * 1000;
65 struct dev_pm_opp *opp;
69 dev = get_cpu_device(policy->cpu);
73 opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
77 ret = dev_pm_opp_set_opp(dev, opp);
82 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
83 unsigned long freq_khz,
86 unsigned long freq_hz = freq_khz * 1000;
89 /* Skip voltage update if the opp table is not available */
90 if (!icc_scaling_enabled)
91 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
93 ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
95 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
99 return dev_pm_opp_enable(cpu_dev, freq_hz);
102 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
105 struct qcom_cpufreq_data *data = policy->driver_data;
106 const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
107 unsigned long freq = policy->freq_table[index].frequency;
109 writel_relaxed(index, data->base + soc_data->reg_perf_state);
111 if (icc_scaling_enabled)
112 qcom_cpufreq_set_bw(policy, freq);
117 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
119 struct qcom_cpufreq_data *data;
120 const struct qcom_cpufreq_soc_data *soc_data;
121 struct cpufreq_policy *policy;
124 policy = cpufreq_cpu_get_raw(cpu);
128 data = policy->driver_data;
129 soc_data = data->soc_data;
131 index = readl_relaxed(data->base + soc_data->reg_perf_state);
132 index = min(index, LUT_MAX_ENTRIES - 1);
134 return policy->freq_table[index].frequency;
137 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
138 unsigned int target_freq)
140 struct qcom_cpufreq_data *data = policy->driver_data;
141 const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
144 index = policy->cached_resolved_idx;
145 writel_relaxed(index, data->base + soc_data->reg_perf_state);
147 return policy->freq_table[index].frequency;
150 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
151 struct cpufreq_policy *policy)
153 u32 data, src, lval, i, core_count, prev_freq = 0, freq;
155 struct cpufreq_frequency_table *table;
156 struct dev_pm_opp *opp;
159 struct qcom_cpufreq_data *drv_data = policy->driver_data;
160 const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
162 table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
166 ret = dev_pm_opp_of_add_table(cpu_dev);
168 /* Disable all opps and cross-validate against LUT later */
169 icc_scaling_enabled = true;
170 for (rate = 0; ; rate++) {
171 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
176 dev_pm_opp_disable(cpu_dev, rate);
178 } else if (ret != -ENODEV) {
179 dev_err(cpu_dev, "Invalid opp table in device tree\n");
182 policy->fast_switch_possible = true;
183 icc_scaling_enabled = false;
186 for (i = 0; i < LUT_MAX_ENTRIES; i++) {
187 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
188 i * soc_data->lut_row_size);
189 src = FIELD_GET(LUT_SRC, data);
190 lval = FIELD_GET(LUT_L_VAL, data);
191 core_count = FIELD_GET(LUT_CORE_COUNT, data);
193 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
194 i * soc_data->lut_row_size);
195 volt = FIELD_GET(LUT_VOLT, data) * 1000;
198 freq = xo_rate * lval / 1000;
200 freq = cpu_hw_rate / 1000;
202 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
203 if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
204 table[i].frequency = freq;
205 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
208 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
209 table[i].frequency = CPUFREQ_ENTRY_INVALID;
212 } else if (core_count == LUT_TURBO_IND) {
213 table[i].frequency = CPUFREQ_ENTRY_INVALID;
217 * Two of the same frequencies with the same core counts means
220 if (i > 0 && prev_freq == freq) {
221 struct cpufreq_frequency_table *prev = &table[i - 1];
224 * Only treat the last frequency that might be a boost
225 * as the boost frequency
227 if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
228 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
229 prev->frequency = prev_freq;
230 prev->flags = CPUFREQ_BOOST_FREQ;
232 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
243 table[i].frequency = CPUFREQ_TABLE_END;
244 policy->freq_table = table;
245 dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
250 static void qcom_get_related_cpus(int index, struct cpumask *m)
252 struct device_node *cpu_np;
253 struct of_phandle_args args;
256 for_each_possible_cpu(cpu) {
257 cpu_np = of_cpu_device_node_get(cpu);
261 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
262 "#freq-domain-cells", 0,
268 if (index == args.args[0])
269 cpumask_set_cpu(cpu, m);
273 static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
277 if (data->soc_data->reg_current_vote)
278 lval = readl_relaxed(data->base + data->soc_data->reg_current_vote) & 0x3ff;
280 lval = readl_relaxed(data->base + data->soc_data->reg_domain_state) & 0xff;
282 return lval * xo_rate;
285 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
287 unsigned long max_capacity, capacity, freq_hz, throttled_freq;
288 struct cpufreq_policy *policy = data->policy;
289 int cpu = cpumask_first(policy->related_cpus);
290 struct device *dev = get_cpu_device(cpu);
291 struct dev_pm_opp *opp;
294 * Get the h/w throttled frequency, normalize it using the
295 * registered opp table and use it to calculate thermal pressure.
297 freq_hz = qcom_lmh_get_throttle_freq(data);
299 opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
300 if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
301 dev_pm_opp_find_freq_ceil(dev, &freq_hz);
303 throttled_freq = freq_hz / HZ_PER_KHZ;
305 /* Update thermal pressure */
307 max_capacity = arch_scale_cpu_capacity(cpu);
308 capacity = mult_frac(max_capacity, throttled_freq, policy->cpuinfo.max_freq);
310 /* Don't pass boost capacity to scheduler */
311 if (capacity > max_capacity)
312 capacity = max_capacity;
314 arch_set_thermal_pressure(policy->related_cpus,
315 max_capacity - capacity);
318 * In the unlikely case policy is unregistered do not enable
319 * polling or h/w interrupt
321 mutex_lock(&data->throttle_lock);
322 if (data->cancel_throttle)
326 * If h/w throttled frequency is higher than what cpufreq has requested
327 * for, then stop polling and switch back to interrupt mechanism.
329 if (throttled_freq >= qcom_cpufreq_hw_get(cpu))
330 enable_irq(data->throttle_irq);
332 mod_delayed_work(system_highpri_wq, &data->throttle_work,
333 msecs_to_jiffies(10));
336 mutex_unlock(&data->throttle_lock);
339 static void qcom_lmh_dcvs_poll(struct work_struct *work)
341 struct qcom_cpufreq_data *data;
343 data = container_of(work, struct qcom_cpufreq_data, throttle_work.work);
344 qcom_lmh_dcvs_notify(data);
347 static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data)
349 struct qcom_cpufreq_data *c_data = data;
351 /* Disable interrupt and enable polling */
352 disable_irq_nosync(c_data->throttle_irq);
353 schedule_delayed_work(&c_data->throttle_work, 0);
355 if (c_data->soc_data->reg_intr_clr)
356 writel_relaxed(GT_IRQ_STATUS,
357 c_data->base + c_data->soc_data->reg_intr_clr);
362 static const struct qcom_cpufreq_soc_data qcom_soc_data = {
364 .reg_freq_lut = 0x110,
365 .reg_volt_lut = 0x114,
366 .reg_current_vote = 0x704,
367 .reg_perf_state = 0x920,
371 static const struct qcom_cpufreq_soc_data epss_soc_data = {
373 .reg_domain_state = 0x20,
374 .reg_freq_lut = 0x100,
375 .reg_volt_lut = 0x200,
376 .reg_intr_clr = 0x308,
377 .reg_perf_state = 0x320,
381 static const struct of_device_id qcom_cpufreq_hw_match[] = {
382 { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
383 { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
386 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
388 static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
390 struct qcom_cpufreq_data *data = policy->driver_data;
391 struct platform_device *pdev = cpufreq_get_driver_data();
396 * Look for LMh interrupt. If no interrupt line is specified /
397 * if there is an error, allow cpufreq to be enabled as usual.
399 data->throttle_irq = platform_get_irq(pdev, index);
400 if (data->throttle_irq <= 0)
401 return data->throttle_irq == -EPROBE_DEFER ? -EPROBE_DEFER : 0;
403 data->cancel_throttle = false;
404 data->policy = policy;
406 mutex_init(&data->throttle_lock);
407 INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
409 snprintf(irq_name, sizeof(irq_name), "dcvsh-irq-%u", policy->cpu);
410 ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
411 IRQF_ONESHOT, irq_name, data);
413 dev_err(&pdev->dev, "Error registering %s: %d\n", irq_name, ret);
420 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
422 if (data->throttle_irq <= 0)
425 mutex_lock(&data->throttle_lock);
426 data->cancel_throttle = true;
427 mutex_unlock(&data->throttle_lock);
429 cancel_delayed_work_sync(&data->throttle_work);
430 free_irq(data->throttle_irq, data);
433 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
435 struct platform_device *pdev = cpufreq_get_driver_data();
436 struct device *dev = &pdev->dev;
437 struct of_phandle_args args;
438 struct device_node *cpu_np;
439 struct device *cpu_dev;
440 struct resource *res;
442 struct qcom_cpufreq_data *data;
445 cpu_dev = get_cpu_device(policy->cpu);
447 pr_err("%s: failed to get cpu%d device\n", __func__,
452 cpu_np = of_cpu_device_node_get(policy->cpu);
456 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
457 "#freq-domain-cells", 0, &args);
462 index = args.args[0];
464 res = platform_get_resource(pdev, IORESOURCE_MEM, index);
466 dev_err(dev, "failed to get mem resource %d\n", index);
470 if (!request_mem_region(res->start, resource_size(res), res->name)) {
471 dev_err(dev, "failed to request resource %pR\n", res);
475 base = ioremap(res->start, resource_size(res));
477 dev_err(dev, "failed to map resource %pR\n", res);
482 data = kzalloc(sizeof(*data), GFP_KERNEL);
488 data->soc_data = of_device_get_match_data(&pdev->dev);
492 /* HW should be in enabled state to proceed */
493 if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
494 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
499 qcom_get_related_cpus(index, policy->cpus);
500 if (!cpumask_weight(policy->cpus)) {
501 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
506 policy->driver_data = data;
507 policy->dvfs_possible_from_any_cpu = true;
509 ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
511 dev_err(dev, "Domain-%d failed to read LUT\n", index);
515 ret = dev_pm_opp_get_opp_count(cpu_dev);
517 dev_err(cpu_dev, "Failed to add OPPs\n");
522 if (policy_has_boost_freq(policy)) {
523 ret = cpufreq_enable_boost_support();
525 dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
528 ret = qcom_cpufreq_hw_lmh_init(policy, index);
538 release_mem_region(res->start, resource_size(res));
542 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
544 struct device *cpu_dev = get_cpu_device(policy->cpu);
545 struct qcom_cpufreq_data *data = policy->driver_data;
546 struct resource *res = data->res;
547 void __iomem *base = data->base;
549 dev_pm_opp_remove_all_dynamic(cpu_dev);
550 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
551 qcom_cpufreq_hw_lmh_exit(data);
552 kfree(policy->freq_table);
555 release_mem_region(res->start, resource_size(res));
560 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
561 &cpufreq_freq_attr_scaling_available_freqs,
562 &cpufreq_freq_attr_scaling_boost_freqs,
566 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
567 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
568 CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
569 CPUFREQ_IS_COOLING_DEV,
570 .verify = cpufreq_generic_frequency_table_verify,
571 .target_index = qcom_cpufreq_hw_target_index,
572 .get = qcom_cpufreq_hw_get,
573 .init = qcom_cpufreq_hw_cpu_init,
574 .exit = qcom_cpufreq_hw_cpu_exit,
575 .register_em = cpufreq_register_em_with_opp,
576 .fast_switch = qcom_cpufreq_hw_fast_switch,
577 .name = "qcom-cpufreq-hw",
578 .attr = qcom_cpufreq_hw_attr,
581 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
583 struct device *cpu_dev;
587 clk = clk_get(&pdev->dev, "xo");
591 xo_rate = clk_get_rate(clk);
594 clk = clk_get(&pdev->dev, "alternate");
598 cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
601 cpufreq_qcom_hw_driver.driver_data = pdev;
603 /* Check for optional interconnect paths on CPU0 */
604 cpu_dev = get_cpu_device(0);
606 return -EPROBE_DEFER;
608 ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
612 ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
614 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
616 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
621 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
623 return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
626 static struct platform_driver qcom_cpufreq_hw_driver = {
627 .probe = qcom_cpufreq_hw_driver_probe,
628 .remove = qcom_cpufreq_hw_driver_remove,
630 .name = "qcom-cpufreq-hw",
631 .of_match_table = qcom_cpufreq_hw_match,
635 static int __init qcom_cpufreq_hw_init(void)
637 return platform_driver_register(&qcom_cpufreq_hw_driver);
639 postcore_initcall(qcom_cpufreq_hw_init);
641 static void __exit qcom_cpufreq_hw_exit(void)
643 platform_driver_unregister(&qcom_cpufreq_hw_driver);
645 module_exit(qcom_cpufreq_hw_exit);
647 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
648 MODULE_LICENSE("GPL v2");