1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 #include <linux/bitfield.h>
7 #include <linux/cpufreq.h>
8 #include <linux/init.h>
9 #include <linux/interconnect.h>
10 #include <linux/interrupt.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_opp.h>
16 #include <linux/slab.h>
17 #include <linux/spinlock.h>
19 #define LUT_MAX_ENTRIES 40U
20 #define LUT_SRC GENMASK(31, 30)
21 #define LUT_L_VAL GENMASK(7, 0)
22 #define LUT_CORE_COUNT GENMASK(18, 16)
23 #define LUT_VOLT GENMASK(11, 0)
25 #define LUT_TURBO_IND 1
27 #define GT_IRQ_STATUS BIT(2)
29 #define HZ_PER_KHZ 1000
31 struct qcom_cpufreq_soc_data {
43 struct qcom_cpufreq_data {
46 const struct qcom_cpufreq_soc_data *soc_data;
49 * Mutex to synchronize between de-init sequence and re-starting LMh
52 struct mutex throttle_lock;
56 struct delayed_work throttle_work;
57 struct cpufreq_policy *policy;
62 static unsigned long cpu_hw_rate, xo_rate;
63 static bool icc_scaling_enabled;
65 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
66 unsigned long freq_khz)
68 unsigned long freq_hz = freq_khz * 1000;
69 struct dev_pm_opp *opp;
73 dev = get_cpu_device(policy->cpu);
77 opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
81 ret = dev_pm_opp_set_opp(dev, opp);
86 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
87 unsigned long freq_khz,
90 unsigned long freq_hz = freq_khz * 1000;
93 /* Skip voltage update if the opp table is not available */
94 if (!icc_scaling_enabled)
95 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
97 ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
99 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
103 return dev_pm_opp_enable(cpu_dev, freq_hz);
106 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
109 struct qcom_cpufreq_data *data = policy->driver_data;
110 const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
111 unsigned long freq = policy->freq_table[index].frequency;
114 writel_relaxed(index, data->base + soc_data->reg_perf_state);
116 if (data->per_core_dcvs)
117 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
118 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
120 if (icc_scaling_enabled)
121 qcom_cpufreq_set_bw(policy, freq);
126 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
128 struct qcom_cpufreq_data *data;
129 const struct qcom_cpufreq_soc_data *soc_data;
130 struct cpufreq_policy *policy;
133 policy = cpufreq_cpu_get_raw(cpu);
137 data = policy->driver_data;
138 soc_data = data->soc_data;
140 index = readl_relaxed(data->base + soc_data->reg_perf_state);
141 index = min(index, LUT_MAX_ENTRIES - 1);
143 return policy->freq_table[index].frequency;
146 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
147 unsigned int target_freq)
149 struct qcom_cpufreq_data *data = policy->driver_data;
150 const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
154 index = policy->cached_resolved_idx;
155 writel_relaxed(index, data->base + soc_data->reg_perf_state);
157 if (data->per_core_dcvs)
158 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
159 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
161 return policy->freq_table[index].frequency;
164 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
165 struct cpufreq_policy *policy)
167 u32 data, src, lval, i, core_count, prev_freq = 0, freq;
169 struct cpufreq_frequency_table *table;
170 struct dev_pm_opp *opp;
173 struct qcom_cpufreq_data *drv_data = policy->driver_data;
174 const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
176 table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
180 ret = dev_pm_opp_of_add_table(cpu_dev);
182 /* Disable all opps and cross-validate against LUT later */
183 icc_scaling_enabled = true;
184 for (rate = 0; ; rate++) {
185 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
190 dev_pm_opp_disable(cpu_dev, rate);
192 } else if (ret != -ENODEV) {
193 dev_err(cpu_dev, "Invalid opp table in device tree\n");
196 policy->fast_switch_possible = true;
197 icc_scaling_enabled = false;
200 for (i = 0; i < LUT_MAX_ENTRIES; i++) {
201 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
202 i * soc_data->lut_row_size);
203 src = FIELD_GET(LUT_SRC, data);
204 lval = FIELD_GET(LUT_L_VAL, data);
205 core_count = FIELD_GET(LUT_CORE_COUNT, data);
207 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
208 i * soc_data->lut_row_size);
209 volt = FIELD_GET(LUT_VOLT, data) * 1000;
212 freq = xo_rate * lval / 1000;
214 freq = cpu_hw_rate / 1000;
216 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
217 if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
218 table[i].frequency = freq;
219 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
222 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
223 table[i].frequency = CPUFREQ_ENTRY_INVALID;
226 } else if (core_count == LUT_TURBO_IND) {
227 table[i].frequency = CPUFREQ_ENTRY_INVALID;
231 * Two of the same frequencies with the same core counts means
234 if (i > 0 && prev_freq == freq) {
235 struct cpufreq_frequency_table *prev = &table[i - 1];
238 * Only treat the last frequency that might be a boost
239 * as the boost frequency
241 if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
242 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
243 prev->frequency = prev_freq;
244 prev->flags = CPUFREQ_BOOST_FREQ;
246 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
257 table[i].frequency = CPUFREQ_TABLE_END;
258 policy->freq_table = table;
259 dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
264 static void qcom_get_related_cpus(int index, struct cpumask *m)
266 struct device_node *cpu_np;
267 struct of_phandle_args args;
270 for_each_possible_cpu(cpu) {
271 cpu_np = of_cpu_device_node_get(cpu);
275 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
276 "#freq-domain-cells", 0,
282 if (index == args.args[0])
283 cpumask_set_cpu(cpu, m);
287 static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
291 if (data->soc_data->reg_current_vote)
292 lval = readl_relaxed(data->base + data->soc_data->reg_current_vote) & 0x3ff;
294 lval = readl_relaxed(data->base + data->soc_data->reg_domain_state) & 0xff;
296 return lval * xo_rate;
299 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
301 struct cpufreq_policy *policy = data->policy;
302 int cpu = cpumask_first(policy->related_cpus);
303 struct device *dev = get_cpu_device(cpu);
304 unsigned long freq_hz, throttled_freq;
305 struct dev_pm_opp *opp;
308 * Get the h/w throttled frequency, normalize it using the
309 * registered opp table and use it to calculate thermal pressure.
311 freq_hz = qcom_lmh_get_throttle_freq(data);
313 opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
314 if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
315 opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz);
318 dev_warn(dev, "Can't find the OPP for throttling: %pe!\n", opp);
320 throttled_freq = freq_hz / HZ_PER_KHZ;
322 /* Update thermal pressure (the boost frequencies are accepted) */
323 arch_update_thermal_pressure(policy->related_cpus, throttled_freq);
329 * In the unlikely case policy is unregistered do not enable
330 * polling or h/w interrupt
332 mutex_lock(&data->throttle_lock);
333 if (data->cancel_throttle)
337 * If h/w throttled frequency is higher than what cpufreq has requested
338 * for, then stop polling and switch back to interrupt mechanism.
340 if (throttled_freq >= qcom_cpufreq_hw_get(cpu))
341 enable_irq(data->throttle_irq);
343 mod_delayed_work(system_highpri_wq, &data->throttle_work,
344 msecs_to_jiffies(10));
347 mutex_unlock(&data->throttle_lock);
350 static void qcom_lmh_dcvs_poll(struct work_struct *work)
352 struct qcom_cpufreq_data *data;
354 data = container_of(work, struct qcom_cpufreq_data, throttle_work.work);
355 qcom_lmh_dcvs_notify(data);
358 static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data)
360 struct qcom_cpufreq_data *c_data = data;
362 /* Disable interrupt and enable polling */
363 disable_irq_nosync(c_data->throttle_irq);
364 schedule_delayed_work(&c_data->throttle_work, 0);
366 if (c_data->soc_data->reg_intr_clr)
367 writel_relaxed(GT_IRQ_STATUS,
368 c_data->base + c_data->soc_data->reg_intr_clr);
373 static const struct qcom_cpufreq_soc_data qcom_soc_data = {
375 .reg_dcvs_ctrl = 0xbc,
376 .reg_freq_lut = 0x110,
377 .reg_volt_lut = 0x114,
378 .reg_current_vote = 0x704,
379 .reg_perf_state = 0x920,
383 static const struct qcom_cpufreq_soc_data epss_soc_data = {
385 .reg_domain_state = 0x20,
386 .reg_dcvs_ctrl = 0xb0,
387 .reg_freq_lut = 0x100,
388 .reg_volt_lut = 0x200,
389 .reg_intr_clr = 0x308,
390 .reg_perf_state = 0x320,
394 static const struct of_device_id qcom_cpufreq_hw_match[] = {
395 { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
396 { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
399 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
401 static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
403 struct qcom_cpufreq_data *data = policy->driver_data;
404 struct platform_device *pdev = cpufreq_get_driver_data();
408 * Look for LMh interrupt. If no interrupt line is specified /
409 * if there is an error, allow cpufreq to be enabled as usual.
411 data->throttle_irq = platform_get_irq_optional(pdev, index);
412 if (data->throttle_irq == -ENXIO)
414 if (data->throttle_irq < 0)
415 return data->throttle_irq;
417 data->cancel_throttle = false;
418 data->policy = policy;
420 mutex_init(&data->throttle_lock);
421 INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
423 snprintf(data->irq_name, sizeof(data->irq_name), "dcvsh-irq-%u", policy->cpu);
424 ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
425 IRQF_ONESHOT | IRQF_NO_AUTOEN, data->irq_name, data);
427 dev_err(&pdev->dev, "Error registering %s: %d\n", data->irq_name, ret);
431 ret = irq_set_affinity_hint(data->throttle_irq, policy->cpus);
433 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
434 data->irq_name, data->throttle_irq);
439 static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy)
441 struct qcom_cpufreq_data *data = policy->driver_data;
442 struct platform_device *pdev = cpufreq_get_driver_data();
445 if (data->throttle_irq <= 0)
448 ret = irq_set_affinity_hint(data->throttle_irq, policy->cpus);
450 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
451 data->irq_name, data->throttle_irq);
456 static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy)
458 struct qcom_cpufreq_data *data = policy->driver_data;
460 if (data->throttle_irq <= 0)
463 mutex_lock(&data->throttle_lock);
464 data->cancel_throttle = true;
465 mutex_unlock(&data->throttle_lock);
467 cancel_delayed_work_sync(&data->throttle_work);
468 irq_set_affinity_hint(data->throttle_irq, NULL);
473 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
475 if (data->throttle_irq <= 0)
478 free_irq(data->throttle_irq, data);
481 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
483 struct platform_device *pdev = cpufreq_get_driver_data();
484 struct device *dev = &pdev->dev;
485 struct of_phandle_args args;
486 struct device_node *cpu_np;
487 struct device *cpu_dev;
488 struct resource *res;
490 struct qcom_cpufreq_data *data;
493 cpu_dev = get_cpu_device(policy->cpu);
495 pr_err("%s: failed to get cpu%d device\n", __func__,
500 cpu_np = of_cpu_device_node_get(policy->cpu);
504 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
505 "#freq-domain-cells", 0, &args);
510 index = args.args[0];
512 res = platform_get_resource(pdev, IORESOURCE_MEM, index);
514 dev_err(dev, "failed to get mem resource %d\n", index);
518 if (!request_mem_region(res->start, resource_size(res), res->name)) {
519 dev_err(dev, "failed to request resource %pR\n", res);
523 base = ioremap(res->start, resource_size(res));
525 dev_err(dev, "failed to map resource %pR\n", res);
530 data = kzalloc(sizeof(*data), GFP_KERNEL);
536 data->soc_data = of_device_get_match_data(&pdev->dev);
540 /* HW should be in enabled state to proceed */
541 if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
542 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
547 if (readl_relaxed(base + data->soc_data->reg_dcvs_ctrl) & 0x1)
548 data->per_core_dcvs = true;
550 qcom_get_related_cpus(index, policy->cpus);
551 if (cpumask_empty(policy->cpus)) {
552 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
557 policy->driver_data = data;
558 policy->dvfs_possible_from_any_cpu = true;
560 ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
562 dev_err(dev, "Domain-%d failed to read LUT\n", index);
566 ret = dev_pm_opp_get_opp_count(cpu_dev);
568 dev_err(cpu_dev, "Failed to add OPPs\n");
573 if (policy_has_boost_freq(policy)) {
574 ret = cpufreq_enable_boost_support();
576 dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
579 ret = qcom_cpufreq_hw_lmh_init(policy, index);
589 release_mem_region(res->start, resource_size(res));
593 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
595 struct device *cpu_dev = get_cpu_device(policy->cpu);
596 struct qcom_cpufreq_data *data = policy->driver_data;
597 struct resource *res = data->res;
598 void __iomem *base = data->base;
600 dev_pm_opp_remove_all_dynamic(cpu_dev);
601 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
602 qcom_cpufreq_hw_lmh_exit(data);
603 kfree(policy->freq_table);
606 release_mem_region(res->start, resource_size(res));
611 static void qcom_cpufreq_ready(struct cpufreq_policy *policy)
613 struct qcom_cpufreq_data *data = policy->driver_data;
615 if (data->throttle_irq >= 0)
616 enable_irq(data->throttle_irq);
619 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
620 &cpufreq_freq_attr_scaling_available_freqs,
621 &cpufreq_freq_attr_scaling_boost_freqs,
625 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
626 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
627 CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
628 CPUFREQ_IS_COOLING_DEV,
629 .verify = cpufreq_generic_frequency_table_verify,
630 .target_index = qcom_cpufreq_hw_target_index,
631 .get = qcom_cpufreq_hw_get,
632 .init = qcom_cpufreq_hw_cpu_init,
633 .exit = qcom_cpufreq_hw_cpu_exit,
634 .online = qcom_cpufreq_hw_cpu_online,
635 .offline = qcom_cpufreq_hw_cpu_offline,
636 .register_em = cpufreq_register_em_with_opp,
637 .fast_switch = qcom_cpufreq_hw_fast_switch,
638 .name = "qcom-cpufreq-hw",
639 .attr = qcom_cpufreq_hw_attr,
640 .ready = qcom_cpufreq_ready,
643 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
645 struct device *cpu_dev;
649 clk = clk_get(&pdev->dev, "xo");
653 xo_rate = clk_get_rate(clk);
656 clk = clk_get(&pdev->dev, "alternate");
660 cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
663 cpufreq_qcom_hw_driver.driver_data = pdev;
665 /* Check for optional interconnect paths on CPU0 */
666 cpu_dev = get_cpu_device(0);
668 return -EPROBE_DEFER;
670 ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
674 ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
676 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
678 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
683 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
685 return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
688 static struct platform_driver qcom_cpufreq_hw_driver = {
689 .probe = qcom_cpufreq_hw_driver_probe,
690 .remove = qcom_cpufreq_hw_driver_remove,
692 .name = "qcom-cpufreq-hw",
693 .of_match_table = qcom_cpufreq_hw_match,
697 static int __init qcom_cpufreq_hw_init(void)
699 return platform_driver_register(&qcom_cpufreq_hw_driver);
701 postcore_initcall(qcom_cpufreq_hw_init);
703 static void __exit qcom_cpufreq_hw_exit(void)
705 platform_driver_unregister(&qcom_cpufreq_hw_driver);
707 module_exit(qcom_cpufreq_hw_exit);
709 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
710 MODULE_LICENSE("GPL v2");