drivers/cpufreq/qcom-cpufreq-hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/cpufreq.h>
   8 #include <linux/init.h>
   9 #include <linux/interconnect.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/pm_opp.h>
  16 #include <linux/slab.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/units.h>
  19
  20 #define LUT_MAX_ENTRIES                 40U
  21 #define LUT_SRC                         GENMASK(31, 30)
  22 #define LUT_L_VAL                       GENMASK(7, 0)
  23 #define LUT_CORE_COUNT                  GENMASK(18, 16)
  24 #define LUT_VOLT                        GENMASK(11, 0)
  25 #define CLK_HW_DIV                      2
  26 #define LUT_TURBO_IND                   1
  27
  28 #define GT_IRQ_STATUS                   BIT(2)
  29
  30 struct qcom_cpufreq_soc_data {
  31         u32 reg_enable;
  32         u32 reg_domain_state;
  33         u32 reg_dcvs_ctrl;
  34         u32 reg_freq_lut;
  35         u32 reg_volt_lut;
  36         u32 reg_intr_clr;
  37         u32 reg_current_vote;
  38         u32 reg_perf_state;
  39         u8 lut_row_size;
  40 };
  41
  42 struct qcom_cpufreq_data {
  43         void __iomem *base;
  44         struct resource *res;
  45         const struct qcom_cpufreq_soc_data *soc_data;
  46
  47         /*
  48          * Mutex to synchronize between de-init sequence and re-starting LMh
  49          * polling/interrupts
  50          */
  51         struct mutex throttle_lock;
  52         int throttle_irq;
  53         char irq_name[15];
  54         bool cancel_throttle;
  55         struct delayed_work throttle_work;
  56         struct cpufreq_policy *policy;
  57
  58         bool per_core_dcvs;
  59 };
  60
  61 static unsigned long cpu_hw_rate, xo_rate;
  62 static bool icc_scaling_enabled;
  63
  64 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
  65                                unsigned long freq_khz)
  66 {
  67         unsigned long freq_hz = freq_khz * 1000;
  68         struct dev_pm_opp *opp;
  69         struct device *dev;
  70         int ret;
  71
  72         dev = get_cpu_device(policy->cpu);
  73         if (!dev)
  74                 return -ENODEV;
  75
  76         opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
  77         if (IS_ERR(opp))
  78                 return PTR_ERR(opp);
  79
  80         ret = dev_pm_opp_set_opp(dev, opp);
  81         dev_pm_opp_put(opp);
  82         return ret;
  83 }
  84
  85 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
  86                                    unsigned long freq_khz,
  87                                    unsigned long volt)
  88 {
  89         unsigned long freq_hz = freq_khz * 1000;
  90         int ret;
  91
  92         /* Skip voltage update if the opp table is not available */
  93         if (!icc_scaling_enabled)
  94                 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
  95
  96         ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
  97         if (ret) {
  98                 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
  99                 return ret;
 100         }
 101
 102         return dev_pm_opp_enable(cpu_dev, freq_hz);
 103 }
 104
 105 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
 106                                         unsigned int index)
 107 {
 108         struct qcom_cpufreq_data *data = policy->driver_data;
 109         const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
 110         unsigned long freq = policy->freq_table[index].frequency;
 111         unsigned int i;
 112
 113         writel_relaxed(index, data->base + soc_data->reg_perf_state);
 114
 115         if (data->per_core_dcvs)
 116                 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
 117                         writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
 118
 119         if (icc_scaling_enabled)
 120                 qcom_cpufreq_set_bw(policy, freq);
 121
 122         return 0;
 123 }
 124
 125 static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
 126 {
 127         unsigned int lval;
 128
 129         if (data->soc_data->reg_current_vote)
 130                 lval = readl_relaxed(data->base + data->soc_data->reg_current_vote) & 0x3ff;
 131         else
 132                 lval = readl_relaxed(data->base + data->soc_data->reg_domain_state) & 0xff;
 133
 134         return lval * xo_rate;
 135 }
 136
 137 /* Get the frequency requested by the cpufreq core for the CPU */
 138 static unsigned int qcom_cpufreq_get_freq(unsigned int cpu)
 139 {
 140         struct qcom_cpufreq_data *data;
 141         const struct qcom_cpufreq_soc_data *soc_data;
 142         struct cpufreq_policy *policy;
 143         unsigned int index;
 144
 145         policy = cpufreq_cpu_get_raw(cpu);
 146         if (!policy)
 147                 return 0;
 148
 149         data = policy->driver_data;
 150         soc_data = data->soc_data;
 151
 152         index = readl_relaxed(data->base + soc_data->reg_perf_state);
 153         index = min(index, LUT_MAX_ENTRIES - 1);
 154
 155         return policy->freq_table[index].frequency;
 156 }
 157
 158 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
 159 {
 160         struct qcom_cpufreq_data *data;
 161         struct cpufreq_policy *policy;
 162
 163         policy = cpufreq_cpu_get_raw(cpu);
 164         if (!policy)
 165                 return 0;
 166
 167         data = policy->driver_data;
 168
 169         if (data->throttle_irq >= 0)
 170                 return qcom_lmh_get_throttle_freq(data) / HZ_PER_KHZ;
 171
 172         return qcom_cpufreq_get_freq(cpu);
 173 }
 174
 175 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
 176                                                 unsigned int target_freq)
 177 {
 178         struct qcom_cpufreq_data *data = policy->driver_data;
 179         const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
 180         unsigned int index;
 181         unsigned int i;
 182
 183         index = policy->cached_resolved_idx;
 184         writel_relaxed(index, data->base + soc_data->reg_perf_state);
 185
 186         if (data->per_core_dcvs)
 187                 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
 188                         writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
 189
 190         return policy->freq_table[index].frequency;
 191 }
 192
 193 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
 194                                     struct cpufreq_policy *policy)
 195 {
 196         u32 data, src, lval, i, core_count, prev_freq = 0, freq;
 197         u32 volt;
 198         struct cpufreq_frequency_table  *table;
 199         struct dev_pm_opp *opp;
 200         unsigned long rate;
 201         int ret;
 202         struct qcom_cpufreq_data *drv_data = policy->driver_data;
 203         const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
 204
 205         table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
 206         if (!table)
 207                 return -ENOMEM;
 208
 209         ret = dev_pm_opp_of_add_table(cpu_dev);
 210         if (!ret) {
 211                 /* Disable all opps and cross-validate against LUT later */
 212                 icc_scaling_enabled = true;
 213                 for (rate = 0; ; rate++) {
 214                         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
 215                         if (IS_ERR(opp))
 216                                 break;
 217
 218                         dev_pm_opp_put(opp);
 219                         dev_pm_opp_disable(cpu_dev, rate);
 220                 }
 221         } else if (ret != -ENODEV) {
 222                 dev_err(cpu_dev, "Invalid opp table in device tree\n");
 223                 kfree(table);
 224                 return ret;
 225         } else {
 226                 policy->fast_switch_possible = true;
 227                 icc_scaling_enabled = false;
 228         }
 229
 230         for (i = 0; i < LUT_MAX_ENTRIES; i++) {
 231                 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
 232                                       i * soc_data->lut_row_size);
 233                 src = FIELD_GET(LUT_SRC, data);
 234                 lval = FIELD_GET(LUT_L_VAL, data);
 235                 core_count = FIELD_GET(LUT_CORE_COUNT, data);
 236
 237                 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
 238                                       i * soc_data->lut_row_size);
 239                 volt = FIELD_GET(LUT_VOLT, data) * 1000;
 240
 241                 if (src)
 242                         freq = xo_rate * lval / 1000;
 243                 else
 244                         freq = cpu_hw_rate / 1000;
 245
 246                 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
 247                         if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
 248                                 table[i].frequency = freq;
 249                                 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
 250                                 freq, core_count);
 251                         } else {
 252                                 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
 253                                 table[i].frequency = CPUFREQ_ENTRY_INVALID;
 254                         }
 255
 256                 } else if (core_count == LUT_TURBO_IND) {
 257                         table[i].frequency = CPUFREQ_ENTRY_INVALID;
 258                 }
 259
 260                 /*
 261                  * Two of the same frequencies with the same core counts means
 262                  * end of table
 263                  */
 264                 if (i > 0 && prev_freq == freq) {
 265                         struct cpufreq_frequency_table *prev = &table[i - 1];
 266
 267                         /*
 268                          * Only treat the last frequency that might be a boost
 269                          * as the boost frequency
 270                          */
 271                         if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
 272                                 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
 273                                         prev->frequency = prev_freq;
 274                                         prev->flags = CPUFREQ_BOOST_FREQ;
 275                                 } else {
 276                                         dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
 277                                                  freq);
 278                                 }
 279                         }
 280
 281                         break;
 282                 }
 283
 284                 prev_freq = freq;
 285         }
 286
 287         table[i].frequency = CPUFREQ_TABLE_END;
 288         policy->freq_table = table;
 289         dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
 290
 291         return 0;
 292 }
 293
 294 static void qcom_get_related_cpus(int index, struct cpumask *m)
 295 {
 296         struct device_node *cpu_np;
 297         struct of_phandle_args args;
 298         int cpu, ret;
 299
 300         for_each_possible_cpu(cpu) {
 301                 cpu_np = of_cpu_device_node_get(cpu);
 302                 if (!cpu_np)
 303                         continue;
 304
 305                 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 306                                                  "#freq-domain-cells", 0,
 307                                                  &args);
 308                 of_node_put(cpu_np);
 309                 if (ret < 0)
 310                         continue;
 311
 312                 if (index == args.args[0])
 313                         cpumask_set_cpu(cpu, m);
 314         }
 315 }
 316
 317 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
 318 {
 319         struct cpufreq_policy *policy = data->policy;
 320         int cpu = cpumask_first(policy->related_cpus);
 321         struct device *dev = get_cpu_device(cpu);
 322         unsigned long freq_hz, throttled_freq;
 323         struct dev_pm_opp *opp;
 324
 325         /*
 326          * Get the h/w throttled frequency, normalize it using the
 327          * registered opp table and use it to calculate thermal pressure.
 328          */
 329         freq_hz = qcom_lmh_get_throttle_freq(data);
 330
 331         opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
 332         if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
 333                 opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz);
 334
 335         if (IS_ERR(opp)) {
 336                 dev_warn(dev, "Can't find the OPP for throttling: %pe!\n", opp);
 337         } else {
 338                 dev_pm_opp_put(opp);
 339         }
 340
 341         throttled_freq = freq_hz / HZ_PER_KHZ;
 342
 343         /* Update thermal pressure (the boost frequencies are accepted) */
 344         arch_update_thermal_pressure(policy->related_cpus, throttled_freq);
 345
 346         /*
 347          * In the unlikely case policy is unregistered do not enable
 348          * polling or h/w interrupt
 349          */
 350         mutex_lock(&data->throttle_lock);
 351         if (data->cancel_throttle)
 352                 goto out;
 353
 354         /*
 355          * If h/w throttled frequency is higher than what cpufreq has requested
 356          * for, then stop polling and switch back to interrupt mechanism.
 357          */
 358         if (throttled_freq >= qcom_cpufreq_get_freq(cpu))
 359                 enable_irq(data->throttle_irq);
 360         else
 361                 mod_delayed_work(system_highpri_wq, &data->throttle_work,
 362                                  msecs_to_jiffies(10));
 363
 364 out:
 365         mutex_unlock(&data->throttle_lock);
 366 }
 367
 368 static void qcom_lmh_dcvs_poll(struct work_struct *work)
 369 {
 370         struct qcom_cpufreq_data *data;
 371
 372         data = container_of(work, struct qcom_cpufreq_data, throttle_work.work);
 373         qcom_lmh_dcvs_notify(data);
 374 }
 375
 376 static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data)
 377 {
 378         struct qcom_cpufreq_data *c_data = data;
 379
 380         /* Disable interrupt and enable polling */
 381         disable_irq_nosync(c_data->throttle_irq);
 382         schedule_delayed_work(&c_data->throttle_work, 0);
 383
 384         if (c_data->soc_data->reg_intr_clr)
 385                 writel_relaxed(GT_IRQ_STATUS,
 386                                c_data->base + c_data->soc_data->reg_intr_clr);
 387
 388         return IRQ_HANDLED;
 389 }
 390
 391 static const struct qcom_cpufreq_soc_data qcom_soc_data = {
 392         .reg_enable = 0x0,
 393         .reg_dcvs_ctrl = 0xbc,
 394         .reg_freq_lut = 0x110,
 395         .reg_volt_lut = 0x114,
 396         .reg_current_vote = 0x704,
 397         .reg_perf_state = 0x920,
 398         .lut_row_size = 32,
 399 };
 400
 401 static const struct qcom_cpufreq_soc_data epss_soc_data = {
 402         .reg_enable = 0x0,
 403         .reg_domain_state = 0x20,
 404         .reg_dcvs_ctrl = 0xb0,
 405         .reg_freq_lut = 0x100,
 406         .reg_volt_lut = 0x200,
 407         .reg_intr_clr = 0x308,
 408         .reg_perf_state = 0x320,
 409         .lut_row_size = 4,
 410 };
 411
 412 static const struct of_device_id qcom_cpufreq_hw_match[] = {
 413         { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
 414         { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
 415         {}
 416 };
 417 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
 418
 419 static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
 420 {
 421         struct qcom_cpufreq_data *data = policy->driver_data;
 422         struct platform_device *pdev = cpufreq_get_driver_data();
 423         int ret;
 424
 425         /*
 426          * Look for LMh interrupt. If no interrupt line is specified /
 427          * if there is an error, allow cpufreq to be enabled as usual.
 428          */
 429         data->throttle_irq = platform_get_irq_optional(pdev, index);
 430         if (data->throttle_irq == -ENXIO)
 431                 return 0;
 432         if (data->throttle_irq < 0)
 433                 return data->throttle_irq;
 434
 435         data->cancel_throttle = false;
 436         data->policy = policy;
 437
 438         mutex_init(&data->throttle_lock);
 439         INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
 440
 441         snprintf(data->irq_name, sizeof(data->irq_name), "dcvsh-irq-%u", policy->cpu);
 442         ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
 443                                    IRQF_ONESHOT | IRQF_NO_AUTOEN, data->irq_name, data);
 444         if (ret) {
 445                 dev_err(&pdev->dev, "Error registering %s: %d\n", data->irq_name, ret);
 446                 return 0;
 447         }
 448
 449         ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
 450         if (ret)
 451                 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
 452                         data->irq_name, data->throttle_irq);
 453
 454         return 0;
 455 }
 456
 457 static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy)
 458 {
 459         struct qcom_cpufreq_data *data = policy->driver_data;
 460         struct platform_device *pdev = cpufreq_get_driver_data();
 461         int ret;
 462
 463         if (data->throttle_irq <= 0)
 464                 return 0;
 465
 466         mutex_lock(&data->throttle_lock);
 467         data->cancel_throttle = false;
 468         mutex_unlock(&data->throttle_lock);
 469
 470         ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
 471         if (ret)
 472                 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
 473                         data->irq_name, data->throttle_irq);
 474
 475         return ret;
 476 }
 477
 478 static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy)
 479 {
 480         struct qcom_cpufreq_data *data = policy->driver_data;
 481
 482         if (data->throttle_irq <= 0)
 483                 return 0;
 484
 485         mutex_lock(&data->throttle_lock);
 486         data->cancel_throttle = true;
 487         mutex_unlock(&data->throttle_lock);
 488
 489         cancel_delayed_work_sync(&data->throttle_work);
 490         irq_set_affinity_and_hint(data->throttle_irq, NULL);
 491         disable_irq_nosync(data->throttle_irq);
 492
 493         return 0;
 494 }
 495
 496 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
 497 {
 498         if (data->throttle_irq <= 0)
 499                 return;
 500
 501         free_irq(data->throttle_irq, data);
 502 }
 503
 504 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
 505 {
 506         struct platform_device *pdev = cpufreq_get_driver_data();
 507         struct device *dev = &pdev->dev;
 508         struct of_phandle_args args;
 509         struct device_node *cpu_np;
 510         struct device *cpu_dev;
 511         struct resource *res;
 512         void __iomem *base;
 513         struct qcom_cpufreq_data *data;
 514         int ret, index;
 515
 516         cpu_dev = get_cpu_device(policy->cpu);
 517         if (!cpu_dev) {
 518                 pr_err("%s: failed to get cpu%d device\n", __func__,
 519                        policy->cpu);
 520                 return -ENODEV;
 521         }
 522
 523         cpu_np = of_cpu_device_node_get(policy->cpu);
 524         if (!cpu_np)
 525                 return -EINVAL;
 526
 527         ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 528                                          "#freq-domain-cells", 0, &args);
 529         of_node_put(cpu_np);
 530         if (ret)
 531                 return ret;
 532
 533         index = args.args[0];
 534
 535         res = platform_get_resource(pdev, IORESOURCE_MEM, index);
 536         if (!res) {
 537                 dev_err(dev, "failed to get mem resource %d\n", index);
 538                 return -ENODEV;
 539         }
 540
 541         if (!request_mem_region(res->start, resource_size(res), res->name)) {
 542                 dev_err(dev, "failed to request resource %pR\n", res);
 543                 return -EBUSY;
 544         }
 545
 546         base = ioremap(res->start, resource_size(res));
 547         if (!base) {
 548                 dev_err(dev, "failed to map resource %pR\n", res);
 549                 ret = -ENOMEM;
 550                 goto release_region;
 551         }
 552
 553         data = kzalloc(sizeof(*data), GFP_KERNEL);
 554         if (!data) {
 555                 ret = -ENOMEM;
 556                 goto unmap_base;
 557         }
 558
 559         data->soc_data = of_device_get_match_data(&pdev->dev);
 560         data->base = base;
 561         data->res = res;
 562
 563         /* HW should be in enabled state to proceed */
 564         if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
 565                 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
 566                 ret = -ENODEV;
 567                 goto error;
 568         }
 569
 570         if (readl_relaxed(base + data->soc_data->reg_dcvs_ctrl) & 0x1)
 571                 data->per_core_dcvs = true;
 572
 573         qcom_get_related_cpus(index, policy->cpus);
 574         if (cpumask_empty(policy->cpus)) {
 575                 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
 576                 ret = -ENOENT;
 577                 goto error;
 578         }
 579
 580         policy->driver_data = data;
 581         policy->dvfs_possible_from_any_cpu = true;
 582
 583         ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
 584         if (ret) {
 585                 dev_err(dev, "Domain-%d failed to read LUT\n", index);
 586                 goto error;
 587         }
 588
 589         ret = dev_pm_opp_get_opp_count(cpu_dev);
 590         if (ret <= 0) {
 591                 dev_err(cpu_dev, "Failed to add OPPs\n");
 592                 ret = -ENODEV;
 593                 goto error;
 594         }
 595
 596         if (policy_has_boost_freq(policy)) {
 597                 ret = cpufreq_enable_boost_support();
 598                 if (ret)
 599                         dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
 600         }
 601
 602         ret = qcom_cpufreq_hw_lmh_init(policy, index);
 603         if (ret)
 604                 goto error;
 605
 606         return 0;
 607 error:
 608         kfree(data);
 609 unmap_base:
 610         iounmap(base);
 611 release_region:
 612         release_mem_region(res->start, resource_size(res));
 613         return ret;
 614 }
 615
 616 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
 617 {
 618         struct device *cpu_dev = get_cpu_device(policy->cpu);
 619         struct qcom_cpufreq_data *data = policy->driver_data;
 620         struct resource *res = data->res;
 621         void __iomem *base = data->base;
 622
 623         dev_pm_opp_remove_all_dynamic(cpu_dev);
 624         dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
 625         qcom_cpufreq_hw_lmh_exit(data);
 626         kfree(policy->freq_table);
 627         kfree(data);
 628         iounmap(base);
 629         release_mem_region(res->start, resource_size(res));
 630
 631         return 0;
 632 }
 633
 634 static void qcom_cpufreq_ready(struct cpufreq_policy *policy)
 635 {
 636         struct qcom_cpufreq_data *data = policy->driver_data;
 637
 638         if (data->throttle_irq >= 0)
 639                 enable_irq(data->throttle_irq);
 640 }
 641
 642 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
 643         &cpufreq_freq_attr_scaling_available_freqs,
 644         &cpufreq_freq_attr_scaling_boost_freqs,
 645         NULL
 646 };
 647
 648 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
 649         .flags          = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
 650                           CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
 651                           CPUFREQ_IS_COOLING_DEV,
 652         .verify         = cpufreq_generic_frequency_table_verify,
 653         .target_index   = qcom_cpufreq_hw_target_index,
 654         .get            = qcom_cpufreq_hw_get,
 655         .init           = qcom_cpufreq_hw_cpu_init,
 656         .exit           = qcom_cpufreq_hw_cpu_exit,
 657         .online         = qcom_cpufreq_hw_cpu_online,
 658         .offline        = qcom_cpufreq_hw_cpu_offline,
 659         .register_em    = cpufreq_register_em_with_opp,
 660         .fast_switch    = qcom_cpufreq_hw_fast_switch,
 661         .name           = "qcom-cpufreq-hw",
 662         .attr           = qcom_cpufreq_hw_attr,
 663         .ready          = qcom_cpufreq_ready,
 664 };
 665
 666 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
 667 {
 668         struct device *cpu_dev;
 669         struct clk *clk;
 670         int ret;
 671
 672         clk = clk_get(&pdev->dev, "xo");
 673         if (IS_ERR(clk))
 674                 return PTR_ERR(clk);
 675
 676         xo_rate = clk_get_rate(clk);
 677         clk_put(clk);
 678
 679         clk = clk_get(&pdev->dev, "alternate");
 680         if (IS_ERR(clk))
 681                 return PTR_ERR(clk);
 682
 683         cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
 684         clk_put(clk);
 685
 686         cpufreq_qcom_hw_driver.driver_data = pdev;
 687
 688         /* Check for optional interconnect paths on CPU0 */
 689         cpu_dev = get_cpu_device(0);
 690         if (!cpu_dev)
 691                 return -EPROBE_DEFER;
 692
 693         ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
 694         if (ret)
 695                 return ret;
 696
 697         ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
 698         if (ret)
 699                 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
 700         else
 701                 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
 702
 703         return ret;
 704 }
 705
 706 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
 707 {
 708         return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
 709 }
 710
 711 static struct platform_driver qcom_cpufreq_hw_driver = {
 712         .probe = qcom_cpufreq_hw_driver_probe,
 713         .remove = qcom_cpufreq_hw_driver_remove,
 714         .driver = {
 715                 .name = "qcom-cpufreq-hw",
 716                 .of_match_table = qcom_cpufreq_hw_match,
 717         },
 718 };
 719
 720 static int __init qcom_cpufreq_hw_init(void)
 721 {
 722         return platform_driver_register(&qcom_cpufreq_hw_driver);
 723 }
 724 postcore_initcall(qcom_cpufreq_hw_init);
 725
 726 static void __exit qcom_cpufreq_hw_exit(void)
 727 {
 728         platform_driver_unregister(&qcom_cpufreq_hw_driver);
 729 }
 730 module_exit(qcom_cpufreq_hw_exit);
 731
 732 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
 733 MODULE_LICENSE("GPL v2");