drivers/cpufreq/intel_pstate.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * intel_pstate.c: Native P state management for Intel processors
   4  *
   5  * (C) Copyright 2012 Intel Corporation
   6  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/kernel.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/module.h>
  14 #include <linux/ktime.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/tick.h>
  17 #include <linux/slab.h>
  18 #include <linux/sched/cpufreq.h>
  19 #include <linux/list.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpufreq.h>
  22 #include <linux/sysfs.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/acpi.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/pm_qos.h>
  28 #include <trace/events/power.h>
  29
  30 #include <asm/div64.h>
  31 #include <asm/msr.h>
  32 #include <asm/cpu_device_id.h>
  33 #include <asm/cpufeature.h>
  34 #include <asm/intel-family.h>
  35
  36 #define INTEL_PSTATE_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
  37
  38 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  39 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
  40
  41 #ifdef CONFIG_ACPI
  42 #include <acpi/processor.h>
  43 #include <acpi/cppc_acpi.h>
  44 #endif
  45
  46 #define FRAC_BITS 8
  47 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  48 #define fp_toint(X) ((X) >> FRAC_BITS)
  49
  50 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
  51
  52 #define EXT_BITS 6
  53 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  54 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  55 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  56
  57 static inline int32_t mul_fp(int32_t x, int32_t y)
  58 {
  59         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  60 }
  61
  62 static inline int32_t div_fp(s64 x, s64 y)
  63 {
  64         return div64_s64((int64_t)x << FRAC_BITS, y);
  65 }
  66
  67 static inline int ceiling_fp(int32_t x)
  68 {
  69         int mask, ret;
  70
  71         ret = fp_toint(x);
  72         mask = (1 << FRAC_BITS) - 1;
  73         if (x & mask)
  74                 ret += 1;
  75         return ret;
  76 }
  77
  78 static inline int32_t percent_fp(int percent)
  79 {
  80         return div_fp(percent, 100);
  81 }
  82
  83 static inline u64 mul_ext_fp(u64 x, u64 y)
  84 {
  85         return (x * y) >> EXT_FRAC_BITS;
  86 }
  87
  88 static inline u64 div_ext_fp(u64 x, u64 y)
  89 {
  90         return div64_u64(x << EXT_FRAC_BITS, y);
  91 }
  92
  93 static inline int32_t percent_ext_fp(int percent)
  94 {
  95         return div_ext_fp(percent, 100);
  96 }
  97
  98 /**
  99  * struct sample -      Store performance sample
 100  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
 101  *                      performance during last sample period
 102  * @busy_scaled:        Scaled busy value which is used to calculate next
 103  *                      P state. This can be different than core_avg_perf
 104  *                      to account for cpu idle period
 105  * @aperf:              Difference of actual performance frequency clock count
 106  *                      read from APERF MSR between last and current sample
 107  * @mperf:              Difference of maximum performance frequency clock count
 108  *                      read from MPERF MSR between last and current sample
 109  * @tsc:                Difference of time stamp counter between last and
 110  *                      current sample
 111  * @time:               Current time from scheduler
 112  *
 113  * This structure is used in the cpudata structure to store performance sample
 114  * data for choosing next P State.
 115  */
 116 struct sample {
 117         int32_t core_avg_perf;
 118         int32_t busy_scaled;
 119         u64 aperf;
 120         u64 mperf;
 121         u64 tsc;
 122         u64 time;
 123 };
 124
 125 /**
 126  * struct pstate_data - Store P state data
 127  * @current_pstate:     Current requested P state
 128  * @min_pstate:         Min P state possible for this platform
 129  * @max_pstate:         Max P state possible for this platform
 130  * @max_pstate_physical:This is physical Max P state for a processor
 131  *                      This can be higher than the max_pstate which can
 132  *                      be limited by platform thermal design power limits
 133  * @scaling:            Scaling factor to  convert frequency to cpufreq
 134  *                      frequency units
 135  * @turbo_pstate:       Max Turbo P state possible for this platform
 136  * @max_freq:           @max_pstate frequency in cpufreq units
 137  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 138  *
 139  * Stores the per cpu model P state limits and current P state.
 140  */
 141 struct pstate_data {
 142         int     current_pstate;
 143         int     min_pstate;
 144         int     max_pstate;
 145         int     max_pstate_physical;
 146         int     scaling;
 147         int     turbo_pstate;
 148         unsigned int max_freq;
 149         unsigned int turbo_freq;
 150 };
 151
 152 /**
 153  * struct vid_data -    Stores voltage information data
 154  * @min:                VID data for this platform corresponding to
 155  *                      the lowest P state
 156  * @max:                VID data corresponding to the highest P State.
 157  * @turbo:              VID data for turbo P state
 158  * @ratio:              Ratio of (vid max - vid min) /
 159  *                      (max P state - Min P State)
 160  *
 161  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 162  * This data is used in Atom platforms, where in addition to target P state,
 163  * the voltage data needs to be specified to select next P State.
 164  */
 165 struct vid_data {
 166         int min;
 167         int max;
 168         int turbo;
 169         int32_t ratio;
 170 };
 171
 172 /**
 173  * struct global_params - Global parameters, mostly tunable via sysfs.
 174  * @no_turbo:           Whether or not to use turbo P-states.
 175  * @turbo_disabled:     Whethet or not turbo P-states are available at all,
 176  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
 177  *                      not the maximum reported turbo P-state is different from
 178  *                      the maximum reported non-turbo one.
 179  * @turbo_disabled_mf:  The @turbo_disabled value reflected by cpuinfo.max_freq.
 180  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
 181  *                      P-state capacity.
 182  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
 183  *                      P-state capacity.
 184  */
 185 struct global_params {
 186         bool no_turbo;
 187         bool turbo_disabled;
 188         bool turbo_disabled_mf;
 189         int max_perf_pct;
 190         int min_perf_pct;
 191 };
 192
 193 /**
 194  * struct cpudata -     Per CPU instance data storage
 195  * @cpu:                CPU number for this instance data
 196  * @policy:             CPUFreq policy value
 197  * @update_util:        CPUFreq utility callback information
 198  * @update_util_set:    CPUFreq utility callback is set
 199  * @iowait_boost:       iowait-related boost fraction
 200  * @last_update:        Time of the last update.
 201  * @pstate:             Stores P state limits for this CPU
 202  * @vid:                Stores VID limits for this CPU
 203  * @last_sample_time:   Last Sample time
 204  * @aperf_mperf_shift:  Number of clock cycles after aperf, merf is incremented
 205  *                      This shift is a multiplier to mperf delta to
 206  *                      calculate CPU busy.
 207  * @prev_aperf:         Last APERF value read from APERF MSR
 208  * @prev_mperf:         Last MPERF value read from MPERF MSR
 209  * @prev_tsc:           Last timestamp counter (TSC) value
 210  * @prev_cummulative_iowait: IO Wait time difference from last and
 211  *                      current sample
 212  * @sample:             Storage for storing last Sample data
 213  * @min_perf_ratio:     Minimum capacity in terms of PERF or HWP ratios
 214  * @max_perf_ratio:     Maximum capacity in terms of PERF or HWP ratios
 215  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 216  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 217  * @epp_powersave:      Last saved HWP energy performance preference
 218  *                      (EPP) or energy performance bias (EPB),
 219  *                      when policy switched to performance
 220  * @epp_policy:         Last saved policy used to set EPP/EPB
 221  * @epp_default:        Power on default HWP energy performance
 222  *                      preference/bias
 223  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
 224  *                      operation
 225  * @hwp_req_cached:     Cached value of the last HWP Request MSR
 226  * @hwp_cap_cached:     Cached value of the last HWP Capabilities MSR
 227  * @last_io_update:     Last time when IO wake flag was set
 228  * @sched_flags:        Store scheduler flags for possible cross CPU update
 229  * @hwp_boost_min:      Last HWP boosted min performance
 230  *
 231  * This structure stores per CPU instance data for all CPUs.
 232  */
 233 struct cpudata {
 234         int cpu;
 235
 236         unsigned int policy;
 237         struct update_util_data update_util;
 238         bool   update_util_set;
 239
 240         struct pstate_data pstate;
 241         struct vid_data vid;
 242
 243         u64     last_update;
 244         u64     last_sample_time;
 245         u64     aperf_mperf_shift;
 246         u64     prev_aperf;
 247         u64     prev_mperf;
 248         u64     prev_tsc;
 249         u64     prev_cummulative_iowait;
 250         struct sample sample;
 251         int32_t min_perf_ratio;
 252         int32_t max_perf_ratio;
 253 #ifdef CONFIG_ACPI
 254         struct acpi_processor_performance acpi_perf_data;
 255         bool valid_pss_table;
 256 #endif
 257         unsigned int iowait_boost;
 258         s16 epp_powersave;
 259         s16 epp_policy;
 260         s16 epp_default;
 261         s16 epp_saved;
 262         u64 hwp_req_cached;
 263         u64 hwp_cap_cached;
 264         u64 last_io_update;
 265         unsigned int sched_flags;
 266         u32 hwp_boost_min;
 267 };
 268
 269 static struct cpudata **all_cpu_data;
 270
 271 /**
 272  * struct pstate_funcs - Per CPU model specific callbacks
 273  * @get_max:            Callback to get maximum non turbo effective P state
 274  * @get_max_physical:   Callback to get maximum non turbo physical P state
 275  * @get_min:            Callback to get minimum P state
 276  * @get_turbo:          Callback to get turbo P state
 277  * @get_scaling:        Callback to get frequency scaling factor
 278  * @get_val:            Callback to convert P state to actual MSR write value
 279  * @get_vid:            Callback to get VID data for Atom platforms
 280  *
 281  * Core and Atom CPU models have different way to get P State limits. This
 282  * structure is used to store those callbacks.
 283  */
 284 struct pstate_funcs {
 285         int (*get_max)(void);
 286         int (*get_max_physical)(void);
 287         int (*get_min)(void);
 288         int (*get_turbo)(void);
 289         int (*get_scaling)(void);
 290         int (*get_aperf_mperf_shift)(void);
 291         u64 (*get_val)(struct cpudata*, int pstate);
 292         void (*get_vid)(struct cpudata *);
 293 };
 294
 295 static struct pstate_funcs pstate_funcs __read_mostly;
 296
 297 static int hwp_active __read_mostly;
 298 static int hwp_mode_bdw __read_mostly;
 299 static bool per_cpu_limits __read_mostly;
 300 static bool hwp_boost __read_mostly;
 301
 302 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
 303
 304 #ifdef CONFIG_ACPI
 305 static bool acpi_ppc;
 306 #endif
 307
 308 static struct global_params global;
 309
 310 static DEFINE_MUTEX(intel_pstate_driver_lock);
 311 static DEFINE_MUTEX(intel_pstate_limits_lock);
 312
 313 #ifdef CONFIG_ACPI
 314
 315 static bool intel_pstate_acpi_pm_profile_server(void)
 316 {
 317         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 318             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 319                 return true;
 320
 321         return false;
 322 }
 323
 324 static bool intel_pstate_get_ppc_enable_status(void)
 325 {
 326         if (intel_pstate_acpi_pm_profile_server())
 327                 return true;
 328
 329         return acpi_ppc;
 330 }
 331
 332 #ifdef CONFIG_ACPI_CPPC_LIB
 333
 334 /* The work item is needed to avoid CPU hotplug locking issues */
 335 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 336 {
 337         sched_set_itmt_support();
 338 }
 339
 340 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 341
 342 static void intel_pstate_set_itmt_prio(int cpu)
 343 {
 344         struct cppc_perf_caps cppc_perf;
 345         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 346         int ret;
 347
 348         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 349         if (ret)
 350                 return;
 351
 352         /*
 353          * The priorities can be set regardless of whether or not
 354          * sched_set_itmt_support(true) has been called and it is valid to
 355          * update them at any time after it has been called.
 356          */
 357         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 358
 359         if (max_highest_perf <= min_highest_perf) {
 360                 if (cppc_perf.highest_perf > max_highest_perf)
 361                         max_highest_perf = cppc_perf.highest_perf;
 362
 363                 if (cppc_perf.highest_perf < min_highest_perf)
 364                         min_highest_perf = cppc_perf.highest_perf;
 365
 366                 if (max_highest_perf > min_highest_perf) {
 367                         /*
 368                          * This code can be run during CPU online under the
 369                          * CPU hotplug locks, so sched_set_itmt_support()
 370                          * cannot be called from here.  Queue up a work item
 371                          * to invoke it.
 372                          */
 373                         schedule_work(&sched_itmt_work);
 374                 }
 375         }
 376 }
 377
 378 static int intel_pstate_get_cppc_guranteed(int cpu)
 379 {
 380         struct cppc_perf_caps cppc_perf;
 381         int ret;
 382
 383         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 384         if (ret)
 385                 return ret;
 386
 387         if (cppc_perf.guaranteed_perf)
 388                 return cppc_perf.guaranteed_perf;
 389
 390         return cppc_perf.nominal_perf;
 391 }
 392
 393 #else /* CONFIG_ACPI_CPPC_LIB */
 394 static void intel_pstate_set_itmt_prio(int cpu)
 395 {
 396 }
 397 #endif /* CONFIG_ACPI_CPPC_LIB */
 398
 399 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 400 {
 401         struct cpudata *cpu;
 402         int ret;
 403         int i;
 404
 405         if (hwp_active) {
 406                 intel_pstate_set_itmt_prio(policy->cpu);
 407                 return;
 408         }
 409
 410         if (!intel_pstate_get_ppc_enable_status())
 411                 return;
 412
 413         cpu = all_cpu_data[policy->cpu];
 414
 415         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 416                                                   policy->cpu);
 417         if (ret)
 418                 return;
 419
 420         /*
 421          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 422          * guarantee that the states returned by it map to the states in our
 423          * list directly.
 424          */
 425         if (cpu->acpi_perf_data.control_register.space_id !=
 426                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 427                 goto err;
 428
 429         /*
 430          * If there is only one entry _PSS, simply ignore _PSS and continue as
 431          * usual without taking _PSS into account
 432          */
 433         if (cpu->acpi_perf_data.state_count < 2)
 434                 goto err;
 435
 436         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 437         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 438                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 439                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 440                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 441                          (u32) cpu->acpi_perf_data.states[i].power,
 442                          (u32) cpu->acpi_perf_data.states[i].control);
 443         }
 444
 445         /*
 446          * The _PSS table doesn't contain whole turbo frequency range.
 447          * This just contains +1 MHZ above the max non turbo frequency,
 448          * with control value corresponding to max turbo ratio. But
 449          * when cpufreq set policy is called, it will call with this
 450          * max frequency, which will cause a reduced performance as
 451          * this driver uses real max turbo frequency as the max
 452          * frequency. So correct this frequency in _PSS table to
 453          * correct max turbo frequency based on the turbo state.
 454          * Also need to convert to MHz as _PSS freq is in MHz.
 455          */
 456         if (!global.turbo_disabled)
 457                 cpu->acpi_perf_data.states[0].core_frequency =
 458                                         policy->cpuinfo.max_freq / 1000;
 459         cpu->valid_pss_table = true;
 460         pr_debug("_PPC limits will be enforced\n");
 461
 462         return;
 463
 464  err:
 465         cpu->valid_pss_table = false;
 466         acpi_processor_unregister_performance(policy->cpu);
 467 }
 468
 469 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 470 {
 471         struct cpudata *cpu;
 472
 473         cpu = all_cpu_data[policy->cpu];
 474         if (!cpu->valid_pss_table)
 475                 return;
 476
 477         acpi_processor_unregister_performance(policy->cpu);
 478 }
 479 #else /* CONFIG_ACPI */
 480 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 481 {
 482 }
 483
 484 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 485 {
 486 }
 487
 488 static inline bool intel_pstate_acpi_pm_profile_server(void)
 489 {
 490         return false;
 491 }
 492 #endif /* CONFIG_ACPI */
 493
 494 #ifndef CONFIG_ACPI_CPPC_LIB
 495 static int intel_pstate_get_cppc_guranteed(int cpu)
 496 {
 497         return -ENOTSUPP;
 498 }
 499 #endif /* CONFIG_ACPI_CPPC_LIB */
 500
 501 static inline void update_turbo_state(void)
 502 {
 503         u64 misc_en;
 504         struct cpudata *cpu;
 505
 506         cpu = all_cpu_data[0];
 507         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 508         global.turbo_disabled =
 509                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 510                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 511 }
 512
 513 static int min_perf_pct_min(void)
 514 {
 515         struct cpudata *cpu = all_cpu_data[0];
 516         int turbo_pstate = cpu->pstate.turbo_pstate;
 517
 518         return turbo_pstate ?
 519                 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
 520 }
 521
 522 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 523 {
 524         u64 epb;
 525         int ret;
 526
 527         if (!boot_cpu_has(X86_FEATURE_EPB))
 528                 return -ENXIO;
 529
 530         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 531         if (ret)
 532                 return (s16)ret;
 533
 534         return (s16)(epb & 0x0f);
 535 }
 536
 537 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 538 {
 539         s16 epp;
 540
 541         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 542                 /*
 543                  * When hwp_req_data is 0, means that caller didn't read
 544                  * MSR_HWP_REQUEST, so need to read and get EPP.
 545                  */
 546                 if (!hwp_req_data) {
 547                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 548                                             &hwp_req_data);
 549                         if (epp)
 550                                 return epp;
 551                 }
 552                 epp = (hwp_req_data >> 24) & 0xff;
 553         } else {
 554                 /* When there is no EPP present, HWP uses EPB settings */
 555                 epp = intel_pstate_get_epb(cpu_data);
 556         }
 557
 558         return epp;
 559 }
 560
 561 static int intel_pstate_set_epb(int cpu, s16 pref)
 562 {
 563         u64 epb;
 564         int ret;
 565
 566         if (!boot_cpu_has(X86_FEATURE_EPB))
 567                 return -ENXIO;
 568
 569         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 570         if (ret)
 571                 return ret;
 572
 573         epb = (epb & ~0x0f) | pref;
 574         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 575
 576         return 0;
 577 }
 578
 579 /*
 580  * EPP/EPB display strings corresponding to EPP index in the
 581  * energy_perf_strings[]
 582  *      index           String
 583  *-------------------------------------
 584  *      0               default
 585  *      1               performance
 586  *      2               balance_performance
 587  *      3               balance_power
 588  *      4               power
 589  */
 590 static const char * const energy_perf_strings[] = {
 591         "default",
 592         "performance",
 593         "balance_performance",
 594         "balance_power",
 595         "power",
 596         NULL
 597 };
 598 static const unsigned int epp_values[] = {
 599         HWP_EPP_PERFORMANCE,
 600         HWP_EPP_BALANCE_PERFORMANCE,
 601         HWP_EPP_BALANCE_POWERSAVE,
 602         HWP_EPP_POWERSAVE
 603 };
 604
 605 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
 606 {
 607         s16 epp;
 608         int index = -EINVAL;
 609
 610         epp = intel_pstate_get_epp(cpu_data, 0);
 611         if (epp < 0)
 612                 return epp;
 613
 614         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 615                 if (epp == HWP_EPP_PERFORMANCE)
 616                         return 1;
 617                 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
 618                         return 2;
 619                 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
 620                         return 3;
 621                 else
 622                         return 4;
 623         } else if (boot_cpu_has(X86_FEATURE_EPB)) {
 624                 /*
 625                  * Range:
 626                  *      0x00-0x03       :       Performance
 627                  *      0x04-0x07       :       Balance performance
 628                  *      0x08-0x0B       :       Balance power
 629                  *      0x0C-0x0F       :       Power
 630                  * The EPB is a 4 bit value, but our ranges restrict the
 631                  * value which can be set. Here only using top two bits
 632                  * effectively.
 633                  */
 634                 index = (epp >> 2) + 1;
 635         }
 636
 637         return index;
 638 }
 639
 640 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 641                                               int pref_index)
 642 {
 643         int epp = -EINVAL;
 644         int ret;
 645
 646         if (!pref_index)
 647                 epp = cpu_data->epp_default;
 648
 649         mutex_lock(&intel_pstate_limits_lock);
 650
 651         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 652                 /*
 653                  * Use the cached HWP Request MSR value, because the register
 654                  * itself may be updated by intel_pstate_hwp_boost_up() or
 655                  * intel_pstate_hwp_boost_down() at any time.
 656                  */
 657                 u64 value = READ_ONCE(cpu_data->hwp_req_cached);
 658
 659                 value &= ~GENMASK_ULL(31, 24);
 660
 661                 if (epp == -EINVAL)
 662                         epp = epp_values[pref_index - 1];
 663
 664                 value |= (u64)epp << 24;
 665                 /*
 666                  * The only other updater of hwp_req_cached in the active mode,
 667                  * intel_pstate_hwp_set(), is called under the same lock as this
 668                  * function, so it cannot run in parallel with the update below.
 669                  */
 670                 WRITE_ONCE(cpu_data->hwp_req_cached, value);
 671                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
 672         } else {
 673                 if (epp == -EINVAL)
 674                         epp = (pref_index - 1) << 2;
 675                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 676         }
 677         mutex_unlock(&intel_pstate_limits_lock);
 678
 679         return ret;
 680 }
 681
 682 static ssize_t show_energy_performance_available_preferences(
 683                                 struct cpufreq_policy *policy, char *buf)
 684 {
 685         int i = 0;
 686         int ret = 0;
 687
 688         while (energy_perf_strings[i] != NULL)
 689                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 690
 691         ret += sprintf(&buf[ret], "\n");
 692
 693         return ret;
 694 }
 695
 696 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 697
 698 static ssize_t store_energy_performance_preference(
 699                 struct cpufreq_policy *policy, const char *buf, size_t count)
 700 {
 701         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 702         char str_preference[21];
 703         int ret;
 704
 705         ret = sscanf(buf, "%20s", str_preference);
 706         if (ret != 1)
 707                 return -EINVAL;
 708
 709         ret = match_string(energy_perf_strings, -1, str_preference);
 710         if (ret < 0)
 711                 return ret;
 712
 713         intel_pstate_set_energy_pref_index(cpu_data, ret);
 714         return count;
 715 }
 716
 717 static ssize_t show_energy_performance_preference(
 718                                 struct cpufreq_policy *policy, char *buf)
 719 {
 720         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 721         int preference;
 722
 723         preference = intel_pstate_get_energy_pref_index(cpu_data);
 724         if (preference < 0)
 725                 return preference;
 726
 727         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 728 }
 729
 730 cpufreq_freq_attr_rw(energy_performance_preference);
 731
 732 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
 733 {
 734         struct cpudata *cpu;
 735         u64 cap;
 736         int ratio;
 737
 738         ratio = intel_pstate_get_cppc_guranteed(policy->cpu);
 739         if (ratio <= 0) {
 740                 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
 741                 ratio = HWP_GUARANTEED_PERF(cap);
 742         }
 743
 744         cpu = all_cpu_data[policy->cpu];
 745
 746         return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling);
 747 }
 748
 749 cpufreq_freq_attr_ro(base_frequency);
 750
 751 static struct freq_attr *hwp_cpufreq_attrs[] = {
 752         &energy_performance_preference,
 753         &energy_performance_available_preferences,
 754         &base_frequency,
 755         NULL,
 756 };
 757
 758 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
 759                                      int *current_max)
 760 {
 761         u64 cap;
 762
 763         rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 764         WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
 765         if (global.no_turbo || global.turbo_disabled)
 766                 *current_max = HWP_GUARANTEED_PERF(cap);
 767         else
 768                 *current_max = HWP_HIGHEST_PERF(cap);
 769
 770         *phy_max = HWP_HIGHEST_PERF(cap);
 771 }
 772
 773 static void intel_pstate_hwp_set(unsigned int cpu)
 774 {
 775         struct cpudata *cpu_data = all_cpu_data[cpu];
 776         int max, min;
 777         u64 value;
 778         s16 epp;
 779
 780         max = cpu_data->max_perf_ratio;
 781         min = cpu_data->min_perf_ratio;
 782
 783         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 784                 min = max;
 785
 786         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 787
 788         value &= ~HWP_MIN_PERF(~0L);
 789         value |= HWP_MIN_PERF(min);
 790
 791         value &= ~HWP_MAX_PERF(~0L);
 792         value |= HWP_MAX_PERF(max);
 793
 794         if (cpu_data->epp_policy == cpu_data->policy)
 795                 goto skip_epp;
 796
 797         cpu_data->epp_policy = cpu_data->policy;
 798
 799         if (cpu_data->epp_saved >= 0) {
 800                 epp = cpu_data->epp_saved;
 801                 cpu_data->epp_saved = -EINVAL;
 802                 goto update_epp;
 803         }
 804
 805         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 806                 epp = intel_pstate_get_epp(cpu_data, value);
 807                 cpu_data->epp_powersave = epp;
 808                 /* If EPP read was failed, then don't try to write */
 809                 if (epp < 0)
 810                         goto skip_epp;
 811
 812                 epp = 0;
 813         } else {
 814                 /* skip setting EPP, when saved value is invalid */
 815                 if (cpu_data->epp_powersave < 0)
 816                         goto skip_epp;
 817
 818                 /*
 819                  * No need to restore EPP when it is not zero. This
 820                  * means:
 821                  *  - Policy is not changed
 822                  *  - user has manually changed
 823                  *  - Error reading EPB
 824                  */
 825                 epp = intel_pstate_get_epp(cpu_data, value);
 826                 if (epp)
 827                         goto skip_epp;
 828
 829                 epp = cpu_data->epp_powersave;
 830         }
 831 update_epp:
 832         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 833                 value &= ~GENMASK_ULL(31, 24);
 834                 value |= (u64)epp << 24;
 835         } else {
 836                 intel_pstate_set_epb(cpu, epp);
 837         }
 838 skip_epp:
 839         WRITE_ONCE(cpu_data->hwp_req_cached, value);
 840         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 841 }
 842
 843 static void intel_pstate_hwp_force_min_perf(int cpu)
 844 {
 845         u64 value;
 846         int min_perf;
 847
 848         value = all_cpu_data[cpu]->hwp_req_cached;
 849         value &= ~GENMASK_ULL(31, 0);
 850         min_perf = HWP_LOWEST_PERF(all_cpu_data[cpu]->hwp_cap_cached);
 851
 852         /* Set hwp_max = hwp_min */
 853         value |= HWP_MAX_PERF(min_perf);
 854         value |= HWP_MIN_PERF(min_perf);
 855
 856         /* Set EPP to min */
 857         if (boot_cpu_has(X86_FEATURE_HWP_EPP))
 858                 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
 859
 860         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 861 }
 862
 863 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
 864 {
 865         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 866
 867         if (!hwp_active)
 868                 return 0;
 869
 870         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
 871
 872         return 0;
 873 }
 874
 875 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
 876
 877 static int intel_pstate_resume(struct cpufreq_policy *policy)
 878 {
 879         if (!hwp_active)
 880                 return 0;
 881
 882         mutex_lock(&intel_pstate_limits_lock);
 883
 884         if (policy->cpu == 0)
 885                 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
 886
 887         all_cpu_data[policy->cpu]->epp_policy = 0;
 888         intel_pstate_hwp_set(policy->cpu);
 889
 890         mutex_unlock(&intel_pstate_limits_lock);
 891
 892         return 0;
 893 }
 894
 895 static void intel_pstate_update_policies(void)
 896 {
 897         int cpu;
 898
 899         for_each_possible_cpu(cpu)
 900                 cpufreq_update_policy(cpu);
 901 }
 902
 903 static void intel_pstate_update_max_freq(unsigned int cpu)
 904 {
 905         struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
 906         struct cpudata *cpudata;
 907
 908         if (!policy)
 909                 return;
 910
 911         cpudata = all_cpu_data[cpu];
 912         policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
 913                         cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
 914
 915         refresh_frequency_limits(policy);
 916
 917         cpufreq_cpu_release(policy);
 918 }
 919
 920 static void intel_pstate_update_limits(unsigned int cpu)
 921 {
 922         mutex_lock(&intel_pstate_driver_lock);
 923
 924         update_turbo_state();
 925         /*
 926          * If turbo has been turned on or off globally, policy limits for
 927          * all CPUs need to be updated to reflect that.
 928          */
 929         if (global.turbo_disabled_mf != global.turbo_disabled) {
 930                 global.turbo_disabled_mf = global.turbo_disabled;
 931                 for_each_possible_cpu(cpu)
 932                         intel_pstate_update_max_freq(cpu);
 933         } else {
 934                 cpufreq_update_policy(cpu);
 935         }
 936
 937         mutex_unlock(&intel_pstate_driver_lock);
 938 }
 939
 940 /************************** sysfs begin ************************/
 941 #define show_one(file_name, object)                                     \
 942         static ssize_t show_##file_name                                 \
 943         (struct kobject *kobj, struct kobj_attribute *attr, char *buf)  \
 944         {                                                               \
 945                 return sprintf(buf, "%u\n", global.object);             \
 946         }
 947
 948 static ssize_t intel_pstate_show_status(char *buf);
 949 static int intel_pstate_update_status(const char *buf, size_t size);
 950
 951 static ssize_t show_status(struct kobject *kobj,
 952                            struct kobj_attribute *attr, char *buf)
 953 {
 954         ssize_t ret;
 955
 956         mutex_lock(&intel_pstate_driver_lock);
 957         ret = intel_pstate_show_status(buf);
 958         mutex_unlock(&intel_pstate_driver_lock);
 959
 960         return ret;
 961 }
 962
 963 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
 964                             const char *buf, size_t count)
 965 {
 966         char *p = memchr(buf, '\n', count);
 967         int ret;
 968
 969         mutex_lock(&intel_pstate_driver_lock);
 970         ret = intel_pstate_update_status(buf, p ? p - buf : count);
 971         mutex_unlock(&intel_pstate_driver_lock);
 972
 973         return ret < 0 ? ret : count;
 974 }
 975
 976 static ssize_t show_turbo_pct(struct kobject *kobj,
 977                                 struct kobj_attribute *attr, char *buf)
 978 {
 979         struct cpudata *cpu;
 980         int total, no_turbo, turbo_pct;
 981         uint32_t turbo_fp;
 982
 983         mutex_lock(&intel_pstate_driver_lock);
 984
 985         if (!intel_pstate_driver) {
 986                 mutex_unlock(&intel_pstate_driver_lock);
 987                 return -EAGAIN;
 988         }
 989
 990         cpu = all_cpu_data[0];
 991
 992         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 993         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
 994         turbo_fp = div_fp(no_turbo, total);
 995         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
 996
 997         mutex_unlock(&intel_pstate_driver_lock);
 998
 999         return sprintf(buf, "%u\n", turbo_pct);
1000 }
1001
1002 static ssize_t show_num_pstates(struct kobject *kobj,
1003                                 struct kobj_attribute *attr, char *buf)
1004 {
1005         struct cpudata *cpu;
1006         int total;
1007
1008         mutex_lock(&intel_pstate_driver_lock);
1009
1010         if (!intel_pstate_driver) {
1011                 mutex_unlock(&intel_pstate_driver_lock);
1012                 return -EAGAIN;
1013         }
1014
1015         cpu = all_cpu_data[0];
1016         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1017
1018         mutex_unlock(&intel_pstate_driver_lock);
1019
1020         return sprintf(buf, "%u\n", total);
1021 }
1022
1023 static ssize_t show_no_turbo(struct kobject *kobj,
1024                              struct kobj_attribute *attr, char *buf)
1025 {
1026         ssize_t ret;
1027
1028         mutex_lock(&intel_pstate_driver_lock);
1029
1030         if (!intel_pstate_driver) {
1031                 mutex_unlock(&intel_pstate_driver_lock);
1032                 return -EAGAIN;
1033         }
1034
1035         update_turbo_state();
1036         if (global.turbo_disabled)
1037                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1038         else
1039                 ret = sprintf(buf, "%u\n", global.no_turbo);
1040
1041         mutex_unlock(&intel_pstate_driver_lock);
1042
1043         return ret;
1044 }
1045
1046 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1047                               const char *buf, size_t count)
1048 {
1049         unsigned int input;
1050         int ret;
1051
1052         ret = sscanf(buf, "%u", &input);
1053         if (ret != 1)
1054                 return -EINVAL;
1055
1056         mutex_lock(&intel_pstate_driver_lock);
1057
1058         if (!intel_pstate_driver) {
1059                 mutex_unlock(&intel_pstate_driver_lock);
1060                 return -EAGAIN;
1061         }
1062
1063         mutex_lock(&intel_pstate_limits_lock);
1064
1065         update_turbo_state();
1066         if (global.turbo_disabled) {
1067                 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1068                 mutex_unlock(&intel_pstate_limits_lock);
1069                 mutex_unlock(&intel_pstate_driver_lock);
1070                 return -EPERM;
1071         }
1072
1073         global.no_turbo = clamp_t(int, input, 0, 1);
1074
1075         if (global.no_turbo) {
1076                 struct cpudata *cpu = all_cpu_data[0];
1077                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1078
1079                 /* Squash the global minimum into the permitted range. */
1080                 if (global.min_perf_pct > pct)
1081                         global.min_perf_pct = pct;
1082         }
1083
1084         mutex_unlock(&intel_pstate_limits_lock);
1085
1086         intel_pstate_update_policies();
1087
1088         mutex_unlock(&intel_pstate_driver_lock);
1089
1090         return count;
1091 }
1092
1093 static struct cpufreq_driver intel_pstate;
1094
1095 static void update_qos_request(enum freq_qos_req_type type)
1096 {
1097         int max_state, turbo_max, freq, i, perf_pct;
1098         struct freq_qos_request *req;
1099         struct cpufreq_policy *policy;
1100
1101         for_each_possible_cpu(i) {
1102                 struct cpudata *cpu = all_cpu_data[i];
1103
1104                 policy = cpufreq_cpu_get(i);
1105                 if (!policy)
1106                         continue;
1107
1108                 req = policy->driver_data;
1109                 cpufreq_cpu_put(policy);
1110
1111                 if (!req)
1112                         continue;
1113
1114                 if (hwp_active)
1115                         intel_pstate_get_hwp_max(i, &turbo_max, &max_state);
1116                 else
1117                         turbo_max = cpu->pstate.turbo_pstate;
1118
1119                 if (type == FREQ_QOS_MIN) {
1120                         perf_pct = global.min_perf_pct;
1121                 } else {
1122                         req++;
1123                         perf_pct = global.max_perf_pct;
1124                 }
1125
1126                 freq = DIV_ROUND_UP(turbo_max * perf_pct, 100);
1127                 freq *= cpu->pstate.scaling;
1128
1129                 if (freq_qos_update_request(req, freq) < 0)
1130                         pr_warn("Failed to update freq constraint: CPU%d\n", i);
1131         }
1132 }
1133
1134 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1135                                   const char *buf, size_t count)
1136 {
1137         unsigned int input;
1138         int ret;
1139
1140         ret = sscanf(buf, "%u", &input);
1141         if (ret != 1)
1142                 return -EINVAL;
1143
1144         mutex_lock(&intel_pstate_driver_lock);
1145
1146         if (!intel_pstate_driver) {
1147                 mutex_unlock(&intel_pstate_driver_lock);
1148                 return -EAGAIN;
1149         }
1150
1151         mutex_lock(&intel_pstate_limits_lock);
1152
1153         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1154
1155         mutex_unlock(&intel_pstate_limits_lock);
1156
1157         if (intel_pstate_driver == &intel_pstate)
1158                 intel_pstate_update_policies();
1159         else
1160                 update_qos_request(FREQ_QOS_MAX);
1161
1162         mutex_unlock(&intel_pstate_driver_lock);
1163
1164         return count;
1165 }
1166
1167 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1168                                   const char *buf, size_t count)
1169 {
1170         unsigned int input;
1171         int ret;
1172
1173         ret = sscanf(buf, "%u", &input);
1174         if (ret != 1)
1175                 return -EINVAL;
1176
1177         mutex_lock(&intel_pstate_driver_lock);
1178
1179         if (!intel_pstate_driver) {
1180                 mutex_unlock(&intel_pstate_driver_lock);
1181                 return -EAGAIN;
1182         }
1183
1184         mutex_lock(&intel_pstate_limits_lock);
1185
1186         global.min_perf_pct = clamp_t(int, input,
1187                                       min_perf_pct_min(), global.max_perf_pct);
1188
1189         mutex_unlock(&intel_pstate_limits_lock);
1190
1191         if (intel_pstate_driver == &intel_pstate)
1192                 intel_pstate_update_policies();
1193         else
1194                 update_qos_request(FREQ_QOS_MIN);
1195
1196         mutex_unlock(&intel_pstate_driver_lock);
1197
1198         return count;
1199 }
1200
1201 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1202                                 struct kobj_attribute *attr, char *buf)
1203 {
1204         return sprintf(buf, "%u\n", hwp_boost);
1205 }
1206
1207 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1208                                        struct kobj_attribute *b,
1209                                        const char *buf, size_t count)
1210 {
1211         unsigned int input;
1212         int ret;
1213
1214         ret = kstrtouint(buf, 10, &input);
1215         if (ret)
1216                 return ret;
1217
1218         mutex_lock(&intel_pstate_driver_lock);
1219         hwp_boost = !!input;
1220         intel_pstate_update_policies();
1221         mutex_unlock(&intel_pstate_driver_lock);
1222
1223         return count;
1224 }
1225
1226 show_one(max_perf_pct, max_perf_pct);
1227 show_one(min_perf_pct, min_perf_pct);
1228
1229 define_one_global_rw(status);
1230 define_one_global_rw(no_turbo);
1231 define_one_global_rw(max_perf_pct);
1232 define_one_global_rw(min_perf_pct);
1233 define_one_global_ro(turbo_pct);
1234 define_one_global_ro(num_pstates);
1235 define_one_global_rw(hwp_dynamic_boost);
1236
1237 static struct attribute *intel_pstate_attributes[] = {
1238         &status.attr,
1239         &no_turbo.attr,
1240         &turbo_pct.attr,
1241         &num_pstates.attr,
1242         NULL
1243 };
1244
1245 static const struct attribute_group intel_pstate_attr_group = {
1246         .attrs = intel_pstate_attributes,
1247 };
1248
1249 static void __init intel_pstate_sysfs_expose_params(void)
1250 {
1251         struct kobject *intel_pstate_kobject;
1252         int rc;
1253
1254         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1255                                                 &cpu_subsys.dev_root->kobj);
1256         if (WARN_ON(!intel_pstate_kobject))
1257                 return;
1258
1259         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1260         if (WARN_ON(rc))
1261                 return;
1262
1263         /*
1264          * If per cpu limits are enforced there are no global limits, so
1265          * return without creating max/min_perf_pct attributes
1266          */
1267         if (per_cpu_limits)
1268                 return;
1269
1270         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1271         WARN_ON(rc);
1272
1273         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1274         WARN_ON(rc);
1275
1276         if (hwp_active) {
1277                 rc = sysfs_create_file(intel_pstate_kobject,
1278                                        &hwp_dynamic_boost.attr);
1279                 WARN_ON(rc);
1280         }
1281 }
1282 /************************** sysfs end ************************/
1283
1284 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1285 {
1286         /* First disable HWP notification interrupt as we don't process them */
1287         if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1288                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1289
1290         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1291         cpudata->epp_policy = 0;
1292         if (cpudata->epp_default == -EINVAL)
1293                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1294 }
1295
1296 #define MSR_IA32_POWER_CTL_BIT_EE       19
1297
1298 /* Disable energy efficiency optimization */
1299 static void intel_pstate_disable_ee(int cpu)
1300 {
1301         u64 power_ctl;
1302         int ret;
1303
1304         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1305         if (ret)
1306                 return;
1307
1308         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1309                 pr_info("Disabling energy efficiency optimization\n");
1310                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1311                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1312         }
1313 }
1314
1315 static int atom_get_min_pstate(void)
1316 {
1317         u64 value;
1318
1319         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1320         return (value >> 8) & 0x7F;
1321 }
1322
1323 static int atom_get_max_pstate(void)
1324 {
1325         u64 value;
1326
1327         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1328         return (value >> 16) & 0x7F;
1329 }
1330
1331 static int atom_get_turbo_pstate(void)
1332 {
1333         u64 value;
1334
1335         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1336         return value & 0x7F;
1337 }
1338
1339 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1340 {
1341         u64 val;
1342         int32_t vid_fp;
1343         u32 vid;
1344
1345         val = (u64)pstate << 8;
1346         if (global.no_turbo && !global.turbo_disabled)
1347                 val |= (u64)1 << 32;
1348
1349         vid_fp = cpudata->vid.min + mul_fp(
1350                 int_tofp(pstate - cpudata->pstate.min_pstate),
1351                 cpudata->vid.ratio);
1352
1353         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1354         vid = ceiling_fp(vid_fp);
1355
1356         if (pstate > cpudata->pstate.max_pstate)
1357                 vid = cpudata->vid.turbo;
1358
1359         return val | vid;
1360 }
1361
1362 static int silvermont_get_scaling(void)
1363 {
1364         u64 value;
1365         int i;
1366         /* Defined in Table 35-6 from SDM (Sept 2015) */
1367         static int silvermont_freq_table[] = {
1368                 83300, 100000, 133300, 116700, 80000};
1369
1370         rdmsrl(MSR_FSB_FREQ, value);
1371         i = value & 0x7;
1372         WARN_ON(i > 4);
1373
1374         return silvermont_freq_table[i];
1375 }
1376
1377 static int airmont_get_scaling(void)
1378 {
1379         u64 value;
1380         int i;
1381         /* Defined in Table 35-10 from SDM (Sept 2015) */
1382         static int airmont_freq_table[] = {
1383                 83300, 100000, 133300, 116700, 80000,
1384                 93300, 90000, 88900, 87500};
1385
1386         rdmsrl(MSR_FSB_FREQ, value);
1387         i = value & 0xF;
1388         WARN_ON(i > 8);
1389
1390         return airmont_freq_table[i];
1391 }
1392
1393 static void atom_get_vid(struct cpudata *cpudata)
1394 {
1395         u64 value;
1396
1397         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1398         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1399         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1400         cpudata->vid.ratio = div_fp(
1401                 cpudata->vid.max - cpudata->vid.min,
1402                 int_tofp(cpudata->pstate.max_pstate -
1403                         cpudata->pstate.min_pstate));
1404
1405         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1406         cpudata->vid.turbo = value & 0x7f;
1407 }
1408
1409 static int core_get_min_pstate(void)
1410 {
1411         u64 value;
1412
1413         rdmsrl(MSR_PLATFORM_INFO, value);
1414         return (value >> 40) & 0xFF;
1415 }
1416
1417 static int core_get_max_pstate_physical(void)
1418 {
1419         u64 value;
1420
1421         rdmsrl(MSR_PLATFORM_INFO, value);
1422         return (value >> 8) & 0xFF;
1423 }
1424
1425 static int core_get_tdp_ratio(u64 plat_info)
1426 {
1427         /* Check how many TDP levels present */
1428         if (plat_info & 0x600000000) {
1429                 u64 tdp_ctrl;
1430                 u64 tdp_ratio;
1431                 int tdp_msr;
1432                 int err;
1433
1434                 /* Get the TDP level (0, 1, 2) to get ratios */
1435                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1436                 if (err)
1437                         return err;
1438
1439                 /* TDP MSR are continuous starting at 0x648 */
1440                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1441                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1442                 if (err)
1443                         return err;
1444
1445                 /* For level 1 and 2, bits[23:16] contain the ratio */
1446                 if (tdp_ctrl & 0x03)
1447                         tdp_ratio >>= 16;
1448
1449                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1450                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1451
1452                 return (int)tdp_ratio;
1453         }
1454
1455         return -ENXIO;
1456 }
1457
1458 static int core_get_max_pstate(void)
1459 {
1460         u64 tar;
1461         u64 plat_info;
1462         int max_pstate;
1463         int tdp_ratio;
1464         int err;
1465
1466         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1467         max_pstate = (plat_info >> 8) & 0xFF;
1468
1469         tdp_ratio = core_get_tdp_ratio(plat_info);
1470         if (tdp_ratio <= 0)
1471                 return max_pstate;
1472
1473         if (hwp_active) {
1474                 /* Turbo activation ratio is not used on HWP platforms */
1475                 return tdp_ratio;
1476         }
1477
1478         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1479         if (!err) {
1480                 int tar_levels;
1481
1482                 /* Do some sanity checking for safety */
1483                 tar_levels = tar & 0xff;
1484                 if (tdp_ratio - 1 == tar_levels) {
1485                         max_pstate = tar_levels;
1486                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1487                 }
1488         }
1489
1490         return max_pstate;
1491 }
1492
1493 static int core_get_turbo_pstate(void)
1494 {
1495         u64 value;
1496         int nont, ret;
1497
1498         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1499         nont = core_get_max_pstate();
1500         ret = (value) & 255;
1501         if (ret <= nont)
1502                 ret = nont;
1503         return ret;
1504 }
1505
1506 static inline int core_get_scaling(void)
1507 {
1508         return 100000;
1509 }
1510
1511 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1512 {
1513         u64 val;
1514
1515         val = (u64)pstate << 8;
1516         if (global.no_turbo && !global.turbo_disabled)
1517                 val |= (u64)1 << 32;
1518
1519         return val;
1520 }
1521
1522 static int knl_get_aperf_mperf_shift(void)
1523 {
1524         return 10;
1525 }
1526
1527 static int knl_get_turbo_pstate(void)
1528 {
1529         u64 value;
1530         int nont, ret;
1531
1532         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1533         nont = core_get_max_pstate();
1534         ret = (((value) >> 8) & 0xFF);
1535         if (ret <= nont)
1536                 ret = nont;
1537         return ret;
1538 }
1539
1540 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1541 {
1542         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1543         cpu->pstate.current_pstate = pstate;
1544         /*
1545          * Generally, there is no guarantee that this code will always run on
1546          * the CPU being updated, so force the register update to run on the
1547          * right CPU.
1548          */
1549         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1550                       pstate_funcs.get_val(cpu, pstate));
1551 }
1552
1553 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1554 {
1555         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1556 }
1557
1558 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1559 {
1560         int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1561
1562         update_turbo_state();
1563         intel_pstate_set_pstate(cpu, pstate);
1564 }
1565
1566 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1567 {
1568         cpu->pstate.min_pstate = pstate_funcs.get_min();
1569         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1570         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1571         cpu->pstate.scaling = pstate_funcs.get_scaling();
1572
1573         if (hwp_active && !hwp_mode_bdw) {
1574                 unsigned int phy_max, current_max;
1575
1576                 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, &current_max);
1577                 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1578                 cpu->pstate.turbo_pstate = phy_max;
1579                 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(READ_ONCE(cpu->hwp_cap_cached));
1580         } else {
1581                 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1582                 cpu->pstate.max_pstate = pstate_funcs.get_max();
1583         }
1584         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1585
1586         if (pstate_funcs.get_aperf_mperf_shift)
1587                 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1588
1589         if (pstate_funcs.get_vid)
1590                 pstate_funcs.get_vid(cpu);
1591
1592         intel_pstate_set_min_pstate(cpu);
1593 }
1594
1595 /*
1596  * Long hold time will keep high perf limits for long time,
1597  * which negatively impacts perf/watt for some workloads,
1598  * like specpower. 3ms is based on experiements on some
1599  * workoads.
1600  */
1601 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1602
1603 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1604 {
1605         u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1606         u32 max_limit = (hwp_req & 0xff00) >> 8;
1607         u32 min_limit = (hwp_req & 0xff);
1608         u32 boost_level1;
1609
1610         /*
1611          * Cases to consider (User changes via sysfs or boot time):
1612          * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1613          *      No boost, return.
1614          * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1615          *     Should result in one level boost only for P0.
1616          * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1617          *     Should result in two level boost:
1618          *         (min + p1)/2 and P1.
1619          * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1620          *     Should result in three level boost:
1621          *        (min + p1)/2, P1 and P0.
1622          */
1623
1624         /* If max and min are equal or already at max, nothing to boost */
1625         if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1626                 return;
1627
1628         if (!cpu->hwp_boost_min)
1629                 cpu->hwp_boost_min = min_limit;
1630
1631         /* level at half way mark between min and guranteed */
1632         boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1633
1634         if (cpu->hwp_boost_min < boost_level1)
1635                 cpu->hwp_boost_min = boost_level1;
1636         else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1637                 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1638         else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1639                  max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1640                 cpu->hwp_boost_min = max_limit;
1641         else
1642                 return;
1643
1644         hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1645         wrmsrl(MSR_HWP_REQUEST, hwp_req);
1646         cpu->last_update = cpu->sample.time;
1647 }
1648
1649 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1650 {
1651         if (cpu->hwp_boost_min) {
1652                 bool expired;
1653
1654                 /* Check if we are idle for hold time to boost down */
1655                 expired = time_after64(cpu->sample.time, cpu->last_update +
1656                                        hwp_boost_hold_time_ns);
1657                 if (expired) {
1658                         wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1659                         cpu->hwp_boost_min = 0;
1660                 }
1661         }
1662         cpu->last_update = cpu->sample.time;
1663 }
1664
1665 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1666                                                       u64 time)
1667 {
1668         cpu->sample.time = time;
1669
1670         if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1671                 bool do_io = false;
1672
1673                 cpu->sched_flags = 0;
1674                 /*
1675                  * Set iowait_boost flag and update time. Since IO WAIT flag
1676                  * is set all the time, we can't just conclude that there is
1677                  * some IO bound activity is scheduled on this CPU with just
1678                  * one occurrence. If we receive at least two in two
1679                  * consecutive ticks, then we treat as boost candidate.
1680                  */
1681                 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1682                         do_io = true;
1683
1684                 cpu->last_io_update = time;
1685
1686                 if (do_io)
1687                         intel_pstate_hwp_boost_up(cpu);
1688
1689         } else {
1690                 intel_pstate_hwp_boost_down(cpu);
1691         }
1692 }
1693
1694 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1695                                                 u64 time, unsigned int flags)
1696 {
1697         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1698
1699         cpu->sched_flags |= flags;
1700
1701         if (smp_processor_id() == cpu->cpu)
1702                 intel_pstate_update_util_hwp_local(cpu, time);
1703 }
1704
1705 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1706 {
1707         struct sample *sample = &cpu->sample;
1708
1709         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1710 }
1711
1712 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1713 {
1714         u64 aperf, mperf;
1715         unsigned long flags;
1716         u64 tsc;
1717
1718         local_irq_save(flags);
1719         rdmsrl(MSR_IA32_APERF, aperf);
1720         rdmsrl(MSR_IA32_MPERF, mperf);
1721         tsc = rdtsc();
1722         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1723                 local_irq_restore(flags);
1724                 return false;
1725         }
1726         local_irq_restore(flags);
1727
1728         cpu->last_sample_time = cpu->sample.time;
1729         cpu->sample.time = time;
1730         cpu->sample.aperf = aperf;
1731         cpu->sample.mperf = mperf;
1732         cpu->sample.tsc =  tsc;
1733         cpu->sample.aperf -= cpu->prev_aperf;
1734         cpu->sample.mperf -= cpu->prev_mperf;
1735         cpu->sample.tsc -= cpu->prev_tsc;
1736
1737         cpu->prev_aperf = aperf;
1738         cpu->prev_mperf = mperf;
1739         cpu->prev_tsc = tsc;
1740         /*
1741          * First time this function is invoked in a given cycle, all of the
1742          * previous sample data fields are equal to zero or stale and they must
1743          * be populated with meaningful numbers for things to work, so assume
1744          * that sample.time will always be reset before setting the utilization
1745          * update hook and make the caller skip the sample then.
1746          */
1747         if (cpu->last_sample_time) {
1748                 intel_pstate_calc_avg_perf(cpu);
1749                 return true;
1750         }
1751         return false;
1752 }
1753
1754 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1755 {
1756         return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1757 }
1758
1759 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1760 {
1761         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1762                           cpu->sample.core_avg_perf);
1763 }
1764
1765 static inline int32_t get_target_pstate(struct cpudata *cpu)
1766 {
1767         struct sample *sample = &cpu->sample;
1768         int32_t busy_frac;
1769         int target, avg_pstate;
1770
1771         busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1772                            sample->tsc);
1773
1774         if (busy_frac < cpu->iowait_boost)
1775                 busy_frac = cpu->iowait_boost;
1776
1777         sample->busy_scaled = busy_frac * 100;
1778
1779         target = global.no_turbo || global.turbo_disabled ?
1780                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1781         target += target >> 2;
1782         target = mul_fp(target, busy_frac);
1783         if (target < cpu->pstate.min_pstate)
1784                 target = cpu->pstate.min_pstate;
1785
1786         /*
1787          * If the average P-state during the previous cycle was higher than the
1788          * current target, add 50% of the difference to the target to reduce
1789          * possible performance oscillations and offset possible performance
1790          * loss related to moving the workload from one CPU to another within
1791          * a package/module.
1792          */
1793         avg_pstate = get_avg_pstate(cpu);
1794         if (avg_pstate > target)
1795                 target += (avg_pstate - target) >> 1;
1796
1797         return target;
1798 }
1799
1800 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1801 {
1802         int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1803         int max_pstate = max(min_pstate, cpu->max_perf_ratio);
1804
1805         return clamp_t(int, pstate, min_pstate, max_pstate);
1806 }
1807
1808 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1809 {
1810         if (pstate == cpu->pstate.current_pstate)
1811                 return;
1812
1813         cpu->pstate.current_pstate = pstate;
1814         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1815 }
1816
1817 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1818 {
1819         int from = cpu->pstate.current_pstate;
1820         struct sample *sample;
1821         int target_pstate;
1822
1823         update_turbo_state();
1824
1825         target_pstate = get_target_pstate(cpu);
1826         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1827         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1828         intel_pstate_update_pstate(cpu, target_pstate);
1829
1830         sample = &cpu->sample;
1831         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1832                 fp_toint(sample->busy_scaled),
1833                 from,
1834                 cpu->pstate.current_pstate,
1835                 sample->mperf,
1836                 sample->aperf,
1837                 sample->tsc,
1838                 get_avg_frequency(cpu),
1839                 fp_toint(cpu->iowait_boost * 100));
1840 }
1841
1842 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1843                                      unsigned int flags)
1844 {
1845         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1846         u64 delta_ns;
1847
1848         /* Don't allow remote callbacks */
1849         if (smp_processor_id() != cpu->cpu)
1850                 return;
1851
1852         delta_ns = time - cpu->last_update;
1853         if (flags & SCHED_CPUFREQ_IOWAIT) {
1854                 /* Start over if the CPU may have been idle. */
1855                 if (delta_ns > TICK_NSEC) {
1856                         cpu->iowait_boost = ONE_EIGHTH_FP;
1857                 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
1858                         cpu->iowait_boost <<= 1;
1859                         if (cpu->iowait_boost > int_tofp(1))
1860                                 cpu->iowait_boost = int_tofp(1);
1861                 } else {
1862                         cpu->iowait_boost = ONE_EIGHTH_FP;
1863                 }
1864         } else if (cpu->iowait_boost) {
1865                 /* Clear iowait_boost if the CPU may have been idle. */
1866                 if (delta_ns > TICK_NSEC)
1867                         cpu->iowait_boost = 0;
1868                 else
1869                         cpu->iowait_boost >>= 1;
1870         }
1871         cpu->last_update = time;
1872         delta_ns = time - cpu->sample.time;
1873         if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1874                 return;
1875
1876         if (intel_pstate_sample(cpu, time))
1877                 intel_pstate_adjust_pstate(cpu);
1878 }
1879
1880 static struct pstate_funcs core_funcs = {
1881         .get_max = core_get_max_pstate,
1882         .get_max_physical = core_get_max_pstate_physical,
1883         .get_min = core_get_min_pstate,
1884         .get_turbo = core_get_turbo_pstate,
1885         .get_scaling = core_get_scaling,
1886         .get_val = core_get_val,
1887 };
1888
1889 static const struct pstate_funcs silvermont_funcs = {
1890         .get_max = atom_get_max_pstate,
1891         .get_max_physical = atom_get_max_pstate,
1892         .get_min = atom_get_min_pstate,
1893         .get_turbo = atom_get_turbo_pstate,
1894         .get_val = atom_get_val,
1895         .get_scaling = silvermont_get_scaling,
1896         .get_vid = atom_get_vid,
1897 };
1898
1899 static const struct pstate_funcs airmont_funcs = {
1900         .get_max = atom_get_max_pstate,
1901         .get_max_physical = atom_get_max_pstate,
1902         .get_min = atom_get_min_pstate,
1903         .get_turbo = atom_get_turbo_pstate,
1904         .get_val = atom_get_val,
1905         .get_scaling = airmont_get_scaling,
1906         .get_vid = atom_get_vid,
1907 };
1908
1909 static const struct pstate_funcs knl_funcs = {
1910         .get_max = core_get_max_pstate,
1911         .get_max_physical = core_get_max_pstate_physical,
1912         .get_min = core_get_min_pstate,
1913         .get_turbo = knl_get_turbo_pstate,
1914         .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1915         .get_scaling = core_get_scaling,
1916         .get_val = core_get_val,
1917 };
1918
1919 #define ICPU(model, policy) \
1920         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1921                         (unsigned long)&policy }
1922
1923 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1924         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_funcs),
1925         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_funcs),
1926         ICPU(INTEL_FAM6_ATOM_SILVERMONT,        silvermont_funcs),
1927         ICPU(INTEL_FAM6_IVYBRIDGE,              core_funcs),
1928         ICPU(INTEL_FAM6_HASWELL,                core_funcs),
1929         ICPU(INTEL_FAM6_BROADWELL,              core_funcs),
1930         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_funcs),
1931         ICPU(INTEL_FAM6_HASWELL_X,              core_funcs),
1932         ICPU(INTEL_FAM6_HASWELL_L,              core_funcs),
1933         ICPU(INTEL_FAM6_HASWELL_G,              core_funcs),
1934         ICPU(INTEL_FAM6_BROADWELL_G,            core_funcs),
1935         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_funcs),
1936         ICPU(INTEL_FAM6_SKYLAKE_L,              core_funcs),
1937         ICPU(INTEL_FAM6_BROADWELL_X,            core_funcs),
1938         ICPU(INTEL_FAM6_SKYLAKE,                core_funcs),
1939         ICPU(INTEL_FAM6_BROADWELL_D,            core_funcs),
1940         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_funcs),
1941         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_funcs),
1942         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          core_funcs),
1943         ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS,     core_funcs),
1944         ICPU(INTEL_FAM6_SKYLAKE_X,              core_funcs),
1945         {}
1946 };
1947 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1948
1949 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1950         ICPU(INTEL_FAM6_BROADWELL_D, core_funcs),
1951         ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1952         ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1953         {}
1954 };
1955
1956 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1957         ICPU(INTEL_FAM6_KABYLAKE, core_funcs),
1958         {}
1959 };
1960
1961 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
1962         ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1963         ICPU(INTEL_FAM6_SKYLAKE, core_funcs),
1964         {}
1965 };
1966
1967 static int intel_pstate_init_cpu(unsigned int cpunum)
1968 {
1969         struct cpudata *cpu;
1970
1971         cpu = all_cpu_data[cpunum];
1972
1973         if (!cpu) {
1974                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1975                 if (!cpu)
1976                         return -ENOMEM;
1977
1978                 all_cpu_data[cpunum] = cpu;
1979
1980                 cpu->epp_default = -EINVAL;
1981                 cpu->epp_powersave = -EINVAL;
1982                 cpu->epp_saved = -EINVAL;
1983         }
1984
1985         cpu = all_cpu_data[cpunum];
1986
1987         cpu->cpu = cpunum;
1988
1989         if (hwp_active) {
1990                 const struct x86_cpu_id *id;
1991
1992                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1993                 if (id)
1994                         intel_pstate_disable_ee(cpunum);
1995
1996                 intel_pstate_hwp_enable(cpu);
1997
1998                 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
1999                 if (id && intel_pstate_acpi_pm_profile_server())
2000                         hwp_boost = true;
2001         }
2002
2003         intel_pstate_get_cpu_pstates(cpu);
2004
2005         pr_debug("controlling: cpu %d\n", cpunum);
2006
2007         return 0;
2008 }
2009
2010 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2011 {
2012         struct cpudata *cpu = all_cpu_data[cpu_num];
2013
2014         if (hwp_active && !hwp_boost)
2015                 return;
2016
2017         if (cpu->update_util_set)
2018                 return;
2019
2020         /* Prevent intel_pstate_update_util() from using stale data. */
2021         cpu->sample.time = 0;
2022         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2023                                      (hwp_active ?
2024                                       intel_pstate_update_util_hwp :
2025                                       intel_pstate_update_util));
2026         cpu->update_util_set = true;
2027 }
2028
2029 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2030 {
2031         struct cpudata *cpu_data = all_cpu_data[cpu];
2032
2033         if (!cpu_data->update_util_set)
2034                 return;
2035
2036         cpufreq_remove_update_util_hook(cpu);
2037         cpu_data->update_util_set = false;
2038         synchronize_rcu();
2039 }
2040
2041 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2042 {
2043         return global.turbo_disabled || global.no_turbo ?
2044                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2045 }
2046
2047 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2048                                             unsigned int policy_min,
2049                                             unsigned int policy_max)
2050 {
2051         int max_freq = intel_pstate_get_max_freq(cpu);
2052         int32_t max_policy_perf, min_policy_perf;
2053         int max_state, turbo_max;
2054
2055         /*
2056          * HWP needs some special consideration, because on BDX the
2057          * HWP_REQUEST uses abstract value to represent performance
2058          * rather than pure ratios.
2059          */
2060         if (hwp_active) {
2061                 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
2062         } else {
2063                 max_state = global.no_turbo || global.turbo_disabled ?
2064                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2065                 turbo_max = cpu->pstate.turbo_pstate;
2066         }
2067
2068         max_policy_perf = max_state * policy_max / max_freq;
2069         if (policy_max == policy_min) {
2070                 min_policy_perf = max_policy_perf;
2071         } else {
2072                 min_policy_perf = max_state * policy_min / max_freq;
2073                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2074                                           0, max_policy_perf);
2075         }
2076
2077         pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
2078                  cpu->cpu, max_state, min_policy_perf, max_policy_perf);
2079
2080         /* Normalize user input to [min_perf, max_perf] */
2081         if (per_cpu_limits) {
2082                 cpu->min_perf_ratio = min_policy_perf;
2083                 cpu->max_perf_ratio = max_policy_perf;
2084         } else {
2085                 int32_t global_min, global_max;
2086
2087                 /* Global limits are in percent of the maximum turbo P-state. */
2088                 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2089                 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2090                 global_min = clamp_t(int32_t, global_min, 0, global_max);
2091
2092                 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2093                          global_min, global_max);
2094
2095                 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2096                 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2097                 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2098                 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2099
2100                 /* Make sure min_perf <= max_perf */
2101                 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2102                                           cpu->max_perf_ratio);
2103
2104         }
2105         pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2106                  cpu->max_perf_ratio,
2107                  cpu->min_perf_ratio);
2108 }
2109
2110 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2111 {
2112         struct cpudata *cpu;
2113
2114         if (!policy->cpuinfo.max_freq)
2115                 return -ENODEV;
2116
2117         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2118                  policy->cpuinfo.max_freq, policy->max);
2119
2120         cpu = all_cpu_data[policy->cpu];
2121         cpu->policy = policy->policy;
2122
2123         mutex_lock(&intel_pstate_limits_lock);
2124
2125         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2126
2127         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2128                 /*
2129                  * NOHZ_FULL CPUs need this as the governor callback may not
2130                  * be invoked on them.
2131                  */
2132                 intel_pstate_clear_update_util_hook(policy->cpu);
2133                 intel_pstate_max_within_limits(cpu);
2134         } else {
2135                 intel_pstate_set_update_util_hook(policy->cpu);
2136         }
2137
2138         if (hwp_active) {
2139                 /*
2140                  * When hwp_boost was active before and dynamically it
2141                  * was turned off, in that case we need to clear the
2142                  * update util hook.
2143                  */
2144                 if (!hwp_boost)
2145                         intel_pstate_clear_update_util_hook(policy->cpu);
2146                 intel_pstate_hwp_set(policy->cpu);
2147         }
2148
2149         mutex_unlock(&intel_pstate_limits_lock);
2150
2151         return 0;
2152 }
2153
2154 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2155                                            struct cpufreq_policy_data *policy)
2156 {
2157         if (!hwp_active &&
2158             cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2159             policy->max < policy->cpuinfo.max_freq &&
2160             policy->max > cpu->pstate.max_freq) {
2161                 pr_debug("policy->max > max non turbo frequency\n");
2162                 policy->max = policy->cpuinfo.max_freq;
2163         }
2164 }
2165
2166 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2167 {
2168         struct cpudata *cpu = all_cpu_data[policy->cpu];
2169
2170         update_turbo_state();
2171         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2172                                      intel_pstate_get_max_freq(cpu));
2173
2174         intel_pstate_adjust_policy_max(cpu, policy);
2175
2176         return 0;
2177 }
2178
2179 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2180 {
2181         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2182 }
2183
2184 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2185 {
2186         pr_debug("CPU %d exiting\n", policy->cpu);
2187
2188         intel_pstate_clear_update_util_hook(policy->cpu);
2189         if (hwp_active) {
2190                 intel_pstate_hwp_save_state(policy);
2191                 intel_pstate_hwp_force_min_perf(policy->cpu);
2192         } else {
2193                 intel_cpufreq_stop_cpu(policy);
2194         }
2195 }
2196
2197 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2198 {
2199         intel_pstate_exit_perf_limits(policy);
2200
2201         policy->fast_switch_possible = false;
2202
2203         return 0;
2204 }
2205
2206 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2207 {
2208         struct cpudata *cpu;
2209         int rc;
2210
2211         rc = intel_pstate_init_cpu(policy->cpu);
2212         if (rc)
2213                 return rc;
2214
2215         cpu = all_cpu_data[policy->cpu];
2216
2217         cpu->max_perf_ratio = 0xFF;
2218         cpu->min_perf_ratio = 0;
2219
2220         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2221         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2222
2223         /* cpuinfo and default policy values */
2224         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2225         update_turbo_state();
2226         global.turbo_disabled_mf = global.turbo_disabled;
2227         policy->cpuinfo.max_freq = global.turbo_disabled ?
2228                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2229         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2230
2231         if (hwp_active) {
2232                 unsigned int max_freq;
2233
2234                 max_freq = global.turbo_disabled ?
2235                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2236                 if (max_freq < policy->cpuinfo.max_freq)
2237                         policy->cpuinfo.max_freq = max_freq;
2238         }
2239
2240         intel_pstate_init_acpi_perf_limits(policy);
2241
2242         policy->fast_switch_possible = true;
2243
2244         return 0;
2245 }
2246
2247 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2248 {
2249         int ret = __intel_pstate_cpu_init(policy);
2250
2251         if (ret)
2252                 return ret;
2253
2254         if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2255                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2256         else
2257                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2258
2259         return 0;
2260 }
2261
2262 static struct cpufreq_driver intel_pstate = {
2263         .flags          = CPUFREQ_CONST_LOOPS,
2264         .verify         = intel_pstate_verify_policy,
2265         .setpolicy      = intel_pstate_set_policy,
2266         .suspend        = intel_pstate_hwp_save_state,
2267         .resume         = intel_pstate_resume,
2268         .init           = intel_pstate_cpu_init,
2269         .exit           = intel_pstate_cpu_exit,
2270         .stop_cpu       = intel_pstate_stop_cpu,
2271         .update_limits  = intel_pstate_update_limits,
2272         .name           = "intel_pstate",
2273 };
2274
2275 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2276 {
2277         struct cpudata *cpu = all_cpu_data[policy->cpu];
2278
2279         update_turbo_state();
2280         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2281                                      intel_pstate_get_max_freq(cpu));
2282
2283         intel_pstate_adjust_policy_max(cpu, policy);
2284
2285         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2286
2287         return 0;
2288 }
2289
2290 /* Use of trace in passive mode:
2291  *
2292  * In passive mode the trace core_busy field (also known as the
2293  * performance field, and lablelled as such on the graphs; also known as
2294  * core_avg_perf) is not needed and so is re-assigned to indicate if the
2295  * driver call was via the normal or fast switch path. Various graphs
2296  * output from the intel_pstate_tracer.py utility that include core_busy
2297  * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2298  * so we use 10 to indicate the the normal path through the driver, and
2299  * 90 to indicate the fast switch path through the driver.
2300  * The scaled_busy field is not used, and is set to 0.
2301  */
2302
2303 #define INTEL_PSTATE_TRACE_TARGET 10
2304 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2305
2306 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2307 {
2308         struct sample *sample;
2309
2310         if (!trace_pstate_sample_enabled())
2311                 return;
2312
2313         if (!intel_pstate_sample(cpu, ktime_get()))
2314                 return;
2315
2316         sample = &cpu->sample;
2317         trace_pstate_sample(trace_type,
2318                 0,
2319                 old_pstate,
2320                 cpu->pstate.current_pstate,
2321                 sample->mperf,
2322                 sample->aperf,
2323                 sample->tsc,
2324                 get_avg_frequency(cpu),
2325                 fp_toint(cpu->iowait_boost * 100));
2326 }
2327
2328 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2329                                 unsigned int target_freq,
2330                                 unsigned int relation)
2331 {
2332         struct cpudata *cpu = all_cpu_data[policy->cpu];
2333         struct cpufreq_freqs freqs;
2334         int target_pstate, old_pstate;
2335
2336         update_turbo_state();
2337
2338         freqs.old = policy->cur;
2339         freqs.new = target_freq;
2340
2341         cpufreq_freq_transition_begin(policy, &freqs);
2342         switch (relation) {
2343         case CPUFREQ_RELATION_L:
2344                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2345                 break;
2346         case CPUFREQ_RELATION_H:
2347                 target_pstate = freqs.new / cpu->pstate.scaling;
2348                 break;
2349         default:
2350                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2351                 break;
2352         }
2353         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2354         old_pstate = cpu->pstate.current_pstate;
2355         if (target_pstate != cpu->pstate.current_pstate) {
2356                 cpu->pstate.current_pstate = target_pstate;
2357                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2358                               pstate_funcs.get_val(cpu, target_pstate));
2359         }
2360         freqs.new = target_pstate * cpu->pstate.scaling;
2361         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
2362         cpufreq_freq_transition_end(policy, &freqs, false);
2363
2364         return 0;
2365 }
2366
2367 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2368                                               unsigned int target_freq)
2369 {
2370         struct cpudata *cpu = all_cpu_data[policy->cpu];
2371         int target_pstate, old_pstate;
2372
2373         update_turbo_state();
2374
2375         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2376         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2377         old_pstate = cpu->pstate.current_pstate;
2378         intel_pstate_update_pstate(cpu, target_pstate);
2379         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2380         return target_pstate * cpu->pstate.scaling;
2381 }
2382
2383 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2384 {
2385         int max_state, turbo_max, min_freq, max_freq, ret;
2386         struct freq_qos_request *req;
2387         struct cpudata *cpu;
2388         struct device *dev;
2389
2390         dev = get_cpu_device(policy->cpu);
2391         if (!dev)
2392                 return -ENODEV;
2393
2394         ret = __intel_pstate_cpu_init(policy);
2395         if (ret)
2396                 return ret;
2397
2398         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2399         policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2400         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2401         policy->cur = policy->cpuinfo.min_freq;
2402
2403         req = kcalloc(2, sizeof(*req), GFP_KERNEL);
2404         if (!req) {
2405                 ret = -ENOMEM;
2406                 goto pstate_exit;
2407         }
2408
2409         cpu = all_cpu_data[policy->cpu];
2410
2411         if (hwp_active)
2412                 intel_pstate_get_hwp_max(policy->cpu, &turbo_max, &max_state);
2413         else
2414                 turbo_max = cpu->pstate.turbo_pstate;
2415
2416         min_freq = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2417         min_freq *= cpu->pstate.scaling;
2418         max_freq = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2419         max_freq *= cpu->pstate.scaling;
2420
2421         ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
2422                                    min_freq);
2423         if (ret < 0) {
2424                 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
2425                 goto free_req;
2426         }
2427
2428         ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
2429                                    max_freq);
2430         if (ret < 0) {
2431                 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
2432                 goto remove_min_req;
2433         }
2434
2435         policy->driver_data = req;
2436
2437         return 0;
2438
2439 remove_min_req:
2440         freq_qos_remove_request(req);
2441 free_req:
2442         kfree(req);
2443 pstate_exit:
2444         intel_pstate_exit_perf_limits(policy);
2445
2446         return ret;
2447 }
2448
2449 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
2450 {
2451         struct freq_qos_request *req;
2452
2453         req = policy->driver_data;
2454
2455         freq_qos_remove_request(req + 1);
2456         freq_qos_remove_request(req);
2457         kfree(req);
2458
2459         return intel_pstate_cpu_exit(policy);
2460 }
2461
2462 static struct cpufreq_driver intel_cpufreq = {
2463         .flags          = CPUFREQ_CONST_LOOPS,
2464         .verify         = intel_cpufreq_verify_policy,
2465         .target         = intel_cpufreq_target,
2466         .fast_switch    = intel_cpufreq_fast_switch,
2467         .init           = intel_cpufreq_cpu_init,
2468         .exit           = intel_cpufreq_cpu_exit,
2469         .stop_cpu       = intel_cpufreq_stop_cpu,
2470         .update_limits  = intel_pstate_update_limits,
2471         .name           = "intel_cpufreq",
2472 };
2473
2474 static struct cpufreq_driver *default_driver = &intel_pstate;
2475
2476 static void intel_pstate_driver_cleanup(void)
2477 {
2478         unsigned int cpu;
2479
2480         get_online_cpus();
2481         for_each_online_cpu(cpu) {
2482                 if (all_cpu_data[cpu]) {
2483                         if (intel_pstate_driver == &intel_pstate)
2484                                 intel_pstate_clear_update_util_hook(cpu);
2485
2486                         kfree(all_cpu_data[cpu]);
2487                         all_cpu_data[cpu] = NULL;
2488                 }
2489         }
2490         put_online_cpus();
2491         intel_pstate_driver = NULL;
2492 }
2493
2494 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2495 {
2496         int ret;
2497
2498         memset(&global, 0, sizeof(global));
2499         global.max_perf_pct = 100;
2500
2501         intel_pstate_driver = driver;
2502         ret = cpufreq_register_driver(intel_pstate_driver);
2503         if (ret) {
2504                 intel_pstate_driver_cleanup();
2505                 return ret;
2506         }
2507
2508         global.min_perf_pct = min_perf_pct_min();
2509
2510         return 0;
2511 }
2512
2513 static int intel_pstate_unregister_driver(void)
2514 {
2515         if (hwp_active)
2516                 return -EBUSY;
2517
2518         cpufreq_unregister_driver(intel_pstate_driver);
2519         intel_pstate_driver_cleanup();
2520
2521         return 0;
2522 }
2523
2524 static ssize_t intel_pstate_show_status(char *buf)
2525 {
2526         if (!intel_pstate_driver)
2527                 return sprintf(buf, "off\n");
2528
2529         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2530                                         "active" : "passive");
2531 }
2532
2533 static int intel_pstate_update_status(const char *buf, size_t size)
2534 {
2535         int ret;
2536
2537         if (size == 3 && !strncmp(buf, "off", size)) {
2538                 if (!intel_pstate_driver)
2539                         return -EINVAL;
2540
2541                 if (hwp_active)
2542                         return -EBUSY;
2543
2544                 return intel_pstate_unregister_driver();
2545         }
2546
2547         if (size == 6 && !strncmp(buf, "active", size)) {
2548                 if (intel_pstate_driver) {
2549                         if (intel_pstate_driver == &intel_pstate)
2550                                 return 0;
2551
2552                         ret = intel_pstate_unregister_driver();
2553                         if (ret)
2554                                 return ret;
2555                 }
2556
2557                 return intel_pstate_register_driver(&intel_pstate);
2558         }
2559
2560         if (size == 7 && !strncmp(buf, "passive", size)) {
2561                 if (intel_pstate_driver) {
2562                         if (intel_pstate_driver == &intel_cpufreq)
2563                                 return 0;
2564
2565                         ret = intel_pstate_unregister_driver();
2566                         if (ret)
2567                                 return ret;
2568                 }
2569
2570                 return intel_pstate_register_driver(&intel_cpufreq);
2571         }
2572
2573         return -EINVAL;
2574 }
2575
2576 static int no_load __initdata;
2577 static int no_hwp __initdata;
2578 static int hwp_only __initdata;
2579 static unsigned int force_load __initdata;
2580
2581 static int __init intel_pstate_msrs_not_valid(void)
2582 {
2583         if (!pstate_funcs.get_max() ||
2584             !pstate_funcs.get_min() ||
2585             !pstate_funcs.get_turbo())
2586                 return -ENODEV;
2587
2588         return 0;
2589 }
2590
2591 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2592 {
2593         pstate_funcs.get_max   = funcs->get_max;
2594         pstate_funcs.get_max_physical = funcs->get_max_physical;
2595         pstate_funcs.get_min   = funcs->get_min;
2596         pstate_funcs.get_turbo = funcs->get_turbo;
2597         pstate_funcs.get_scaling = funcs->get_scaling;
2598         pstate_funcs.get_val   = funcs->get_val;
2599         pstate_funcs.get_vid   = funcs->get_vid;
2600         pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2601 }
2602
2603 #ifdef CONFIG_ACPI
2604
2605 static bool __init intel_pstate_no_acpi_pss(void)
2606 {
2607         int i;
2608
2609         for_each_possible_cpu(i) {
2610                 acpi_status status;
2611                 union acpi_object *pss;
2612                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2613                 struct acpi_processor *pr = per_cpu(processors, i);
2614
2615                 if (!pr)
2616                         continue;
2617
2618                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2619                 if (ACPI_FAILURE(status))
2620                         continue;
2621
2622                 pss = buffer.pointer;
2623                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2624                         kfree(pss);
2625                         return false;
2626                 }
2627
2628                 kfree(pss);
2629         }
2630
2631         pr_debug("ACPI _PSS not found\n");
2632         return true;
2633 }
2634
2635 static bool __init intel_pstate_no_acpi_pcch(void)
2636 {
2637         acpi_status status;
2638         acpi_handle handle;
2639
2640         status = acpi_get_handle(NULL, "\\_SB", &handle);
2641         if (ACPI_FAILURE(status))
2642                 goto not_found;
2643
2644         if (acpi_has_method(handle, "PCCH"))
2645                 return false;
2646
2647 not_found:
2648         pr_debug("ACPI PCCH not found\n");
2649         return true;
2650 }
2651
2652 static bool __init intel_pstate_has_acpi_ppc(void)
2653 {
2654         int i;
2655
2656         for_each_possible_cpu(i) {
2657                 struct acpi_processor *pr = per_cpu(processors, i);
2658
2659                 if (!pr)
2660                         continue;
2661                 if (acpi_has_method(pr->handle, "_PPC"))
2662                         return true;
2663         }
2664         pr_debug("ACPI _PPC not found\n");
2665         return false;
2666 }
2667
2668 enum {
2669         PSS,
2670         PPC,
2671 };
2672
2673 /* Hardware vendor-specific info that has its own power management modes */
2674 static struct acpi_platform_list plat_info[] __initdata = {
2675         {"HP    ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2676         {"ORACLE", "X4-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2677         {"ORACLE", "X4-2L   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2678         {"ORACLE", "X4-2B   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2679         {"ORACLE", "X3-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2680         {"ORACLE", "X3-2L   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2681         {"ORACLE", "X3-2B   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2682         {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2683         {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2684         {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2685         {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2686         {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2687         {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2688         {"ORACLE", "X6-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2689         {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2690         { } /* End */
2691 };
2692
2693 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2694 {
2695         const struct x86_cpu_id *id;
2696         u64 misc_pwr;
2697         int idx;
2698
2699         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2700         if (id) {
2701                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2702                 if (misc_pwr & (1 << 8)) {
2703                         pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n");
2704                         return true;
2705                 }
2706         }
2707
2708         idx = acpi_match_platform_list(plat_info);
2709         if (idx < 0)
2710                 return false;
2711
2712         switch (plat_info[idx].data) {
2713         case PSS:
2714                 if (!intel_pstate_no_acpi_pss())
2715                         return false;
2716
2717                 return intel_pstate_no_acpi_pcch();
2718         case PPC:
2719                 return intel_pstate_has_acpi_ppc() && !force_load;
2720         }
2721
2722         return false;
2723 }
2724
2725 static void intel_pstate_request_control_from_smm(void)
2726 {
2727         /*
2728          * It may be unsafe to request P-states control from SMM if _PPC support
2729          * has not been enabled.
2730          */
2731         if (acpi_ppc)
2732                 acpi_processor_pstate_control();
2733 }
2734 #else /* CONFIG_ACPI not enabled */
2735 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2736 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2737 static inline void intel_pstate_request_control_from_smm(void) {}
2738 #endif /* CONFIG_ACPI */
2739
2740 #define INTEL_PSTATE_HWP_BROADWELL      0x01
2741
2742 #define ICPU_HWP(model, hwp_mode) \
2743         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode }
2744
2745 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2746         ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
2747         ICPU_HWP(INTEL_FAM6_BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
2748         ICPU_HWP(X86_MODEL_ANY, 0),
2749         {}
2750 };
2751
2752 static int __init intel_pstate_init(void)
2753 {
2754         const struct x86_cpu_id *id;
2755         int rc;
2756
2757         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2758                 return -ENODEV;
2759
2760         if (no_load)
2761                 return -ENODEV;
2762
2763         id = x86_match_cpu(hwp_support_ids);
2764         if (id) {
2765                 copy_cpu_funcs(&core_funcs);
2766                 if (!no_hwp) {
2767                         hwp_active++;
2768                         hwp_mode_bdw = id->driver_data;
2769                         intel_pstate.attr = hwp_cpufreq_attrs;
2770                         goto hwp_cpu_matched;
2771                 }
2772         } else {
2773                 id = x86_match_cpu(intel_pstate_cpu_ids);
2774                 if (!id) {
2775                         pr_info("CPU model not supported\n");
2776                         return -ENODEV;
2777                 }
2778
2779                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2780         }
2781
2782         if (intel_pstate_msrs_not_valid()) {
2783                 pr_info("Invalid MSRs\n");
2784                 return -ENODEV;
2785         }
2786
2787 hwp_cpu_matched:
2788         /*
2789          * The Intel pstate driver will be ignored if the platform
2790          * firmware has its own power management modes.
2791          */
2792         if (intel_pstate_platform_pwr_mgmt_exists()) {
2793                 pr_info("P-states controlled by the platform\n");
2794                 return -ENODEV;
2795         }
2796
2797         if (!hwp_active && hwp_only)
2798                 return -ENOTSUPP;
2799
2800         pr_info("Intel P-state driver initializing\n");
2801
2802         all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
2803         if (!all_cpu_data)
2804                 return -ENOMEM;
2805
2806         intel_pstate_request_control_from_smm();
2807
2808         intel_pstate_sysfs_expose_params();
2809
2810         mutex_lock(&intel_pstate_driver_lock);
2811         rc = intel_pstate_register_driver(default_driver);
2812         mutex_unlock(&intel_pstate_driver_lock);
2813         if (rc)
2814                 return rc;
2815
2816         if (hwp_active)
2817                 pr_info("HWP enabled\n");
2818
2819         return 0;
2820 }
2821 device_initcall(intel_pstate_init);
2822
2823 static int __init intel_pstate_setup(char *str)
2824 {
2825         if (!str)
2826                 return -EINVAL;
2827
2828         if (!strcmp(str, "disable")) {
2829                 no_load = 1;
2830         } else if (!strcmp(str, "passive")) {
2831                 pr_info("Passive mode enabled\n");
2832                 default_driver = &intel_cpufreq;
2833                 no_hwp = 1;
2834         }
2835         if (!strcmp(str, "no_hwp")) {
2836                 pr_info("HWP disabled\n");
2837                 no_hwp = 1;
2838         }
2839         if (!strcmp(str, "force"))
2840                 force_load = 1;
2841         if (!strcmp(str, "hwp_only"))
2842                 hwp_only = 1;
2843         if (!strcmp(str, "per_cpu_perf_limits"))
2844                 per_cpu_limits = true;
2845
2846 #ifdef CONFIG_ACPI
2847         if (!strcmp(str, "support_acpi_ppc"))
2848                 acpi_ppc = true;
2849 #endif
2850
2851         return 0;
2852 }
2853 early_param("intel_pstate", intel_pstate_setup);
2854
2855 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2856 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2857 MODULE_LICENSE("GPL");