drivers/cpufreq/intel_pstate.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * intel_pstate.c: Native P state management for Intel processors
   4  *
   5  * (C) Copyright 2012 Intel Corporation
   6  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/kernel.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/module.h>
  14 #include <linux/ktime.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/tick.h>
  17 #include <linux/slab.h>
  18 #include <linux/sched/cpufreq.h>
  19 #include <linux/list.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpufreq.h>
  22 #include <linux/sysfs.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/acpi.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/pm_qos.h>
  28 #include <trace/events/power.h>
  29
  30 #include <asm/cpu.h>
  31 #include <asm/div64.h>
  32 #include <asm/msr.h>
  33 #include <asm/cpu_device_id.h>
  34 #include <asm/cpufeature.h>
  35 #include <asm/intel-family.h>
  36 #include "../drivers/thermal/intel/thermal_interrupt.h"
  37
  38 #define INTEL_PSTATE_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
  39
  40 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  41 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP      5000
  42 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
  43
  44 #ifdef CONFIG_ACPI
  45 #include <acpi/processor.h>
  46 #include <acpi/cppc_acpi.h>
  47 #endif
  48
  49 #define FRAC_BITS 8
  50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  51 #define fp_toint(X) ((X) >> FRAC_BITS)
  52
  53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
  54
  55 #define EXT_BITS 6
  56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  59
  60 static inline int32_t mul_fp(int32_t x, int32_t y)
  61 {
  62         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  63 }
  64
  65 static inline int32_t div_fp(s64 x, s64 y)
  66 {
  67         return div64_s64((int64_t)x << FRAC_BITS, y);
  68 }
  69
  70 static inline int ceiling_fp(int32_t x)
  71 {
  72         int mask, ret;
  73
  74         ret = fp_toint(x);
  75         mask = (1 << FRAC_BITS) - 1;
  76         if (x & mask)
  77                 ret += 1;
  78         return ret;
  79 }
  80
  81 static inline u64 mul_ext_fp(u64 x, u64 y)
  82 {
  83         return (x * y) >> EXT_FRAC_BITS;
  84 }
  85
  86 static inline u64 div_ext_fp(u64 x, u64 y)
  87 {
  88         return div64_u64(x << EXT_FRAC_BITS, y);
  89 }
  90
  91 /**
  92  * struct sample -      Store performance sample
  93  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  94  *                      performance during last sample period
  95  * @busy_scaled:        Scaled busy value which is used to calculate next
  96  *                      P state. This can be different than core_avg_perf
  97  *                      to account for cpu idle period
  98  * @aperf:              Difference of actual performance frequency clock count
  99  *                      read from APERF MSR between last and current sample
 100  * @mperf:              Difference of maximum performance frequency clock count
 101  *                      read from MPERF MSR between last and current sample
 102  * @tsc:                Difference of time stamp counter between last and
 103  *                      current sample
 104  * @time:               Current time from scheduler
 105  *
 106  * This structure is used in the cpudata structure to store performance sample
 107  * data for choosing next P State.
 108  */
 109 struct sample {
 110         int32_t core_avg_perf;
 111         int32_t busy_scaled;
 112         u64 aperf;
 113         u64 mperf;
 114         u64 tsc;
 115         u64 time;
 116 };
 117
 118 /**
 119  * struct pstate_data - Store P state data
 120  * @current_pstate:     Current requested P state
 121  * @min_pstate:         Min P state possible for this platform
 122  * @max_pstate:         Max P state possible for this platform
 123  * @max_pstate_physical:This is physical Max P state for a processor
 124  *                      This can be higher than the max_pstate which can
 125  *                      be limited by platform thermal design power limits
 126  * @perf_ctl_scaling:   PERF_CTL P-state to frequency scaling factor
 127  * @scaling:            Scaling factor between performance and frequency
 128  * @turbo_pstate:       Max Turbo P state possible for this platform
 129  * @min_freq:           @min_pstate frequency in cpufreq units
 130  * @max_freq:           @max_pstate frequency in cpufreq units
 131  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 132  *
 133  * Stores the per cpu model P state limits and current P state.
 134  */
 135 struct pstate_data {
 136         int     current_pstate;
 137         int     min_pstate;
 138         int     max_pstate;
 139         int     max_pstate_physical;
 140         int     perf_ctl_scaling;
 141         int     scaling;
 142         int     turbo_pstate;
 143         unsigned int min_freq;
 144         unsigned int max_freq;
 145         unsigned int turbo_freq;
 146 };
 147
 148 /**
 149  * struct vid_data -    Stores voltage information data
 150  * @min:                VID data for this platform corresponding to
 151  *                      the lowest P state
 152  * @max:                VID data corresponding to the highest P State.
 153  * @turbo:              VID data for turbo P state
 154  * @ratio:              Ratio of (vid max - vid min) /
 155  *                      (max P state - Min P State)
 156  *
 157  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 158  * This data is used in Atom platforms, where in addition to target P state,
 159  * the voltage data needs to be specified to select next P State.
 160  */
 161 struct vid_data {
 162         int min;
 163         int max;
 164         int turbo;
 165         int32_t ratio;
 166 };
 167
 168 /**
 169  * struct global_params - Global parameters, mostly tunable via sysfs.
 170  * @no_turbo:           Whether or not to use turbo P-states.
 171  * @turbo_disabled:     Whether or not turbo P-states are available at all,
 172  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
 173  *                      not the maximum reported turbo P-state is different from
 174  *                      the maximum reported non-turbo one.
 175  * @turbo_disabled_mf:  The @turbo_disabled value reflected by cpuinfo.max_freq.
 176  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
 177  *                      P-state capacity.
 178  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
 179  *                      P-state capacity.
 180  */
 181 struct global_params {
 182         bool no_turbo;
 183         bool turbo_disabled;
 184         bool turbo_disabled_mf;
 185         int max_perf_pct;
 186         int min_perf_pct;
 187 };
 188
 189 /**
 190  * struct cpudata -     Per CPU instance data storage
 191  * @cpu:                CPU number for this instance data
 192  * @policy:             CPUFreq policy value
 193  * @update_util:        CPUFreq utility callback information
 194  * @update_util_set:    CPUFreq utility callback is set
 195  * @iowait_boost:       iowait-related boost fraction
 196  * @last_update:        Time of the last update.
 197  * @pstate:             Stores P state limits for this CPU
 198  * @vid:                Stores VID limits for this CPU
 199  * @last_sample_time:   Last Sample time
 200  * @aperf_mperf_shift:  APERF vs MPERF counting frequency difference
 201  * @prev_aperf:         Last APERF value read from APERF MSR
 202  * @prev_mperf:         Last MPERF value read from MPERF MSR
 203  * @prev_tsc:           Last timestamp counter (TSC) value
 204  * @prev_cummulative_iowait: IO Wait time difference from last and
 205  *                      current sample
 206  * @sample:             Storage for storing last Sample data
 207  * @min_perf_ratio:     Minimum capacity in terms of PERF or HWP ratios
 208  * @max_perf_ratio:     Maximum capacity in terms of PERF or HWP ratios
 209  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 210  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 211  * @epp_powersave:      Last saved HWP energy performance preference
 212  *                      (EPP) or energy performance bias (EPB),
 213  *                      when policy switched to performance
 214  * @epp_policy:         Last saved policy used to set EPP/EPB
 215  * @epp_default:        Power on default HWP energy performance
 216  *                      preference/bias
 217  * @epp_cached          Cached HWP energy-performance preference value
 218  * @hwp_req_cached:     Cached value of the last HWP Request MSR
 219  * @hwp_cap_cached:     Cached value of the last HWP Capabilities MSR
 220  * @last_io_update:     Last time when IO wake flag was set
 221  * @sched_flags:        Store scheduler flags for possible cross CPU update
 222  * @hwp_boost_min:      Last HWP boosted min performance
 223  * @suspended:          Whether or not the driver has been suspended.
 224  * @hwp_notify_work:    workqueue for HWP notifications.
 225  *
 226  * This structure stores per CPU instance data for all CPUs.
 227  */
 228 struct cpudata {
 229         int cpu;
 230
 231         unsigned int policy;
 232         struct update_util_data update_util;
 233         bool   update_util_set;
 234
 235         struct pstate_data pstate;
 236         struct vid_data vid;
 237
 238         u64     last_update;
 239         u64     last_sample_time;
 240         u64     aperf_mperf_shift;
 241         u64     prev_aperf;
 242         u64     prev_mperf;
 243         u64     prev_tsc;
 244         u64     prev_cummulative_iowait;
 245         struct sample sample;
 246         int32_t min_perf_ratio;
 247         int32_t max_perf_ratio;
 248 #ifdef CONFIG_ACPI
 249         struct acpi_processor_performance acpi_perf_data;
 250         bool valid_pss_table;
 251 #endif
 252         unsigned int iowait_boost;
 253         s16 epp_powersave;
 254         s16 epp_policy;
 255         s16 epp_default;
 256         s16 epp_cached;
 257         u64 hwp_req_cached;
 258         u64 hwp_cap_cached;
 259         u64 last_io_update;
 260         unsigned int sched_flags;
 261         u32 hwp_boost_min;
 262         bool suspended;
 263         struct delayed_work hwp_notify_work;
 264 };
 265
 266 static struct cpudata **all_cpu_data;
 267
 268 /**
 269  * struct pstate_funcs - Per CPU model specific callbacks
 270  * @get_max:            Callback to get maximum non turbo effective P state
 271  * @get_max_physical:   Callback to get maximum non turbo physical P state
 272  * @get_min:            Callback to get minimum P state
 273  * @get_turbo:          Callback to get turbo P state
 274  * @get_scaling:        Callback to get frequency scaling factor
 275  * @get_cpu_scaling:    Get frequency scaling factor for a given cpu
 276  * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
 277  * @get_val:            Callback to convert P state to actual MSR write value
 278  * @get_vid:            Callback to get VID data for Atom platforms
 279  *
 280  * Core and Atom CPU models have different way to get P State limits. This
 281  * structure is used to store those callbacks.
 282  */
 283 struct pstate_funcs {
 284         int (*get_max)(int cpu);
 285         int (*get_max_physical)(int cpu);
 286         int (*get_min)(int cpu);
 287         int (*get_turbo)(int cpu);
 288         int (*get_scaling)(void);
 289         int (*get_cpu_scaling)(int cpu);
 290         int (*get_aperf_mperf_shift)(void);
 291         u64 (*get_val)(struct cpudata*, int pstate);
 292         void (*get_vid)(struct cpudata *);
 293 };
 294
 295 static struct pstate_funcs pstate_funcs __read_mostly;
 296
 297 static int hwp_active __read_mostly;
 298 static int hwp_mode_bdw __read_mostly;
 299 static bool per_cpu_limits __read_mostly;
 300 static bool hwp_boost __read_mostly;
 301 static bool hwp_forced __read_mostly;
 302
 303 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
 304
 305 #define HYBRID_SCALING_FACTOR   78741
 306
 307 static inline int core_get_scaling(void)
 308 {
 309         return 100000;
 310 }
 311
 312 #ifdef CONFIG_ACPI
 313 static bool acpi_ppc;
 314 #endif
 315
 316 static struct global_params global;
 317
 318 static DEFINE_MUTEX(intel_pstate_driver_lock);
 319 static DEFINE_MUTEX(intel_pstate_limits_lock);
 320
 321 #ifdef CONFIG_ACPI
 322
 323 static bool intel_pstate_acpi_pm_profile_server(void)
 324 {
 325         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 326             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 327                 return true;
 328
 329         return false;
 330 }
 331
 332 static bool intel_pstate_get_ppc_enable_status(void)
 333 {
 334         if (intel_pstate_acpi_pm_profile_server())
 335                 return true;
 336
 337         return acpi_ppc;
 338 }
 339
 340 #ifdef CONFIG_ACPI_CPPC_LIB
 341
 342 /* The work item is needed to avoid CPU hotplug locking issues */
 343 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 344 {
 345         sched_set_itmt_support();
 346 }
 347
 348 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 349
 350 #define CPPC_MAX_PERF   U8_MAX
 351
 352 static void intel_pstate_set_itmt_prio(int cpu)
 353 {
 354         struct cppc_perf_caps cppc_perf;
 355         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 356         int ret;
 357
 358         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 359         if (ret)
 360                 return;
 361
 362         /*
 363          * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
 364          * In this case we can't use CPPC.highest_perf to enable ITMT.
 365          * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
 366          */
 367         if (cppc_perf.highest_perf == CPPC_MAX_PERF)
 368                 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
 369
 370         /*
 371          * The priorities can be set regardless of whether or not
 372          * sched_set_itmt_support(true) has been called and it is valid to
 373          * update them at any time after it has been called.
 374          */
 375         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 376
 377         if (max_highest_perf <= min_highest_perf) {
 378                 if (cppc_perf.highest_perf > max_highest_perf)
 379                         max_highest_perf = cppc_perf.highest_perf;
 380
 381                 if (cppc_perf.highest_perf < min_highest_perf)
 382                         min_highest_perf = cppc_perf.highest_perf;
 383
 384                 if (max_highest_perf > min_highest_perf) {
 385                         /*
 386                          * This code can be run during CPU online under the
 387                          * CPU hotplug locks, so sched_set_itmt_support()
 388                          * cannot be called from here.  Queue up a work item
 389                          * to invoke it.
 390                          */
 391                         schedule_work(&sched_itmt_work);
 392                 }
 393         }
 394 }
 395
 396 static int intel_pstate_get_cppc_guaranteed(int cpu)
 397 {
 398         struct cppc_perf_caps cppc_perf;
 399         int ret;
 400
 401         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 402         if (ret)
 403                 return ret;
 404
 405         if (cppc_perf.guaranteed_perf)
 406                 return cppc_perf.guaranteed_perf;
 407
 408         return cppc_perf.nominal_perf;
 409 }
 410
 411 static int intel_pstate_cppc_get_scaling(int cpu)
 412 {
 413         struct cppc_perf_caps cppc_perf;
 414         int ret;
 415
 416         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 417
 418         /*
 419          * If the nominal frequency and the nominal performance are not
 420          * zero and the ratio between them is not 100, return the hybrid
 421          * scaling factor.
 422          */
 423         if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq &&
 424             cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)
 425                 return HYBRID_SCALING_FACTOR;
 426
 427         return core_get_scaling();
 428 }
 429
 430 #else /* CONFIG_ACPI_CPPC_LIB */
 431 static inline void intel_pstate_set_itmt_prio(int cpu)
 432 {
 433 }
 434 #endif /* CONFIG_ACPI_CPPC_LIB */
 435
 436 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 437 {
 438         struct cpudata *cpu;
 439         int ret;
 440         int i;
 441
 442         if (hwp_active) {
 443                 intel_pstate_set_itmt_prio(policy->cpu);
 444                 return;
 445         }
 446
 447         if (!intel_pstate_get_ppc_enable_status())
 448                 return;
 449
 450         cpu = all_cpu_data[policy->cpu];
 451
 452         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 453                                                   policy->cpu);
 454         if (ret)
 455                 return;
 456
 457         /*
 458          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 459          * guarantee that the states returned by it map to the states in our
 460          * list directly.
 461          */
 462         if (cpu->acpi_perf_data.control_register.space_id !=
 463                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 464                 goto err;
 465
 466         /*
 467          * If there is only one entry _PSS, simply ignore _PSS and continue as
 468          * usual without taking _PSS into account
 469          */
 470         if (cpu->acpi_perf_data.state_count < 2)
 471                 goto err;
 472
 473         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 474         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 475                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 476                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 477                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 478                          (u32) cpu->acpi_perf_data.states[i].power,
 479                          (u32) cpu->acpi_perf_data.states[i].control);
 480         }
 481
 482         cpu->valid_pss_table = true;
 483         pr_debug("_PPC limits will be enforced\n");
 484
 485         return;
 486
 487  err:
 488         cpu->valid_pss_table = false;
 489         acpi_processor_unregister_performance(policy->cpu);
 490 }
 491
 492 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 493 {
 494         struct cpudata *cpu;
 495
 496         cpu = all_cpu_data[policy->cpu];
 497         if (!cpu->valid_pss_table)
 498                 return;
 499
 500         acpi_processor_unregister_performance(policy->cpu);
 501 }
 502 #else /* CONFIG_ACPI */
 503 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 504 {
 505 }
 506
 507 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 508 {
 509 }
 510
 511 static inline bool intel_pstate_acpi_pm_profile_server(void)
 512 {
 513         return false;
 514 }
 515 #endif /* CONFIG_ACPI */
 516
 517 #ifndef CONFIG_ACPI_CPPC_LIB
 518 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
 519 {
 520         return -ENOTSUPP;
 521 }
 522
 523 static int intel_pstate_cppc_get_scaling(int cpu)
 524 {
 525         return core_get_scaling();
 526 }
 527 #endif /* CONFIG_ACPI_CPPC_LIB */
 528
 529 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
 530                                         unsigned int relation)
 531 {
 532         if (freq == cpu->pstate.turbo_freq)
 533                 return cpu->pstate.turbo_pstate;
 534
 535         if (freq == cpu->pstate.max_freq)
 536                 return cpu->pstate.max_pstate;
 537
 538         switch (relation) {
 539         case CPUFREQ_RELATION_H:
 540                 return freq / cpu->pstate.scaling;
 541         case CPUFREQ_RELATION_C:
 542                 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
 543         }
 544
 545         return DIV_ROUND_UP(freq, cpu->pstate.scaling);
 546 }
 547
 548 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
 549 {
 550         return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
 551 }
 552
 553 /**
 554  * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
 555  * @cpu: Target CPU.
 556  *
 557  * On hybrid processors, HWP may expose more performance levels than there are
 558  * P-states accessible through the PERF_CTL interface.  If that happens, the
 559  * scaling factor between HWP performance levels and CPU frequency will be less
 560  * than the scaling factor between P-state values and CPU frequency.
 561  *
 562  * In that case, adjust the CPU parameters used in computations accordingly.
 563  */
 564 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
 565 {
 566         int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
 567         int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
 568         int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
 569         int scaling = cpu->pstate.scaling;
 570         int freq;
 571
 572         pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
 573         pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
 574         pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
 575         pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
 576         pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
 577         pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
 578
 579         cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
 580                                            perf_ctl_scaling);
 581         cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
 582                                          perf_ctl_scaling);
 583
 584         freq = perf_ctl_max_phys * perf_ctl_scaling;
 585         cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
 586
 587         freq = cpu->pstate.min_pstate * perf_ctl_scaling;
 588         cpu->pstate.min_freq = freq;
 589         /*
 590          * Cast the min P-state value retrieved via pstate_funcs.get_min() to
 591          * the effective range of HWP performance levels.
 592          */
 593         cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
 594 }
 595
 596 static inline void update_turbo_state(void)
 597 {
 598         u64 misc_en;
 599
 600         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 601         global.turbo_disabled = misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
 602 }
 603
 604 static int min_perf_pct_min(void)
 605 {
 606         struct cpudata *cpu = all_cpu_data[0];
 607         int turbo_pstate = cpu->pstate.turbo_pstate;
 608
 609         return turbo_pstate ?
 610                 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
 611 }
 612
 613 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 614 {
 615         u64 epb;
 616         int ret;
 617
 618         if (!boot_cpu_has(X86_FEATURE_EPB))
 619                 return -ENXIO;
 620
 621         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 622         if (ret)
 623                 return (s16)ret;
 624
 625         return (s16)(epb & 0x0f);
 626 }
 627
 628 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 629 {
 630         s16 epp;
 631
 632         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 633                 /*
 634                  * When hwp_req_data is 0, means that caller didn't read
 635                  * MSR_HWP_REQUEST, so need to read and get EPP.
 636                  */
 637                 if (!hwp_req_data) {
 638                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 639                                             &hwp_req_data);
 640                         if (epp)
 641                                 return epp;
 642                 }
 643                 epp = (hwp_req_data >> 24) & 0xff;
 644         } else {
 645                 /* When there is no EPP present, HWP uses EPB settings */
 646                 epp = intel_pstate_get_epb(cpu_data);
 647         }
 648
 649         return epp;
 650 }
 651
 652 static int intel_pstate_set_epb(int cpu, s16 pref)
 653 {
 654         u64 epb;
 655         int ret;
 656
 657         if (!boot_cpu_has(X86_FEATURE_EPB))
 658                 return -ENXIO;
 659
 660         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 661         if (ret)
 662                 return ret;
 663
 664         epb = (epb & ~0x0f) | pref;
 665         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 666
 667         return 0;
 668 }
 669
 670 /*
 671  * EPP/EPB display strings corresponding to EPP index in the
 672  * energy_perf_strings[]
 673  *      index           String
 674  *-------------------------------------
 675  *      0               default
 676  *      1               performance
 677  *      2               balance_performance
 678  *      3               balance_power
 679  *      4               power
 680  */
 681
 682 enum energy_perf_value_index {
 683         EPP_INDEX_DEFAULT = 0,
 684         EPP_INDEX_PERFORMANCE,
 685         EPP_INDEX_BALANCE_PERFORMANCE,
 686         EPP_INDEX_BALANCE_POWERSAVE,
 687         EPP_INDEX_POWERSAVE,
 688 };
 689
 690 static const char * const energy_perf_strings[] = {
 691         [EPP_INDEX_DEFAULT] = "default",
 692         [EPP_INDEX_PERFORMANCE] = "performance",
 693         [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
 694         [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
 695         [EPP_INDEX_POWERSAVE] = "power",
 696         NULL
 697 };
 698 static unsigned int epp_values[] = {
 699         [EPP_INDEX_DEFAULT] = 0, /* Unused index */
 700         [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
 701         [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
 702         [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
 703         [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
 704 };
 705
 706 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
 707 {
 708         s16 epp;
 709         int index = -EINVAL;
 710
 711         *raw_epp = 0;
 712         epp = intel_pstate_get_epp(cpu_data, 0);
 713         if (epp < 0)
 714                 return epp;
 715
 716         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 717                 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
 718                         return EPP_INDEX_PERFORMANCE;
 719                 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
 720                         return EPP_INDEX_BALANCE_PERFORMANCE;
 721                 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
 722                         return EPP_INDEX_BALANCE_POWERSAVE;
 723                 if (epp == epp_values[EPP_INDEX_POWERSAVE])
 724                         return EPP_INDEX_POWERSAVE;
 725                 *raw_epp = epp;
 726                 return 0;
 727         } else if (boot_cpu_has(X86_FEATURE_EPB)) {
 728                 /*
 729                  * Range:
 730                  *      0x00-0x03       :       Performance
 731                  *      0x04-0x07       :       Balance performance
 732                  *      0x08-0x0B       :       Balance power
 733                  *      0x0C-0x0F       :       Power
 734                  * The EPB is a 4 bit value, but our ranges restrict the
 735                  * value which can be set. Here only using top two bits
 736                  * effectively.
 737                  */
 738                 index = (epp >> 2) + 1;
 739         }
 740
 741         return index;
 742 }
 743
 744 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
 745 {
 746         int ret;
 747
 748         /*
 749          * Use the cached HWP Request MSR value, because in the active mode the
 750          * register itself may be updated by intel_pstate_hwp_boost_up() or
 751          * intel_pstate_hwp_boost_down() at any time.
 752          */
 753         u64 value = READ_ONCE(cpu->hwp_req_cached);
 754
 755         value &= ~GENMASK_ULL(31, 24);
 756         value |= (u64)epp << 24;
 757         /*
 758          * The only other updater of hwp_req_cached in the active mode,
 759          * intel_pstate_hwp_set(), is called under the same lock as this
 760          * function, so it cannot run in parallel with the update below.
 761          */
 762         WRITE_ONCE(cpu->hwp_req_cached, value);
 763         ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
 764         if (!ret)
 765                 cpu->epp_cached = epp;
 766
 767         return ret;
 768 }
 769
 770 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 771                                               int pref_index, bool use_raw,
 772                                               u32 raw_epp)
 773 {
 774         int epp = -EINVAL;
 775         int ret;
 776
 777         if (!pref_index)
 778                 epp = cpu_data->epp_default;
 779
 780         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 781                 if (use_raw)
 782                         epp = raw_epp;
 783                 else if (epp == -EINVAL)
 784                         epp = epp_values[pref_index];
 785
 786                 /*
 787                  * To avoid confusion, refuse to set EPP to any values different
 788                  * from 0 (performance) if the current policy is "performance",
 789                  * because those values would be overridden.
 790                  */
 791                 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 792                         return -EBUSY;
 793
 794                 ret = intel_pstate_set_epp(cpu_data, epp);
 795         } else {
 796                 if (epp == -EINVAL)
 797                         epp = (pref_index - 1) << 2;
 798                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 799         }
 800
 801         return ret;
 802 }
 803
 804 static ssize_t show_energy_performance_available_preferences(
 805                                 struct cpufreq_policy *policy, char *buf)
 806 {
 807         int i = 0;
 808         int ret = 0;
 809
 810         while (energy_perf_strings[i] != NULL)
 811                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 812
 813         ret += sprintf(&buf[ret], "\n");
 814
 815         return ret;
 816 }
 817
 818 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 819
 820 static struct cpufreq_driver intel_pstate;
 821
 822 static ssize_t store_energy_performance_preference(
 823                 struct cpufreq_policy *policy, const char *buf, size_t count)
 824 {
 825         struct cpudata *cpu = all_cpu_data[policy->cpu];
 826         char str_preference[21];
 827         bool raw = false;
 828         ssize_t ret;
 829         u32 epp = 0;
 830
 831         ret = sscanf(buf, "%20s", str_preference);
 832         if (ret != 1)
 833                 return -EINVAL;
 834
 835         ret = match_string(energy_perf_strings, -1, str_preference);
 836         if (ret < 0) {
 837                 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
 838                         return ret;
 839
 840                 ret = kstrtouint(buf, 10, &epp);
 841                 if (ret)
 842                         return ret;
 843
 844                 if (epp > 255)
 845                         return -EINVAL;
 846
 847                 raw = true;
 848         }
 849
 850         /*
 851          * This function runs with the policy R/W semaphore held, which
 852          * guarantees that the driver pointer will not change while it is
 853          * running.
 854          */
 855         if (!intel_pstate_driver)
 856                 return -EAGAIN;
 857
 858         mutex_lock(&intel_pstate_limits_lock);
 859
 860         if (intel_pstate_driver == &intel_pstate) {
 861                 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
 862         } else {
 863                 /*
 864                  * In the passive mode the governor needs to be stopped on the
 865                  * target CPU before the EPP update and restarted after it,
 866                  * which is super-heavy-weight, so make sure it is worth doing
 867                  * upfront.
 868                  */
 869                 if (!raw)
 870                         epp = ret ? epp_values[ret] : cpu->epp_default;
 871
 872                 if (cpu->epp_cached != epp) {
 873                         int err;
 874
 875                         cpufreq_stop_governor(policy);
 876                         ret = intel_pstate_set_epp(cpu, epp);
 877                         err = cpufreq_start_governor(policy);
 878                         if (!ret)
 879                                 ret = err;
 880                 } else {
 881                         ret = 0;
 882                 }
 883         }
 884
 885         mutex_unlock(&intel_pstate_limits_lock);
 886
 887         return ret ?: count;
 888 }
 889
 890 static ssize_t show_energy_performance_preference(
 891                                 struct cpufreq_policy *policy, char *buf)
 892 {
 893         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 894         int preference, raw_epp;
 895
 896         preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
 897         if (preference < 0)
 898                 return preference;
 899
 900         if (raw_epp)
 901                 return  sprintf(buf, "%d\n", raw_epp);
 902         else
 903                 return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 904 }
 905
 906 cpufreq_freq_attr_rw(energy_performance_preference);
 907
 908 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
 909 {
 910         struct cpudata *cpu = all_cpu_data[policy->cpu];
 911         int ratio, freq;
 912
 913         ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
 914         if (ratio <= 0) {
 915                 u64 cap;
 916
 917                 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
 918                 ratio = HWP_GUARANTEED_PERF(cap);
 919         }
 920
 921         freq = ratio * cpu->pstate.scaling;
 922         if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
 923                 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
 924
 925         return sprintf(buf, "%d\n", freq);
 926 }
 927
 928 cpufreq_freq_attr_ro(base_frequency);
 929
 930 static struct freq_attr *hwp_cpufreq_attrs[] = {
 931         &energy_performance_preference,
 932         &energy_performance_available_preferences,
 933         &base_frequency,
 934         NULL,
 935 };
 936
 937 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
 938 {
 939         u64 cap;
 940
 941         rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
 942         WRITE_ONCE(cpu->hwp_cap_cached, cap);
 943         cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
 944         cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
 945 }
 946
 947 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
 948 {
 949         int scaling = cpu->pstate.scaling;
 950
 951         __intel_pstate_get_hwp_cap(cpu);
 952
 953         cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
 954         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
 955         if (scaling != cpu->pstate.perf_ctl_scaling) {
 956                 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
 957
 958                 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
 959                                                  perf_ctl_scaling);
 960                 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
 961                                                    perf_ctl_scaling);
 962         }
 963 }
 964
 965 static void intel_pstate_hwp_set(unsigned int cpu)
 966 {
 967         struct cpudata *cpu_data = all_cpu_data[cpu];
 968         int max, min;
 969         u64 value;
 970         s16 epp;
 971
 972         max = cpu_data->max_perf_ratio;
 973         min = cpu_data->min_perf_ratio;
 974
 975         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 976                 min = max;
 977
 978         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 979
 980         value &= ~HWP_MIN_PERF(~0L);
 981         value |= HWP_MIN_PERF(min);
 982
 983         value &= ~HWP_MAX_PERF(~0L);
 984         value |= HWP_MAX_PERF(max);
 985
 986         if (cpu_data->epp_policy == cpu_data->policy)
 987                 goto skip_epp;
 988
 989         cpu_data->epp_policy = cpu_data->policy;
 990
 991         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 992                 epp = intel_pstate_get_epp(cpu_data, value);
 993                 cpu_data->epp_powersave = epp;
 994                 /* If EPP read was failed, then don't try to write */
 995                 if (epp < 0)
 996                         goto skip_epp;
 997
 998                 epp = 0;
 999         } else {
1000                 /* skip setting EPP, when saved value is invalid */
1001                 if (cpu_data->epp_powersave < 0)
1002                         goto skip_epp;
1003
1004                 /*
1005                  * No need to restore EPP when it is not zero. This
1006                  * means:
1007                  *  - Policy is not changed
1008                  *  - user has manually changed
1009                  *  - Error reading EPB
1010                  */
1011                 epp = intel_pstate_get_epp(cpu_data, value);
1012                 if (epp)
1013                         goto skip_epp;
1014
1015                 epp = cpu_data->epp_powersave;
1016         }
1017         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1018                 value &= ~GENMASK_ULL(31, 24);
1019                 value |= (u64)epp << 24;
1020         } else {
1021                 intel_pstate_set_epb(cpu, epp);
1022         }
1023 skip_epp:
1024         WRITE_ONCE(cpu_data->hwp_req_cached, value);
1025         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1026 }
1027
1028 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1029
1030 static void intel_pstate_hwp_offline(struct cpudata *cpu)
1031 {
1032         u64 value = READ_ONCE(cpu->hwp_req_cached);
1033         int min_perf;
1034
1035         intel_pstate_disable_hwp_interrupt(cpu);
1036
1037         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1038                 /*
1039                  * In case the EPP has been set to "performance" by the
1040                  * active mode "performance" scaling algorithm, replace that
1041                  * temporary value with the cached EPP one.
1042                  */
1043                 value &= ~GENMASK_ULL(31, 24);
1044                 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1045                 /*
1046                  * However, make sure that EPP will be set to "performance" when
1047                  * the CPU is brought back online again and the "performance"
1048                  * scaling algorithm is still in effect.
1049                  */
1050                 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1051         }
1052
1053         /*
1054          * Clear the desired perf field in the cached HWP request value to
1055          * prevent nonzero desired values from being leaked into the active
1056          * mode.
1057          */
1058         value &= ~HWP_DESIRED_PERF(~0L);
1059         WRITE_ONCE(cpu->hwp_req_cached, value);
1060
1061         value &= ~GENMASK_ULL(31, 0);
1062         min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1063
1064         /* Set hwp_max = hwp_min */
1065         value |= HWP_MAX_PERF(min_perf);
1066         value |= HWP_MIN_PERF(min_perf);
1067
1068         /* Set EPP to min */
1069         if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1070                 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1071
1072         wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1073 }
1074
1075 #define POWER_CTL_EE_ENABLE     1
1076 #define POWER_CTL_EE_DISABLE    2
1077
1078 static int power_ctl_ee_state;
1079
1080 static void set_power_ctl_ee_state(bool input)
1081 {
1082         u64 power_ctl;
1083
1084         mutex_lock(&intel_pstate_driver_lock);
1085         rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1086         if (input) {
1087                 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1088                 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1089         } else {
1090                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1091                 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1092         }
1093         wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1094         mutex_unlock(&intel_pstate_driver_lock);
1095 }
1096
1097 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1098
1099 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1100 {
1101         intel_pstate_hwp_enable(cpu);
1102         wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1103 }
1104
1105 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1106 {
1107         struct cpudata *cpu = all_cpu_data[policy->cpu];
1108
1109         pr_debug("CPU %d suspending\n", cpu->cpu);
1110
1111         cpu->suspended = true;
1112
1113         /* disable HWP interrupt and cancel any pending work */
1114         intel_pstate_disable_hwp_interrupt(cpu);
1115
1116         return 0;
1117 }
1118
1119 static int intel_pstate_resume(struct cpufreq_policy *policy)
1120 {
1121         struct cpudata *cpu = all_cpu_data[policy->cpu];
1122
1123         pr_debug("CPU %d resuming\n", cpu->cpu);
1124
1125         /* Only restore if the system default is changed */
1126         if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1127                 set_power_ctl_ee_state(true);
1128         else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1129                 set_power_ctl_ee_state(false);
1130
1131         if (cpu->suspended && hwp_active) {
1132                 mutex_lock(&intel_pstate_limits_lock);
1133
1134                 /* Re-enable HWP, because "online" has not done that. */
1135                 intel_pstate_hwp_reenable(cpu);
1136
1137                 mutex_unlock(&intel_pstate_limits_lock);
1138         }
1139
1140         cpu->suspended = false;
1141
1142         return 0;
1143 }
1144
1145 static void intel_pstate_update_policies(void)
1146 {
1147         int cpu;
1148
1149         for_each_possible_cpu(cpu)
1150                 cpufreq_update_policy(cpu);
1151 }
1152
1153 static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1154                                            struct cpufreq_policy *policy)
1155 {
1156         policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1157                         cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1158         refresh_frequency_limits(policy);
1159 }
1160
1161 static void intel_pstate_update_max_freq(unsigned int cpu)
1162 {
1163         struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1164
1165         if (!policy)
1166                 return;
1167
1168         __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1169
1170         cpufreq_cpu_release(policy);
1171 }
1172
1173 static void intel_pstate_update_limits(unsigned int cpu)
1174 {
1175         mutex_lock(&intel_pstate_driver_lock);
1176
1177         update_turbo_state();
1178         /*
1179          * If turbo has been turned on or off globally, policy limits for
1180          * all CPUs need to be updated to reflect that.
1181          */
1182         if (global.turbo_disabled_mf != global.turbo_disabled) {
1183                 global.turbo_disabled_mf = global.turbo_disabled;
1184                 arch_set_max_freq_ratio(global.turbo_disabled);
1185                 for_each_possible_cpu(cpu)
1186                         intel_pstate_update_max_freq(cpu);
1187         } else {
1188                 cpufreq_update_policy(cpu);
1189         }
1190
1191         mutex_unlock(&intel_pstate_driver_lock);
1192 }
1193
1194 /************************** sysfs begin ************************/
1195 #define show_one(file_name, object)                                     \
1196         static ssize_t show_##file_name                                 \
1197         (struct kobject *kobj, struct kobj_attribute *attr, char *buf)  \
1198         {                                                               \
1199                 return sprintf(buf, "%u\n", global.object);             \
1200         }
1201
1202 static ssize_t intel_pstate_show_status(char *buf);
1203 static int intel_pstate_update_status(const char *buf, size_t size);
1204
1205 static ssize_t show_status(struct kobject *kobj,
1206                            struct kobj_attribute *attr, char *buf)
1207 {
1208         ssize_t ret;
1209
1210         mutex_lock(&intel_pstate_driver_lock);
1211         ret = intel_pstate_show_status(buf);
1212         mutex_unlock(&intel_pstate_driver_lock);
1213
1214         return ret;
1215 }
1216
1217 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1218                             const char *buf, size_t count)
1219 {
1220         char *p = memchr(buf, '\n', count);
1221         int ret;
1222
1223         mutex_lock(&intel_pstate_driver_lock);
1224         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1225         mutex_unlock(&intel_pstate_driver_lock);
1226
1227         return ret < 0 ? ret : count;
1228 }
1229
1230 static ssize_t show_turbo_pct(struct kobject *kobj,
1231                                 struct kobj_attribute *attr, char *buf)
1232 {
1233         struct cpudata *cpu;
1234         int total, no_turbo, turbo_pct;
1235         uint32_t turbo_fp;
1236
1237         mutex_lock(&intel_pstate_driver_lock);
1238
1239         if (!intel_pstate_driver) {
1240                 mutex_unlock(&intel_pstate_driver_lock);
1241                 return -EAGAIN;
1242         }
1243
1244         cpu = all_cpu_data[0];
1245
1246         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1247         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1248         turbo_fp = div_fp(no_turbo, total);
1249         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1250
1251         mutex_unlock(&intel_pstate_driver_lock);
1252
1253         return sprintf(buf, "%u\n", turbo_pct);
1254 }
1255
1256 static ssize_t show_num_pstates(struct kobject *kobj,
1257                                 struct kobj_attribute *attr, char *buf)
1258 {
1259         struct cpudata *cpu;
1260         int total;
1261
1262         mutex_lock(&intel_pstate_driver_lock);
1263
1264         if (!intel_pstate_driver) {
1265                 mutex_unlock(&intel_pstate_driver_lock);
1266                 return -EAGAIN;
1267         }
1268
1269         cpu = all_cpu_data[0];
1270         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1271
1272         mutex_unlock(&intel_pstate_driver_lock);
1273
1274         return sprintf(buf, "%u\n", total);
1275 }
1276
1277 static ssize_t show_no_turbo(struct kobject *kobj,
1278                              struct kobj_attribute *attr, char *buf)
1279 {
1280         ssize_t ret;
1281
1282         mutex_lock(&intel_pstate_driver_lock);
1283
1284         if (!intel_pstate_driver) {
1285                 mutex_unlock(&intel_pstate_driver_lock);
1286                 return -EAGAIN;
1287         }
1288
1289         update_turbo_state();
1290         if (global.turbo_disabled)
1291                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1292         else
1293                 ret = sprintf(buf, "%u\n", global.no_turbo);
1294
1295         mutex_unlock(&intel_pstate_driver_lock);
1296
1297         return ret;
1298 }
1299
1300 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1301                               const char *buf, size_t count)
1302 {
1303         unsigned int input;
1304         int ret;
1305
1306         ret = sscanf(buf, "%u", &input);
1307         if (ret != 1)
1308                 return -EINVAL;
1309
1310         mutex_lock(&intel_pstate_driver_lock);
1311
1312         if (!intel_pstate_driver) {
1313                 mutex_unlock(&intel_pstate_driver_lock);
1314                 return -EAGAIN;
1315         }
1316
1317         mutex_lock(&intel_pstate_limits_lock);
1318
1319         update_turbo_state();
1320         if (global.turbo_disabled) {
1321                 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1322                 mutex_unlock(&intel_pstate_limits_lock);
1323                 mutex_unlock(&intel_pstate_driver_lock);
1324                 return -EPERM;
1325         }
1326
1327         global.no_turbo = clamp_t(int, input, 0, 1);
1328
1329         if (global.no_turbo) {
1330                 struct cpudata *cpu = all_cpu_data[0];
1331                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1332
1333                 /* Squash the global minimum into the permitted range. */
1334                 if (global.min_perf_pct > pct)
1335                         global.min_perf_pct = pct;
1336         }
1337
1338         mutex_unlock(&intel_pstate_limits_lock);
1339
1340         intel_pstate_update_policies();
1341         arch_set_max_freq_ratio(global.no_turbo);
1342
1343         mutex_unlock(&intel_pstate_driver_lock);
1344
1345         return count;
1346 }
1347
1348 static void update_qos_request(enum freq_qos_req_type type)
1349 {
1350         struct freq_qos_request *req;
1351         struct cpufreq_policy *policy;
1352         int i;
1353
1354         for_each_possible_cpu(i) {
1355                 struct cpudata *cpu = all_cpu_data[i];
1356                 unsigned int freq, perf_pct;
1357
1358                 policy = cpufreq_cpu_get(i);
1359                 if (!policy)
1360                         continue;
1361
1362                 req = policy->driver_data;
1363                 cpufreq_cpu_put(policy);
1364
1365                 if (!req)
1366                         continue;
1367
1368                 if (hwp_active)
1369                         intel_pstate_get_hwp_cap(cpu);
1370
1371                 if (type == FREQ_QOS_MIN) {
1372                         perf_pct = global.min_perf_pct;
1373                 } else {
1374                         req++;
1375                         perf_pct = global.max_perf_pct;
1376                 }
1377
1378                 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1379
1380                 if (freq_qos_update_request(req, freq) < 0)
1381                         pr_warn("Failed to update freq constraint: CPU%d\n", i);
1382         }
1383 }
1384
1385 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1386                                   const char *buf, size_t count)
1387 {
1388         unsigned int input;
1389         int ret;
1390
1391         ret = sscanf(buf, "%u", &input);
1392         if (ret != 1)
1393                 return -EINVAL;
1394
1395         mutex_lock(&intel_pstate_driver_lock);
1396
1397         if (!intel_pstate_driver) {
1398                 mutex_unlock(&intel_pstate_driver_lock);
1399                 return -EAGAIN;
1400         }
1401
1402         mutex_lock(&intel_pstate_limits_lock);
1403
1404         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1405
1406         mutex_unlock(&intel_pstate_limits_lock);
1407
1408         if (intel_pstate_driver == &intel_pstate)
1409                 intel_pstate_update_policies();
1410         else
1411                 update_qos_request(FREQ_QOS_MAX);
1412
1413         mutex_unlock(&intel_pstate_driver_lock);
1414
1415         return count;
1416 }
1417
1418 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1419                                   const char *buf, size_t count)
1420 {
1421         unsigned int input;
1422         int ret;
1423
1424         ret = sscanf(buf, "%u", &input);
1425         if (ret != 1)
1426                 return -EINVAL;
1427
1428         mutex_lock(&intel_pstate_driver_lock);
1429
1430         if (!intel_pstate_driver) {
1431                 mutex_unlock(&intel_pstate_driver_lock);
1432                 return -EAGAIN;
1433         }
1434
1435         mutex_lock(&intel_pstate_limits_lock);
1436
1437         global.min_perf_pct = clamp_t(int, input,
1438                                       min_perf_pct_min(), global.max_perf_pct);
1439
1440         mutex_unlock(&intel_pstate_limits_lock);
1441
1442         if (intel_pstate_driver == &intel_pstate)
1443                 intel_pstate_update_policies();
1444         else
1445                 update_qos_request(FREQ_QOS_MIN);
1446
1447         mutex_unlock(&intel_pstate_driver_lock);
1448
1449         return count;
1450 }
1451
1452 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1453                                 struct kobj_attribute *attr, char *buf)
1454 {
1455         return sprintf(buf, "%u\n", hwp_boost);
1456 }
1457
1458 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1459                                        struct kobj_attribute *b,
1460                                        const char *buf, size_t count)
1461 {
1462         unsigned int input;
1463         int ret;
1464
1465         ret = kstrtouint(buf, 10, &input);
1466         if (ret)
1467                 return ret;
1468
1469         mutex_lock(&intel_pstate_driver_lock);
1470         hwp_boost = !!input;
1471         intel_pstate_update_policies();
1472         mutex_unlock(&intel_pstate_driver_lock);
1473
1474         return count;
1475 }
1476
1477 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1478                                       char *buf)
1479 {
1480         u64 power_ctl;
1481         int enable;
1482
1483         rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1484         enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1485         return sprintf(buf, "%d\n", !enable);
1486 }
1487
1488 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1489                                        const char *buf, size_t count)
1490 {
1491         bool input;
1492         int ret;
1493
1494         ret = kstrtobool(buf, &input);
1495         if (ret)
1496                 return ret;
1497
1498         set_power_ctl_ee_state(input);
1499
1500         return count;
1501 }
1502
1503 show_one(max_perf_pct, max_perf_pct);
1504 show_one(min_perf_pct, min_perf_pct);
1505
1506 define_one_global_rw(status);
1507 define_one_global_rw(no_turbo);
1508 define_one_global_rw(max_perf_pct);
1509 define_one_global_rw(min_perf_pct);
1510 define_one_global_ro(turbo_pct);
1511 define_one_global_ro(num_pstates);
1512 define_one_global_rw(hwp_dynamic_boost);
1513 define_one_global_rw(energy_efficiency);
1514
1515 static struct attribute *intel_pstate_attributes[] = {
1516         &status.attr,
1517         &no_turbo.attr,
1518         NULL
1519 };
1520
1521 static const struct attribute_group intel_pstate_attr_group = {
1522         .attrs = intel_pstate_attributes,
1523 };
1524
1525 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1526
1527 static struct kobject *intel_pstate_kobject;
1528
1529 static void __init intel_pstate_sysfs_expose_params(void)
1530 {
1531         struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1532         int rc;
1533
1534         if (dev_root) {
1535                 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1536                 put_device(dev_root);
1537         }
1538         if (WARN_ON(!intel_pstate_kobject))
1539                 return;
1540
1541         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1542         if (WARN_ON(rc))
1543                 return;
1544
1545         if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1546                 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1547                 WARN_ON(rc);
1548
1549                 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1550                 WARN_ON(rc);
1551         }
1552
1553         /*
1554          * If per cpu limits are enforced there are no global limits, so
1555          * return without creating max/min_perf_pct attributes
1556          */
1557         if (per_cpu_limits)
1558                 return;
1559
1560         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1561         WARN_ON(rc);
1562
1563         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1564         WARN_ON(rc);
1565
1566         if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1567                 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1568                 WARN_ON(rc);
1569         }
1570 }
1571
1572 static void __init intel_pstate_sysfs_remove(void)
1573 {
1574         if (!intel_pstate_kobject)
1575                 return;
1576
1577         sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1578
1579         if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1580                 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1581                 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1582         }
1583
1584         if (!per_cpu_limits) {
1585                 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1586                 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1587
1588                 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1589                         sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1590         }
1591
1592         kobject_put(intel_pstate_kobject);
1593 }
1594
1595 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1596 {
1597         int rc;
1598
1599         if (!hwp_active)
1600                 return;
1601
1602         rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1603         WARN_ON_ONCE(rc);
1604 }
1605
1606 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1607 {
1608         if (!hwp_active)
1609                 return;
1610
1611         sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1612 }
1613
1614 /************************** sysfs end ************************/
1615
1616 static void intel_pstate_notify_work(struct work_struct *work)
1617 {
1618         struct cpudata *cpudata =
1619                 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1620         struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1621
1622         if (policy) {
1623                 intel_pstate_get_hwp_cap(cpudata);
1624                 __intel_pstate_update_max_freq(cpudata, policy);
1625
1626                 cpufreq_cpu_release(policy);
1627         }
1628
1629         wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1630 }
1631
1632 static DEFINE_SPINLOCK(hwp_notify_lock);
1633 static cpumask_t hwp_intr_enable_mask;
1634
1635 void notify_hwp_interrupt(void)
1636 {
1637         unsigned int this_cpu = smp_processor_id();
1638         struct cpudata *cpudata;
1639         unsigned long flags;
1640         u64 value;
1641
1642         if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1643                 return;
1644
1645         rdmsrl_safe(MSR_HWP_STATUS, &value);
1646         if (!(value & 0x01))
1647                 return;
1648
1649         spin_lock_irqsave(&hwp_notify_lock, flags);
1650
1651         if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1652                 goto ack_intr;
1653
1654         /*
1655          * Currently we never free all_cpu_data. And we can't reach here
1656          * without this allocated. But for safety for future changes, added
1657          * check.
1658          */
1659         if (unlikely(!READ_ONCE(all_cpu_data)))
1660                 goto ack_intr;
1661
1662         /*
1663          * The free is done during cleanup, when cpufreq registry is failed.
1664          * We wouldn't be here if it fails on init or switch status. But for
1665          * future changes, added check.
1666          */
1667         cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1668         if (unlikely(!cpudata))
1669                 goto ack_intr;
1670
1671         schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1672
1673         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1674
1675         return;
1676
1677 ack_intr:
1678         wrmsrl_safe(MSR_HWP_STATUS, 0);
1679         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1680 }
1681
1682 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1683 {
1684         unsigned long flags;
1685
1686         if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1687                 return;
1688
1689         /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1690         wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1691
1692         spin_lock_irqsave(&hwp_notify_lock, flags);
1693         if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1694                 cancel_delayed_work(&cpudata->hwp_notify_work);
1695         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1696 }
1697
1698 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1699 {
1700         /* Enable HWP notification interrupt for guaranteed performance change */
1701         if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1702                 unsigned long flags;
1703
1704                 spin_lock_irqsave(&hwp_notify_lock, flags);
1705                 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1706                 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1707                 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1708
1709                 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1710                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1711                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1712         }
1713 }
1714
1715 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1716 {
1717         cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1718
1719         /*
1720          * If this CPU gen doesn't call for change in balance_perf
1721          * EPP return.
1722          */
1723         if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1724                 return;
1725
1726         /*
1727          * If the EPP is set by firmware, which means that firmware enabled HWP
1728          * - Is equal or less than 0x80 (default balance_perf EPP)
1729          * - But less performance oriented than performance EPP
1730          *   then use this as new balance_perf EPP.
1731          */
1732         if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1733             cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1734                 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1735                 return;
1736         }
1737
1738         /*
1739          * Use hard coded value per gen to update the balance_perf
1740          * and default EPP.
1741          */
1742         cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1743         intel_pstate_set_epp(cpudata, cpudata->epp_default);
1744 }
1745
1746 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1747 {
1748         /* First disable HWP notification interrupt till we activate again */
1749         if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1750                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1751
1752         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1753
1754         intel_pstate_enable_hwp_interrupt(cpudata);
1755
1756         if (cpudata->epp_default >= 0)
1757                 return;
1758
1759         intel_pstate_update_epp_defaults(cpudata);
1760 }
1761
1762 static int atom_get_min_pstate(int not_used)
1763 {
1764         u64 value;
1765
1766         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1767         return (value >> 8) & 0x7F;
1768 }
1769
1770 static int atom_get_max_pstate(int not_used)
1771 {
1772         u64 value;
1773
1774         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1775         return (value >> 16) & 0x7F;
1776 }
1777
1778 static int atom_get_turbo_pstate(int not_used)
1779 {
1780         u64 value;
1781
1782         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1783         return value & 0x7F;
1784 }
1785
1786 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1787 {
1788         u64 val;
1789         int32_t vid_fp;
1790         u32 vid;
1791
1792         val = (u64)pstate << 8;
1793         if (global.no_turbo && !global.turbo_disabled)
1794                 val |= (u64)1 << 32;
1795
1796         vid_fp = cpudata->vid.min + mul_fp(
1797                 int_tofp(pstate - cpudata->pstate.min_pstate),
1798                 cpudata->vid.ratio);
1799
1800         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1801         vid = ceiling_fp(vid_fp);
1802
1803         if (pstate > cpudata->pstate.max_pstate)
1804                 vid = cpudata->vid.turbo;
1805
1806         return val | vid;
1807 }
1808
1809 static int silvermont_get_scaling(void)
1810 {
1811         u64 value;
1812         int i;
1813         /* Defined in Table 35-6 from SDM (Sept 2015) */
1814         static int silvermont_freq_table[] = {
1815                 83300, 100000, 133300, 116700, 80000};
1816
1817         rdmsrl(MSR_FSB_FREQ, value);
1818         i = value & 0x7;
1819         WARN_ON(i > 4);
1820
1821         return silvermont_freq_table[i];
1822 }
1823
1824 static int airmont_get_scaling(void)
1825 {
1826         u64 value;
1827         int i;
1828         /* Defined in Table 35-10 from SDM (Sept 2015) */
1829         static int airmont_freq_table[] = {
1830                 83300, 100000, 133300, 116700, 80000,
1831                 93300, 90000, 88900, 87500};
1832
1833         rdmsrl(MSR_FSB_FREQ, value);
1834         i = value & 0xF;
1835         WARN_ON(i > 8);
1836
1837         return airmont_freq_table[i];
1838 }
1839
1840 static void atom_get_vid(struct cpudata *cpudata)
1841 {
1842         u64 value;
1843
1844         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1845         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1846         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1847         cpudata->vid.ratio = div_fp(
1848                 cpudata->vid.max - cpudata->vid.min,
1849                 int_tofp(cpudata->pstate.max_pstate -
1850                         cpudata->pstate.min_pstate));
1851
1852         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1853         cpudata->vid.turbo = value & 0x7f;
1854 }
1855
1856 static int core_get_min_pstate(int cpu)
1857 {
1858         u64 value;
1859
1860         rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1861         return (value >> 40) & 0xFF;
1862 }
1863
1864 static int core_get_max_pstate_physical(int cpu)
1865 {
1866         u64 value;
1867
1868         rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1869         return (value >> 8) & 0xFF;
1870 }
1871
1872 static int core_get_tdp_ratio(int cpu, u64 plat_info)
1873 {
1874         /* Check how many TDP levels present */
1875         if (plat_info & 0x600000000) {
1876                 u64 tdp_ctrl;
1877                 u64 tdp_ratio;
1878                 int tdp_msr;
1879                 int err;
1880
1881                 /* Get the TDP level (0, 1, 2) to get ratios */
1882                 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1883                 if (err)
1884                         return err;
1885
1886                 /* TDP MSR are continuous starting at 0x648 */
1887                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1888                 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
1889                 if (err)
1890                         return err;
1891
1892                 /* For level 1 and 2, bits[23:16] contain the ratio */
1893                 if (tdp_ctrl & 0x03)
1894                         tdp_ratio >>= 16;
1895
1896                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1897                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1898
1899                 return (int)tdp_ratio;
1900         }
1901
1902         return -ENXIO;
1903 }
1904
1905 static int core_get_max_pstate(int cpu)
1906 {
1907         u64 tar;
1908         u64 plat_info;
1909         int max_pstate;
1910         int tdp_ratio;
1911         int err;
1912
1913         rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
1914         max_pstate = (plat_info >> 8) & 0xFF;
1915
1916         tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1917         if (tdp_ratio <= 0)
1918                 return max_pstate;
1919
1920         if (hwp_active) {
1921                 /* Turbo activation ratio is not used on HWP platforms */
1922                 return tdp_ratio;
1923         }
1924
1925         err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
1926         if (!err) {
1927                 int tar_levels;
1928
1929                 /* Do some sanity checking for safety */
1930                 tar_levels = tar & 0xff;
1931                 if (tdp_ratio - 1 == tar_levels) {
1932                         max_pstate = tar_levels;
1933                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1934                 }
1935         }
1936
1937         return max_pstate;
1938 }
1939
1940 static int core_get_turbo_pstate(int cpu)
1941 {
1942         u64 value;
1943         int nont, ret;
1944
1945         rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1946         nont = core_get_max_pstate(cpu);
1947         ret = (value) & 255;
1948         if (ret <= nont)
1949                 ret = nont;
1950         return ret;
1951 }
1952
1953 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1954 {
1955         u64 val;
1956
1957         val = (u64)pstate << 8;
1958         if (global.no_turbo && !global.turbo_disabled)
1959                 val |= (u64)1 << 32;
1960
1961         return val;
1962 }
1963
1964 static int knl_get_aperf_mperf_shift(void)
1965 {
1966         return 10;
1967 }
1968
1969 static int knl_get_turbo_pstate(int cpu)
1970 {
1971         u64 value;
1972         int nont, ret;
1973
1974         rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1975         nont = core_get_max_pstate(cpu);
1976         ret = (((value) >> 8) & 0xFF);
1977         if (ret <= nont)
1978                 ret = nont;
1979         return ret;
1980 }
1981
1982 static void hybrid_get_type(void *data)
1983 {
1984         u8 *cpu_type = data;
1985
1986         *cpu_type = get_this_hybrid_cpu_type();
1987 }
1988
1989 static int hwp_get_cpu_scaling(int cpu)
1990 {
1991         u8 cpu_type = 0;
1992
1993         smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1994         /* P-cores have a smaller perf level-to-freqency scaling factor. */
1995         if (cpu_type == 0x40)
1996                 return HYBRID_SCALING_FACTOR;
1997
1998         /* Use default core scaling for E-cores */
1999         if (cpu_type == 0x20)
2000                 return core_get_scaling();
2001
2002         /*
2003          * If reached here, this system is either non-hybrid (like Tiger
2004          * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with
2005          * no E cores (in which case CPUID for hybrid support is 0).
2006          *
2007          * The CPPC nominal_frequency field is 0 for non-hybrid systems,
2008          * so the default core scaling will be used for them.
2009          */
2010         return intel_pstate_cppc_get_scaling(cpu);
2011 }
2012
2013 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2014 {
2015         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2016         cpu->pstate.current_pstate = pstate;
2017         /*
2018          * Generally, there is no guarantee that this code will always run on
2019          * the CPU being updated, so force the register update to run on the
2020          * right CPU.
2021          */
2022         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2023                       pstate_funcs.get_val(cpu, pstate));
2024 }
2025
2026 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2027 {
2028         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2029 }
2030
2031 static void intel_pstate_max_within_limits(struct cpudata *cpu)
2032 {
2033         int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2034
2035         update_turbo_state();
2036         intel_pstate_set_pstate(cpu, pstate);
2037 }
2038
2039 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2040 {
2041         int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2042         int perf_ctl_scaling = pstate_funcs.get_scaling();
2043
2044         cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2045         cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2046         cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2047
2048         if (hwp_active && !hwp_mode_bdw) {
2049                 __intel_pstate_get_hwp_cap(cpu);
2050
2051                 if (pstate_funcs.get_cpu_scaling) {
2052                         cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2053                         if (cpu->pstate.scaling != perf_ctl_scaling)
2054                                 intel_pstate_hybrid_hwp_adjust(cpu);
2055                 } else {
2056                         cpu->pstate.scaling = perf_ctl_scaling;
2057                 }
2058         } else {
2059                 cpu->pstate.scaling = perf_ctl_scaling;
2060                 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2061                 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2062         }
2063
2064         if (cpu->pstate.scaling == perf_ctl_scaling) {
2065                 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2066                 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2067                 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2068         }
2069
2070         if (pstate_funcs.get_aperf_mperf_shift)
2071                 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2072
2073         if (pstate_funcs.get_vid)
2074                 pstate_funcs.get_vid(cpu);
2075
2076         intel_pstate_set_min_pstate(cpu);
2077 }
2078
2079 /*
2080  * Long hold time will keep high perf limits for long time,
2081  * which negatively impacts perf/watt for some workloads,
2082  * like specpower. 3ms is based on experiements on some
2083  * workoads.
2084  */
2085 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2086
2087 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2088 {
2089         u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2090         u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2091         u32 max_limit = (hwp_req & 0xff00) >> 8;
2092         u32 min_limit = (hwp_req & 0xff);
2093         u32 boost_level1;
2094
2095         /*
2096          * Cases to consider (User changes via sysfs or boot time):
2097          * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2098          *      No boost, return.
2099          * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2100          *     Should result in one level boost only for P0.
2101          * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2102          *     Should result in two level boost:
2103          *         (min + p1)/2 and P1.
2104          * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2105          *     Should result in three level boost:
2106          *        (min + p1)/2, P1 and P0.
2107          */
2108
2109         /* If max and min are equal or already at max, nothing to boost */
2110         if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2111                 return;
2112
2113         if (!cpu->hwp_boost_min)
2114                 cpu->hwp_boost_min = min_limit;
2115
2116         /* level at half way mark between min and guranteed */
2117         boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2118
2119         if (cpu->hwp_boost_min < boost_level1)
2120                 cpu->hwp_boost_min = boost_level1;
2121         else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2122                 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2123         else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2124                  max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2125                 cpu->hwp_boost_min = max_limit;
2126         else
2127                 return;
2128
2129         hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2130         wrmsrl(MSR_HWP_REQUEST, hwp_req);
2131         cpu->last_update = cpu->sample.time;
2132 }
2133
2134 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2135 {
2136         if (cpu->hwp_boost_min) {
2137                 bool expired;
2138
2139                 /* Check if we are idle for hold time to boost down */
2140                 expired = time_after64(cpu->sample.time, cpu->last_update +
2141                                        hwp_boost_hold_time_ns);
2142                 if (expired) {
2143                         wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2144                         cpu->hwp_boost_min = 0;
2145                 }
2146         }
2147         cpu->last_update = cpu->sample.time;
2148 }
2149
2150 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2151                                                       u64 time)
2152 {
2153         cpu->sample.time = time;
2154
2155         if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2156                 bool do_io = false;
2157
2158                 cpu->sched_flags = 0;
2159                 /*
2160                  * Set iowait_boost flag and update time. Since IO WAIT flag
2161                  * is set all the time, we can't just conclude that there is
2162                  * some IO bound activity is scheduled on this CPU with just
2163                  * one occurrence. If we receive at least two in two
2164                  * consecutive ticks, then we treat as boost candidate.
2165                  */
2166                 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2167                         do_io = true;
2168
2169                 cpu->last_io_update = time;
2170
2171                 if (do_io)
2172                         intel_pstate_hwp_boost_up(cpu);
2173
2174         } else {
2175                 intel_pstate_hwp_boost_down(cpu);
2176         }
2177 }
2178
2179 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2180                                                 u64 time, unsigned int flags)
2181 {
2182         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2183
2184         cpu->sched_flags |= flags;
2185
2186         if (smp_processor_id() == cpu->cpu)
2187                 intel_pstate_update_util_hwp_local(cpu, time);
2188 }
2189
2190 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2191 {
2192         struct sample *sample = &cpu->sample;
2193
2194         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2195 }
2196
2197 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2198 {
2199         u64 aperf, mperf;
2200         unsigned long flags;
2201         u64 tsc;
2202
2203         local_irq_save(flags);
2204         rdmsrl(MSR_IA32_APERF, aperf);
2205         rdmsrl(MSR_IA32_MPERF, mperf);
2206         tsc = rdtsc();
2207         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2208                 local_irq_restore(flags);
2209                 return false;
2210         }
2211         local_irq_restore(flags);
2212
2213         cpu->last_sample_time = cpu->sample.time;
2214         cpu->sample.time = time;
2215         cpu->sample.aperf = aperf;
2216         cpu->sample.mperf = mperf;
2217         cpu->sample.tsc =  tsc;
2218         cpu->sample.aperf -= cpu->prev_aperf;
2219         cpu->sample.mperf -= cpu->prev_mperf;
2220         cpu->sample.tsc -= cpu->prev_tsc;
2221
2222         cpu->prev_aperf = aperf;
2223         cpu->prev_mperf = mperf;
2224         cpu->prev_tsc = tsc;
2225         /*
2226          * First time this function is invoked in a given cycle, all of the
2227          * previous sample data fields are equal to zero or stale and they must
2228          * be populated with meaningful numbers for things to work, so assume
2229          * that sample.time will always be reset before setting the utilization
2230          * update hook and make the caller skip the sample then.
2231          */
2232         if (cpu->last_sample_time) {
2233                 intel_pstate_calc_avg_perf(cpu);
2234                 return true;
2235         }
2236         return false;
2237 }
2238
2239 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2240 {
2241         return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2242 }
2243
2244 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2245 {
2246         return mul_ext_fp(cpu->pstate.max_pstate_physical,
2247                           cpu->sample.core_avg_perf);
2248 }
2249
2250 static inline int32_t get_target_pstate(struct cpudata *cpu)
2251 {
2252         struct sample *sample = &cpu->sample;
2253         int32_t busy_frac;
2254         int target, avg_pstate;
2255
2256         busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2257                            sample->tsc);
2258
2259         if (busy_frac < cpu->iowait_boost)
2260                 busy_frac = cpu->iowait_boost;
2261
2262         sample->busy_scaled = busy_frac * 100;
2263
2264         target = global.no_turbo || global.turbo_disabled ?
2265                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2266         target += target >> 2;
2267         target = mul_fp(target, busy_frac);
2268         if (target < cpu->pstate.min_pstate)
2269                 target = cpu->pstate.min_pstate;
2270
2271         /*
2272          * If the average P-state during the previous cycle was higher than the
2273          * current target, add 50% of the difference to the target to reduce
2274          * possible performance oscillations and offset possible performance
2275          * loss related to moving the workload from one CPU to another within
2276          * a package/module.
2277          */
2278         avg_pstate = get_avg_pstate(cpu);
2279         if (avg_pstate > target)
2280                 target += (avg_pstate - target) >> 1;
2281
2282         return target;
2283 }
2284
2285 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2286 {
2287         int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2288         int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2289
2290         return clamp_t(int, pstate, min_pstate, max_pstate);
2291 }
2292
2293 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2294 {
2295         if (pstate == cpu->pstate.current_pstate)
2296                 return;
2297
2298         cpu->pstate.current_pstate = pstate;
2299         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2300 }
2301
2302 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2303 {
2304         int from = cpu->pstate.current_pstate;
2305         struct sample *sample;
2306         int target_pstate;
2307
2308         update_turbo_state();
2309
2310         target_pstate = get_target_pstate(cpu);
2311         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2312         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2313         intel_pstate_update_pstate(cpu, target_pstate);
2314
2315         sample = &cpu->sample;
2316         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2317                 fp_toint(sample->busy_scaled),
2318                 from,
2319                 cpu->pstate.current_pstate,
2320                 sample->mperf,
2321                 sample->aperf,
2322                 sample->tsc,
2323                 get_avg_frequency(cpu),
2324                 fp_toint(cpu->iowait_boost * 100));
2325 }
2326
2327 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2328                                      unsigned int flags)
2329 {
2330         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2331         u64 delta_ns;
2332
2333         /* Don't allow remote callbacks */
2334         if (smp_processor_id() != cpu->cpu)
2335                 return;
2336
2337         delta_ns = time - cpu->last_update;
2338         if (flags & SCHED_CPUFREQ_IOWAIT) {
2339                 /* Start over if the CPU may have been idle. */
2340                 if (delta_ns > TICK_NSEC) {
2341                         cpu->iowait_boost = ONE_EIGHTH_FP;
2342                 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2343                         cpu->iowait_boost <<= 1;
2344                         if (cpu->iowait_boost > int_tofp(1))
2345                                 cpu->iowait_boost = int_tofp(1);
2346                 } else {
2347                         cpu->iowait_boost = ONE_EIGHTH_FP;
2348                 }
2349         } else if (cpu->iowait_boost) {
2350                 /* Clear iowait_boost if the CPU may have been idle. */
2351                 if (delta_ns > TICK_NSEC)
2352                         cpu->iowait_boost = 0;
2353                 else
2354                         cpu->iowait_boost >>= 1;
2355         }
2356         cpu->last_update = time;
2357         delta_ns = time - cpu->sample.time;
2358         if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2359                 return;
2360
2361         if (intel_pstate_sample(cpu, time))
2362                 intel_pstate_adjust_pstate(cpu);
2363 }
2364
2365 static struct pstate_funcs core_funcs = {
2366         .get_max = core_get_max_pstate,
2367         .get_max_physical = core_get_max_pstate_physical,
2368         .get_min = core_get_min_pstate,
2369         .get_turbo = core_get_turbo_pstate,
2370         .get_scaling = core_get_scaling,
2371         .get_val = core_get_val,
2372 };
2373
2374 static const struct pstate_funcs silvermont_funcs = {
2375         .get_max = atom_get_max_pstate,
2376         .get_max_physical = atom_get_max_pstate,
2377         .get_min = atom_get_min_pstate,
2378         .get_turbo = atom_get_turbo_pstate,
2379         .get_val = atom_get_val,
2380         .get_scaling = silvermont_get_scaling,
2381         .get_vid = atom_get_vid,
2382 };
2383
2384 static const struct pstate_funcs airmont_funcs = {
2385         .get_max = atom_get_max_pstate,
2386         .get_max_physical = atom_get_max_pstate,
2387         .get_min = atom_get_min_pstate,
2388         .get_turbo = atom_get_turbo_pstate,
2389         .get_val = atom_get_val,
2390         .get_scaling = airmont_get_scaling,
2391         .get_vid = atom_get_vid,
2392 };
2393
2394 static const struct pstate_funcs knl_funcs = {
2395         .get_max = core_get_max_pstate,
2396         .get_max_physical = core_get_max_pstate_physical,
2397         .get_min = core_get_min_pstate,
2398         .get_turbo = knl_get_turbo_pstate,
2399         .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2400         .get_scaling = core_get_scaling,
2401         .get_val = core_get_val,
2402 };
2403
2404 #define X86_MATCH(model, policy)                                         \
2405         X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2406                                            X86_FEATURE_APERFMPERF, &policy)
2407
2408 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2409         X86_MATCH(SANDYBRIDGE,          core_funcs),
2410         X86_MATCH(SANDYBRIDGE_X,        core_funcs),
2411         X86_MATCH(ATOM_SILVERMONT,      silvermont_funcs),
2412         X86_MATCH(IVYBRIDGE,            core_funcs),
2413         X86_MATCH(HASWELL,              core_funcs),
2414         X86_MATCH(BROADWELL,            core_funcs),
2415         X86_MATCH(IVYBRIDGE_X,          core_funcs),
2416         X86_MATCH(HASWELL_X,            core_funcs),
2417         X86_MATCH(HASWELL_L,            core_funcs),
2418         X86_MATCH(HASWELL_G,            core_funcs),
2419         X86_MATCH(BROADWELL_G,          core_funcs),
2420         X86_MATCH(ATOM_AIRMONT,         airmont_funcs),
2421         X86_MATCH(SKYLAKE_L,            core_funcs),
2422         X86_MATCH(BROADWELL_X,          core_funcs),
2423         X86_MATCH(SKYLAKE,              core_funcs),
2424         X86_MATCH(BROADWELL_D,          core_funcs),
2425         X86_MATCH(XEON_PHI_KNL,         knl_funcs),
2426         X86_MATCH(XEON_PHI_KNM,         knl_funcs),
2427         X86_MATCH(ATOM_GOLDMONT,        core_funcs),
2428         X86_MATCH(ATOM_GOLDMONT_PLUS,   core_funcs),
2429         X86_MATCH(SKYLAKE_X,            core_funcs),
2430         X86_MATCH(COMETLAKE,            core_funcs),
2431         X86_MATCH(ICELAKE_X,            core_funcs),
2432         X86_MATCH(TIGERLAKE,            core_funcs),
2433         X86_MATCH(SAPPHIRERAPIDS_X,     core_funcs),
2434         {}
2435 };
2436 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2437
2438 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2439         X86_MATCH(BROADWELL_D,          core_funcs),
2440         X86_MATCH(BROADWELL_X,          core_funcs),
2441         X86_MATCH(SKYLAKE_X,            core_funcs),
2442         X86_MATCH(ICELAKE_X,            core_funcs),
2443         X86_MATCH(SAPPHIRERAPIDS_X,     core_funcs),
2444         {}
2445 };
2446
2447 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2448         X86_MATCH(KABYLAKE,             core_funcs),
2449         {}
2450 };
2451
2452 static int intel_pstate_init_cpu(unsigned int cpunum)
2453 {
2454         struct cpudata *cpu;
2455
2456         cpu = all_cpu_data[cpunum];
2457
2458         if (!cpu) {
2459                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2460                 if (!cpu)
2461                         return -ENOMEM;
2462
2463                 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2464
2465                 cpu->cpu = cpunum;
2466
2467                 cpu->epp_default = -EINVAL;
2468
2469                 if (hwp_active) {
2470                         intel_pstate_hwp_enable(cpu);
2471
2472                         if (intel_pstate_acpi_pm_profile_server())
2473                                 hwp_boost = true;
2474                 }
2475         } else if (hwp_active) {
2476                 /*
2477                  * Re-enable HWP in case this happens after a resume from ACPI
2478                  * S3 if the CPU was offline during the whole system/resume
2479                  * cycle.
2480                  */
2481                 intel_pstate_hwp_reenable(cpu);
2482         }
2483
2484         cpu->epp_powersave = -EINVAL;
2485         cpu->epp_policy = 0;
2486
2487         intel_pstate_get_cpu_pstates(cpu);
2488
2489         pr_debug("controlling: cpu %d\n", cpunum);
2490
2491         return 0;
2492 }
2493
2494 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2495 {
2496         struct cpudata *cpu = all_cpu_data[cpu_num];
2497
2498         if (hwp_active && !hwp_boost)
2499                 return;
2500
2501         if (cpu->update_util_set)
2502                 return;
2503
2504         /* Prevent intel_pstate_update_util() from using stale data. */
2505         cpu->sample.time = 0;
2506         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2507                                      (hwp_active ?
2508                                       intel_pstate_update_util_hwp :
2509                                       intel_pstate_update_util));
2510         cpu->update_util_set = true;
2511 }
2512
2513 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2514 {
2515         struct cpudata *cpu_data = all_cpu_data[cpu];
2516
2517         if (!cpu_data->update_util_set)
2518                 return;
2519
2520         cpufreq_remove_update_util_hook(cpu);
2521         cpu_data->update_util_set = false;
2522         synchronize_rcu();
2523 }
2524
2525 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2526 {
2527         return global.turbo_disabled || global.no_turbo ?
2528                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2529 }
2530
2531 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2532                                             unsigned int policy_min,
2533                                             unsigned int policy_max)
2534 {
2535         int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2536         int32_t max_policy_perf, min_policy_perf;
2537
2538         max_policy_perf = policy_max / perf_ctl_scaling;
2539         if (policy_max == policy_min) {
2540                 min_policy_perf = max_policy_perf;
2541         } else {
2542                 min_policy_perf = policy_min / perf_ctl_scaling;
2543                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2544                                           0, max_policy_perf);
2545         }
2546
2547         /*
2548          * HWP needs some special consideration, because HWP_REQUEST uses
2549          * abstract values to represent performance rather than pure ratios.
2550          */
2551         if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2552                 int freq;
2553
2554                 freq = max_policy_perf * perf_ctl_scaling;
2555                 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2556                 freq = min_policy_perf * perf_ctl_scaling;
2557                 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2558         }
2559
2560         pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2561                  cpu->cpu, min_policy_perf, max_policy_perf);
2562
2563         /* Normalize user input to [min_perf, max_perf] */
2564         if (per_cpu_limits) {
2565                 cpu->min_perf_ratio = min_policy_perf;
2566                 cpu->max_perf_ratio = max_policy_perf;
2567         } else {
2568                 int turbo_max = cpu->pstate.turbo_pstate;
2569                 int32_t global_min, global_max;
2570
2571                 /* Global limits are in percent of the maximum turbo P-state. */
2572                 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2573                 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2574                 global_min = clamp_t(int32_t, global_min, 0, global_max);
2575
2576                 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2577                          global_min, global_max);
2578
2579                 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2580                 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2581                 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2582                 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2583
2584                 /* Make sure min_perf <= max_perf */
2585                 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2586                                           cpu->max_perf_ratio);
2587
2588         }
2589         pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2590                  cpu->max_perf_ratio,
2591                  cpu->min_perf_ratio);
2592 }
2593
2594 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2595 {
2596         struct cpudata *cpu;
2597
2598         if (!policy->cpuinfo.max_freq)
2599                 return -ENODEV;
2600
2601         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2602                  policy->cpuinfo.max_freq, policy->max);
2603
2604         cpu = all_cpu_data[policy->cpu];
2605         cpu->policy = policy->policy;
2606
2607         mutex_lock(&intel_pstate_limits_lock);
2608
2609         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2610
2611         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2612                 /*
2613                  * NOHZ_FULL CPUs need this as the governor callback may not
2614                  * be invoked on them.
2615                  */
2616                 intel_pstate_clear_update_util_hook(policy->cpu);
2617                 intel_pstate_max_within_limits(cpu);
2618         } else {
2619                 intel_pstate_set_update_util_hook(policy->cpu);
2620         }
2621
2622         if (hwp_active) {
2623                 /*
2624                  * When hwp_boost was active before and dynamically it
2625                  * was turned off, in that case we need to clear the
2626                  * update util hook.
2627                  */
2628                 if (!hwp_boost)
2629                         intel_pstate_clear_update_util_hook(policy->cpu);
2630                 intel_pstate_hwp_set(policy->cpu);
2631         }
2632         /*
2633          * policy->cur is never updated with the intel_pstate driver, but it
2634          * is used as a stale frequency value. So, keep it within limits.
2635          */
2636         policy->cur = policy->min;
2637
2638         mutex_unlock(&intel_pstate_limits_lock);
2639
2640         return 0;
2641 }
2642
2643 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2644                                            struct cpufreq_policy_data *policy)
2645 {
2646         if (!hwp_active &&
2647             cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2648             policy->max < policy->cpuinfo.max_freq &&
2649             policy->max > cpu->pstate.max_freq) {
2650                 pr_debug("policy->max > max non turbo frequency\n");
2651                 policy->max = policy->cpuinfo.max_freq;
2652         }
2653 }
2654
2655 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2656                                            struct cpufreq_policy_data *policy)
2657 {
2658         int max_freq;
2659
2660         update_turbo_state();
2661         if (hwp_active) {
2662                 intel_pstate_get_hwp_cap(cpu);
2663                 max_freq = global.no_turbo || global.turbo_disabled ?
2664                                 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2665         } else {
2666                 max_freq = intel_pstate_get_max_freq(cpu);
2667         }
2668         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2669
2670         intel_pstate_adjust_policy_max(cpu, policy);
2671 }
2672
2673 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2674 {
2675         intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2676
2677         return 0;
2678 }
2679
2680 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2681 {
2682         struct cpudata *cpu = all_cpu_data[policy->cpu];
2683
2684         pr_debug("CPU %d going offline\n", cpu->cpu);
2685
2686         if (cpu->suspended)
2687                 return 0;
2688
2689         /*
2690          * If the CPU is an SMT thread and it goes offline with the performance
2691          * settings different from the minimum, it will prevent its sibling
2692          * from getting to lower performance levels, so force the minimum
2693          * performance on CPU offline to prevent that from happening.
2694          */
2695         if (hwp_active)
2696                 intel_pstate_hwp_offline(cpu);
2697         else
2698                 intel_pstate_set_min_pstate(cpu);
2699
2700         intel_pstate_exit_perf_limits(policy);
2701
2702         return 0;
2703 }
2704
2705 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2706 {
2707         struct cpudata *cpu = all_cpu_data[policy->cpu];
2708
2709         pr_debug("CPU %d going online\n", cpu->cpu);
2710
2711         intel_pstate_init_acpi_perf_limits(policy);
2712
2713         if (hwp_active) {
2714                 /*
2715                  * Re-enable HWP and clear the "suspended" flag to let "resume"
2716                  * know that it need not do that.
2717                  */
2718                 intel_pstate_hwp_reenable(cpu);
2719                 cpu->suspended = false;
2720         }
2721
2722         return 0;
2723 }
2724
2725 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2726 {
2727         intel_pstate_clear_update_util_hook(policy->cpu);
2728
2729         return intel_cpufreq_cpu_offline(policy);
2730 }
2731
2732 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2733 {
2734         pr_debug("CPU %d exiting\n", policy->cpu);
2735
2736         policy->fast_switch_possible = false;
2737
2738         return 0;
2739 }
2740
2741 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2742 {
2743         struct cpudata *cpu;
2744         int rc;
2745
2746         rc = intel_pstate_init_cpu(policy->cpu);
2747         if (rc)
2748                 return rc;
2749
2750         cpu = all_cpu_data[policy->cpu];
2751
2752         cpu->max_perf_ratio = 0xFF;
2753         cpu->min_perf_ratio = 0;
2754
2755         /* cpuinfo and default policy values */
2756         policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2757         update_turbo_state();
2758         global.turbo_disabled_mf = global.turbo_disabled;
2759         policy->cpuinfo.max_freq = global.turbo_disabled ?
2760                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2761
2762         policy->min = policy->cpuinfo.min_freq;
2763         policy->max = policy->cpuinfo.max_freq;
2764
2765         intel_pstate_init_acpi_perf_limits(policy);
2766
2767         policy->fast_switch_possible = true;
2768
2769         return 0;
2770 }
2771
2772 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2773 {
2774         int ret = __intel_pstate_cpu_init(policy);
2775
2776         if (ret)
2777                 return ret;
2778
2779         /*
2780          * Set the policy to powersave to provide a valid fallback value in case
2781          * the default cpufreq governor is neither powersave nor performance.
2782          */
2783         policy->policy = CPUFREQ_POLICY_POWERSAVE;
2784
2785         if (hwp_active) {
2786                 struct cpudata *cpu = all_cpu_data[policy->cpu];
2787
2788                 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2789         }
2790
2791         return 0;
2792 }
2793
2794 static struct cpufreq_driver intel_pstate = {
2795         .flags          = CPUFREQ_CONST_LOOPS,
2796         .verify         = intel_pstate_verify_policy,
2797         .setpolicy      = intel_pstate_set_policy,
2798         .suspend        = intel_pstate_suspend,
2799         .resume         = intel_pstate_resume,
2800         .init           = intel_pstate_cpu_init,
2801         .exit           = intel_pstate_cpu_exit,
2802         .offline        = intel_pstate_cpu_offline,
2803         .online         = intel_pstate_cpu_online,
2804         .update_limits  = intel_pstate_update_limits,
2805         .name           = "intel_pstate",
2806 };
2807
2808 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2809 {
2810         struct cpudata *cpu = all_cpu_data[policy->cpu];
2811
2812         intel_pstate_verify_cpu_policy(cpu, policy);
2813         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2814
2815         return 0;
2816 }
2817
2818 /* Use of trace in passive mode:
2819  *
2820  * In passive mode the trace core_busy field (also known as the
2821  * performance field, and lablelled as such on the graphs; also known as
2822  * core_avg_perf) is not needed and so is re-assigned to indicate if the
2823  * driver call was via the normal or fast switch path. Various graphs
2824  * output from the intel_pstate_tracer.py utility that include core_busy
2825  * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2826  * so we use 10 to indicate the normal path through the driver, and
2827  * 90 to indicate the fast switch path through the driver.
2828  * The scaled_busy field is not used, and is set to 0.
2829  */
2830
2831 #define INTEL_PSTATE_TRACE_TARGET 10
2832 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2833
2834 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2835 {
2836         struct sample *sample;
2837
2838         if (!trace_pstate_sample_enabled())
2839                 return;
2840
2841         if (!intel_pstate_sample(cpu, ktime_get()))
2842                 return;
2843
2844         sample = &cpu->sample;
2845         trace_pstate_sample(trace_type,
2846                 0,
2847                 old_pstate,
2848                 cpu->pstate.current_pstate,
2849                 sample->mperf,
2850                 sample->aperf,
2851                 sample->tsc,
2852                 get_avg_frequency(cpu),
2853                 fp_toint(cpu->iowait_boost * 100));
2854 }
2855
2856 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2857                                      u32 desired, bool fast_switch)
2858 {
2859         u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2860
2861         value &= ~HWP_MIN_PERF(~0L);
2862         value |= HWP_MIN_PERF(min);
2863
2864         value &= ~HWP_MAX_PERF(~0L);
2865         value |= HWP_MAX_PERF(max);
2866
2867         value &= ~HWP_DESIRED_PERF(~0L);
2868         value |= HWP_DESIRED_PERF(desired);
2869
2870         if (value == prev)
2871                 return;
2872
2873         WRITE_ONCE(cpu->hwp_req_cached, value);
2874         if (fast_switch)
2875                 wrmsrl(MSR_HWP_REQUEST, value);
2876         else
2877                 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2878 }
2879
2880 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2881                                           u32 target_pstate, bool fast_switch)
2882 {
2883         if (fast_switch)
2884                 wrmsrl(MSR_IA32_PERF_CTL,
2885                        pstate_funcs.get_val(cpu, target_pstate));
2886         else
2887                 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2888                               pstate_funcs.get_val(cpu, target_pstate));
2889 }
2890
2891 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2892                                        int target_pstate, bool fast_switch)
2893 {
2894         struct cpudata *cpu = all_cpu_data[policy->cpu];
2895         int old_pstate = cpu->pstate.current_pstate;
2896
2897         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2898         if (hwp_active) {
2899                 int max_pstate = policy->strict_target ?
2900                                         target_pstate : cpu->max_perf_ratio;
2901
2902                 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2903                                          fast_switch);
2904         } else if (target_pstate != old_pstate) {
2905                 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2906         }
2907
2908         cpu->pstate.current_pstate = target_pstate;
2909
2910         intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2911                             INTEL_PSTATE_TRACE_TARGET, old_pstate);
2912
2913         return target_pstate;
2914 }
2915
2916 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2917                                 unsigned int target_freq,
2918                                 unsigned int relation)
2919 {
2920         struct cpudata *cpu = all_cpu_data[policy->cpu];
2921         struct cpufreq_freqs freqs;
2922         int target_pstate;
2923
2924         update_turbo_state();
2925
2926         freqs.old = policy->cur;
2927         freqs.new = target_freq;
2928
2929         cpufreq_freq_transition_begin(policy, &freqs);
2930
2931         target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
2932         target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2933
2934         freqs.new = target_pstate * cpu->pstate.scaling;
2935
2936         cpufreq_freq_transition_end(policy, &freqs, false);
2937
2938         return 0;
2939 }
2940
2941 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2942                                               unsigned int target_freq)
2943 {
2944         struct cpudata *cpu = all_cpu_data[policy->cpu];
2945         int target_pstate;
2946
2947         update_turbo_state();
2948
2949         target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
2950
2951         target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2952
2953         return target_pstate * cpu->pstate.scaling;
2954 }
2955
2956 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2957                                       unsigned long min_perf,
2958                                       unsigned long target_perf,
2959                                       unsigned long capacity)
2960 {
2961         struct cpudata *cpu = all_cpu_data[cpunum];
2962         u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2963         int old_pstate = cpu->pstate.current_pstate;
2964         int cap_pstate, min_pstate, max_pstate, target_pstate;
2965
2966         update_turbo_state();
2967         cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2968                                              HWP_HIGHEST_PERF(hwp_cap);
2969
2970         /* Optimization: Avoid unnecessary divisions. */
2971
2972         target_pstate = cap_pstate;
2973         if (target_perf < capacity)
2974                 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2975
2976         min_pstate = cap_pstate;
2977         if (min_perf < capacity)
2978                 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2979
2980         if (min_pstate < cpu->pstate.min_pstate)
2981                 min_pstate = cpu->pstate.min_pstate;
2982
2983         if (min_pstate < cpu->min_perf_ratio)
2984                 min_pstate = cpu->min_perf_ratio;
2985
2986         if (min_pstate > cpu->max_perf_ratio)
2987                 min_pstate = cpu->max_perf_ratio;
2988
2989         max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2990         if (max_pstate < min_pstate)
2991                 max_pstate = min_pstate;
2992
2993         target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2994
2995         intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
2996
2997         cpu->pstate.current_pstate = target_pstate;
2998         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2999 }
3000
3001 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3002 {
3003         struct freq_qos_request *req;
3004         struct cpudata *cpu;
3005         struct device *dev;
3006         int ret, freq;
3007
3008         dev = get_cpu_device(policy->cpu);
3009         if (!dev)
3010                 return -ENODEV;
3011
3012         ret = __intel_pstate_cpu_init(policy);
3013         if (ret)
3014                 return ret;
3015
3016         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3017         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3018         policy->cur = policy->cpuinfo.min_freq;
3019
3020         req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3021         if (!req) {
3022                 ret = -ENOMEM;
3023                 goto pstate_exit;
3024         }
3025
3026         cpu = all_cpu_data[policy->cpu];
3027
3028         if (hwp_active) {
3029                 u64 value;
3030
3031                 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3032
3033                 intel_pstate_get_hwp_cap(cpu);
3034
3035                 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3036                 WRITE_ONCE(cpu->hwp_req_cached, value);
3037
3038                 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3039         } else {
3040                 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3041         }
3042
3043         freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3044
3045         ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3046                                    freq);
3047         if (ret < 0) {
3048                 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3049                 goto free_req;
3050         }
3051
3052         freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3053
3054         ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3055                                    freq);
3056         if (ret < 0) {
3057                 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3058                 goto remove_min_req;
3059         }
3060
3061         policy->driver_data = req;
3062
3063         return 0;
3064
3065 remove_min_req:
3066         freq_qos_remove_request(req);
3067 free_req:
3068         kfree(req);
3069 pstate_exit:
3070         intel_pstate_exit_perf_limits(policy);
3071
3072         return ret;
3073 }
3074
3075 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3076 {
3077         struct freq_qos_request *req;
3078
3079         req = policy->driver_data;
3080
3081         freq_qos_remove_request(req + 1);
3082         freq_qos_remove_request(req);
3083         kfree(req);
3084
3085         return intel_pstate_cpu_exit(policy);
3086 }
3087
3088 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3089 {
3090         intel_pstate_suspend(policy);
3091
3092         if (hwp_active) {
3093                 struct cpudata *cpu = all_cpu_data[policy->cpu];
3094                 u64 value = READ_ONCE(cpu->hwp_req_cached);
3095
3096                 /*
3097                  * Clear the desired perf field in MSR_HWP_REQUEST in case
3098                  * intel_cpufreq_adjust_perf() is in use and the last value
3099                  * written by it may not be suitable.
3100                  */
3101                 value &= ~HWP_DESIRED_PERF(~0L);
3102                 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3103                 WRITE_ONCE(cpu->hwp_req_cached, value);
3104         }
3105
3106         return 0;
3107 }
3108
3109 static struct cpufreq_driver intel_cpufreq = {
3110         .flags          = CPUFREQ_CONST_LOOPS,
3111         .verify         = intel_cpufreq_verify_policy,
3112         .target         = intel_cpufreq_target,
3113         .fast_switch    = intel_cpufreq_fast_switch,
3114         .init           = intel_cpufreq_cpu_init,
3115         .exit           = intel_cpufreq_cpu_exit,
3116         .offline        = intel_cpufreq_cpu_offline,
3117         .online         = intel_pstate_cpu_online,
3118         .suspend        = intel_cpufreq_suspend,
3119         .resume         = intel_pstate_resume,
3120         .update_limits  = intel_pstate_update_limits,
3121         .name           = "intel_cpufreq",
3122 };
3123
3124 static struct cpufreq_driver *default_driver;
3125
3126 static void intel_pstate_driver_cleanup(void)
3127 {
3128         unsigned int cpu;
3129
3130         cpus_read_lock();
3131         for_each_online_cpu(cpu) {
3132                 if (all_cpu_data[cpu]) {
3133                         if (intel_pstate_driver == &intel_pstate)
3134                                 intel_pstate_clear_update_util_hook(cpu);
3135
3136                         spin_lock(&hwp_notify_lock);
3137                         kfree(all_cpu_data[cpu]);
3138                         WRITE_ONCE(all_cpu_data[cpu], NULL);
3139                         spin_unlock(&hwp_notify_lock);
3140                 }
3141         }
3142         cpus_read_unlock();
3143
3144         intel_pstate_driver = NULL;
3145 }
3146
3147 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3148 {
3149         int ret;
3150
3151         if (driver == &intel_pstate)
3152                 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3153
3154         memset(&global, 0, sizeof(global));
3155         global.max_perf_pct = 100;
3156
3157         intel_pstate_driver = driver;
3158         ret = cpufreq_register_driver(intel_pstate_driver);
3159         if (ret) {
3160                 intel_pstate_driver_cleanup();
3161                 return ret;
3162         }
3163
3164         global.min_perf_pct = min_perf_pct_min();
3165
3166         return 0;
3167 }
3168
3169 static ssize_t intel_pstate_show_status(char *buf)
3170 {
3171         if (!intel_pstate_driver)
3172                 return sprintf(buf, "off\n");
3173
3174         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3175                                         "active" : "passive");
3176 }
3177
3178 static int intel_pstate_update_status(const char *buf, size_t size)
3179 {
3180         if (size == 3 && !strncmp(buf, "off", size)) {
3181                 if (!intel_pstate_driver)
3182                         return -EINVAL;
3183
3184                 if (hwp_active)
3185                         return -EBUSY;
3186
3187                 cpufreq_unregister_driver(intel_pstate_driver);
3188                 intel_pstate_driver_cleanup();
3189                 return 0;
3190         }
3191
3192         if (size == 6 && !strncmp(buf, "active", size)) {
3193                 if (intel_pstate_driver) {
3194                         if (intel_pstate_driver == &intel_pstate)
3195                                 return 0;
3196
3197                         cpufreq_unregister_driver(intel_pstate_driver);
3198                 }
3199
3200                 return intel_pstate_register_driver(&intel_pstate);
3201         }
3202
3203         if (size == 7 && !strncmp(buf, "passive", size)) {
3204                 if (intel_pstate_driver) {
3205                         if (intel_pstate_driver == &intel_cpufreq)
3206                                 return 0;
3207
3208                         cpufreq_unregister_driver(intel_pstate_driver);
3209                         intel_pstate_sysfs_hide_hwp_dynamic_boost();
3210                 }
3211
3212                 return intel_pstate_register_driver(&intel_cpufreq);
3213         }
3214
3215         return -EINVAL;
3216 }
3217
3218 static int no_load __initdata;
3219 static int no_hwp __initdata;
3220 static int hwp_only __initdata;
3221 static unsigned int force_load __initdata;
3222
3223 static int __init intel_pstate_msrs_not_valid(void)
3224 {
3225         if (!pstate_funcs.get_max(0) ||
3226             !pstate_funcs.get_min(0) ||
3227             !pstate_funcs.get_turbo(0))
3228                 return -ENODEV;
3229
3230         return 0;
3231 }
3232
3233 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3234 {
3235         pstate_funcs.get_max   = funcs->get_max;
3236         pstate_funcs.get_max_physical = funcs->get_max_physical;
3237         pstate_funcs.get_min   = funcs->get_min;
3238         pstate_funcs.get_turbo = funcs->get_turbo;
3239         pstate_funcs.get_scaling = funcs->get_scaling;
3240         pstate_funcs.get_val   = funcs->get_val;
3241         pstate_funcs.get_vid   = funcs->get_vid;
3242         pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3243 }
3244
3245 #ifdef CONFIG_ACPI
3246
3247 static bool __init intel_pstate_no_acpi_pss(void)
3248 {
3249         int i;
3250
3251         for_each_possible_cpu(i) {
3252                 acpi_status status;
3253                 union acpi_object *pss;
3254                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3255                 struct acpi_processor *pr = per_cpu(processors, i);
3256
3257                 if (!pr)
3258                         continue;
3259
3260                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3261                 if (ACPI_FAILURE(status))
3262                         continue;
3263
3264                 pss = buffer.pointer;
3265                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3266                         kfree(pss);
3267                         return false;
3268                 }
3269
3270                 kfree(pss);
3271         }
3272
3273         pr_debug("ACPI _PSS not found\n");
3274         return true;
3275 }
3276
3277 static bool __init intel_pstate_no_acpi_pcch(void)
3278 {
3279         acpi_status status;
3280         acpi_handle handle;
3281
3282         status = acpi_get_handle(NULL, "\\_SB", &handle);
3283         if (ACPI_FAILURE(status))
3284                 goto not_found;
3285
3286         if (acpi_has_method(handle, "PCCH"))
3287                 return false;
3288
3289 not_found:
3290         pr_debug("ACPI PCCH not found\n");
3291         return true;
3292 }
3293
3294 static bool __init intel_pstate_has_acpi_ppc(void)
3295 {
3296         int i;
3297
3298         for_each_possible_cpu(i) {
3299                 struct acpi_processor *pr = per_cpu(processors, i);
3300
3301                 if (!pr)
3302                         continue;
3303                 if (acpi_has_method(pr->handle, "_PPC"))
3304                         return true;
3305         }
3306         pr_debug("ACPI _PPC not found\n");
3307         return false;
3308 }
3309
3310 enum {
3311         PSS,
3312         PPC,
3313 };
3314
3315 /* Hardware vendor-specific info that has its own power management modes */
3316 static struct acpi_platform_list plat_info[] __initdata = {
3317         {"HP    ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3318         {"ORACLE", "X4-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3319         {"ORACLE", "X4-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3320         {"ORACLE", "X4-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3321         {"ORACLE", "X3-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3322         {"ORACLE", "X3-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3323         {"ORACLE", "X3-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3324         {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3325         {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3326         {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3327         {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3328         {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3329         {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3330         {"ORACLE", "X6-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3331         {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3332         { } /* End */
3333 };
3334
3335 #define BITMASK_OOB     (BIT(8) | BIT(18))
3336
3337 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3338 {
3339         const struct x86_cpu_id *id;
3340         u64 misc_pwr;
3341         int idx;
3342
3343         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3344         if (id) {
3345                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3346                 if (misc_pwr & BITMASK_OOB) {
3347                         pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3348                         pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3349                         return true;
3350                 }
3351         }
3352
3353         idx = acpi_match_platform_list(plat_info);
3354         if (idx < 0)
3355                 return false;
3356
3357         switch (plat_info[idx].data) {
3358         case PSS:
3359                 if (!intel_pstate_no_acpi_pss())
3360                         return false;
3361
3362                 return intel_pstate_no_acpi_pcch();
3363         case PPC:
3364                 return intel_pstate_has_acpi_ppc() && !force_load;
3365         }
3366
3367         return false;
3368 }
3369
3370 static void intel_pstate_request_control_from_smm(void)
3371 {
3372         /*
3373          * It may be unsafe to request P-states control from SMM if _PPC support
3374          * has not been enabled.
3375          */
3376         if (acpi_ppc)
3377                 acpi_processor_pstate_control();
3378 }
3379 #else /* CONFIG_ACPI not enabled */
3380 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3381 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3382 static inline void intel_pstate_request_control_from_smm(void) {}
3383 #endif /* CONFIG_ACPI */
3384
3385 #define INTEL_PSTATE_HWP_BROADWELL      0x01
3386
3387 #define X86_MATCH_HWP(model, hwp_mode)                                  \
3388         X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3389                                            X86_FEATURE_HWP, hwp_mode)
3390
3391 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3392         X86_MATCH_HWP(BROADWELL_X,      INTEL_PSTATE_HWP_BROADWELL),
3393         X86_MATCH_HWP(BROADWELL_D,      INTEL_PSTATE_HWP_BROADWELL),
3394         X86_MATCH_HWP(ANY,              0),
3395         {}
3396 };
3397
3398 static bool intel_pstate_hwp_is_enabled(void)
3399 {
3400         u64 value;
3401
3402         rdmsrl(MSR_PM_ENABLE, value);
3403         return !!(value & 0x1);
3404 }
3405
3406 static const struct x86_cpu_id intel_epp_balance_perf[] = {
3407         /*
3408          * Set EPP value as 102, this is the max suggested EPP
3409          * which can result in one core turbo frequency for
3410          * AlderLake Mobile CPUs.
3411          */
3412         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102),
3413         X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 32),
3414         {}
3415 };
3416
3417 static int __init intel_pstate_init(void)
3418 {
3419         static struct cpudata **_all_cpu_data;
3420         const struct x86_cpu_id *id;
3421         int rc;
3422
3423         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3424                 return -ENODEV;
3425
3426         id = x86_match_cpu(hwp_support_ids);
3427         if (id) {
3428                 hwp_forced = intel_pstate_hwp_is_enabled();
3429
3430                 if (hwp_forced)
3431                         pr_info("HWP enabled by BIOS\n");
3432                 else if (no_load)
3433                         return -ENODEV;
3434
3435                 copy_cpu_funcs(&core_funcs);
3436                 /*
3437                  * Avoid enabling HWP for processors without EPP support,
3438                  * because that means incomplete HWP implementation which is a
3439                  * corner case and supporting it is generally problematic.
3440                  *
3441                  * If HWP is enabled already, though, there is no choice but to
3442                  * deal with it.
3443                  */
3444                 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3445                         WRITE_ONCE(hwp_active, 1);
3446                         hwp_mode_bdw = id->driver_data;
3447                         intel_pstate.attr = hwp_cpufreq_attrs;
3448                         intel_cpufreq.attr = hwp_cpufreq_attrs;
3449                         intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3450                         intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3451                         if (!default_driver)
3452                                 default_driver = &intel_pstate;
3453
3454                         pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3455
3456                         goto hwp_cpu_matched;
3457                 }
3458                 pr_info("HWP not enabled\n");
3459         } else {
3460                 if (no_load)
3461                         return -ENODEV;
3462
3463                 id = x86_match_cpu(intel_pstate_cpu_ids);
3464                 if (!id) {
3465                         pr_info("CPU model not supported\n");
3466                         return -ENODEV;
3467                 }
3468
3469                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3470         }
3471
3472         if (intel_pstate_msrs_not_valid()) {
3473                 pr_info("Invalid MSRs\n");
3474                 return -ENODEV;
3475         }
3476         /* Without HWP start in the passive mode. */
3477         if (!default_driver)
3478                 default_driver = &intel_cpufreq;
3479
3480 hwp_cpu_matched:
3481         /*
3482          * The Intel pstate driver will be ignored if the platform
3483          * firmware has its own power management modes.
3484          */
3485         if (intel_pstate_platform_pwr_mgmt_exists()) {
3486                 pr_info("P-states controlled by the platform\n");
3487                 return -ENODEV;
3488         }
3489
3490         if (!hwp_active && hwp_only)
3491                 return -ENOTSUPP;
3492
3493         pr_info("Intel P-state driver initializing\n");
3494
3495         _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3496         if (!_all_cpu_data)
3497                 return -ENOMEM;
3498
3499         WRITE_ONCE(all_cpu_data, _all_cpu_data);
3500
3501         intel_pstate_request_control_from_smm();
3502
3503         intel_pstate_sysfs_expose_params();
3504
3505         if (hwp_active) {
3506                 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf);
3507
3508                 if (id)
3509                         epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data;
3510         }
3511
3512         mutex_lock(&intel_pstate_driver_lock);
3513         rc = intel_pstate_register_driver(default_driver);
3514         mutex_unlock(&intel_pstate_driver_lock);
3515         if (rc) {
3516                 intel_pstate_sysfs_remove();
3517                 return rc;
3518         }
3519
3520         if (hwp_active) {
3521                 const struct x86_cpu_id *id;
3522
3523                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3524                 if (id) {
3525                         set_power_ctl_ee_state(false);
3526                         pr_info("Disabling energy efficiency optimization\n");
3527                 }
3528
3529                 pr_info("HWP enabled\n");
3530         } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3531                 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3532         }
3533
3534         return 0;
3535 }
3536 device_initcall(intel_pstate_init);
3537
3538 static int __init intel_pstate_setup(char *str)
3539 {
3540         if (!str)
3541                 return -EINVAL;
3542
3543         if (!strcmp(str, "disable"))
3544                 no_load = 1;
3545         else if (!strcmp(str, "active"))
3546                 default_driver = &intel_pstate;
3547         else if (!strcmp(str, "passive"))
3548                 default_driver = &intel_cpufreq;
3549
3550         if (!strcmp(str, "no_hwp"))
3551                 no_hwp = 1;
3552
3553         if (!strcmp(str, "force"))
3554                 force_load = 1;
3555         if (!strcmp(str, "hwp_only"))
3556                 hwp_only = 1;
3557         if (!strcmp(str, "per_cpu_perf_limits"))
3558                 per_cpu_limits = true;
3559
3560 #ifdef CONFIG_ACPI
3561         if (!strcmp(str, "support_acpi_ppc"))
3562                 acpi_ppc = true;
3563 #endif
3564
3565         return 0;
3566 }
3567 early_param("intel_pstate", intel_pstate_setup);
3568
3569 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3570 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");