2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/cpu.h>
11 #include <linux/cpufreq.h>
12 #include <linux/cpu_cooling.h>
13 #include <linux/err.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-consumer.h>
17 #include <linux/of_address.h>
18 #include <linux/pm_opp.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/consumer.h>
22 #define PU_SOC_VOLTAGE_NORMAL 1250000
23 #define PU_SOC_VOLTAGE_HIGH 1275000
24 #define FREQ_1P2_GHZ 1200000000
26 static struct regulator *arm_reg;
27 static struct regulator *pu_reg;
28 static struct regulator *soc_reg;
30 enum IMX6_CPUFREQ_CLKS {
36 /* MX6UL requires two more clks */
40 #define IMX6Q_CPUFREQ_CLK_NUM 5
41 #define IMX6UL_CPUFREQ_CLK_NUM 7
44 static struct clk_bulk_data clks[] = {
49 { .id = "pll2_pfd2_396m" },
51 { .id = "secondary_sel" },
54 static struct device *cpu_dev;
55 static struct thermal_cooling_device *cdev;
57 static struct cpufreq_frequency_table *freq_table;
58 static unsigned int max_freq;
59 static unsigned int transition_latency;
61 static u32 *imx6_soc_volt;
62 static u32 soc_opp_count;
64 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
66 struct dev_pm_opp *opp;
67 unsigned long freq_hz, volt, volt_old;
68 unsigned int old_freq, new_freq;
69 bool pll1_sys_temp_enabled = false;
72 new_freq = freq_table[index].frequency;
73 freq_hz = new_freq * 1000;
74 old_freq = clk_get_rate(clks[ARM].clk) / 1000;
76 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
78 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
82 volt = dev_pm_opp_get_voltage(opp);
85 volt_old = regulator_get_voltage(arm_reg);
87 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
88 old_freq / 1000, volt_old / 1000,
89 new_freq / 1000, volt / 1000);
91 /* scaling up? scale voltage before frequency */
92 if (new_freq > old_freq) {
93 if (!IS_ERR(pu_reg)) {
94 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
96 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
100 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
102 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
105 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
108 "failed to scale vddarm up: %d\n", ret);
114 * The setpoints are selected per PLL/PDF frequencies, so we need to
115 * reprogram PLL for frequency scaling. The procedure of reprogramming
117 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
118 * flow is slightly different from other i.MX6 OSC.
119 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
120 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
121 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
122 * - Disable pll2_pfd2_396m_clk
124 if (of_machine_is_compatible("fsl,imx6ul") ||
125 of_machine_is_compatible("fsl,imx6ull")) {
127 * When changing pll1_sw_clk's parent to pll1_sys_clk,
128 * CPU may run at higher than 528MHz, this will lead to
129 * the system unstable if the voltage is lower than the
130 * voltage of 528MHz, so lower the CPU frequency to one
131 * half before changing CPU frequency.
133 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
134 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
135 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
136 clk_set_parent(clks[SECONDARY_SEL].clk,
139 clk_set_parent(clks[SECONDARY_SEL].clk,
140 clks[PLL2_PFD2_396M].clk);
141 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
142 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
143 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
144 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
145 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
148 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
149 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
150 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
151 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
152 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
154 /* pll1_sys needs to be enabled for divider rate change to work. */
155 pll1_sys_temp_enabled = true;
156 clk_prepare_enable(clks[PLL1_SYS].clk);
160 /* Ensure the arm clock divider is what we expect */
161 ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
165 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
166 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
169 "failed to restore vddarm voltage: %d\n", ret1);
173 /* PLL1 is only needed until after ARM-PODF is set. */
174 if (pll1_sys_temp_enabled)
175 clk_disable_unprepare(clks[PLL1_SYS].clk);
177 /* scaling down? scale voltage after frequency */
178 if (new_freq < old_freq) {
179 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
182 "failed to scale vddarm down: %d\n", ret);
185 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
187 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
190 if (!IS_ERR(pu_reg)) {
191 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
193 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
202 static void imx6q_cpufreq_ready(struct cpufreq_policy *policy)
204 cdev = of_cpufreq_cooling_register(policy);
208 "running cpufreq without cooling device: %ld\n",
212 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
216 policy->clk = clks[ARM].clk;
217 ret = cpufreq_generic_init(policy, freq_table, transition_latency);
218 policy->suspend_freq = max_freq;
223 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
225 cpufreq_cooling_unregister(cdev);
230 static struct cpufreq_driver imx6q_cpufreq_driver = {
231 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
232 .verify = cpufreq_generic_frequency_table_verify,
233 .target_index = imx6q_set_target,
234 .get = cpufreq_generic_get,
235 .init = imx6q_cpufreq_init,
236 .exit = imx6q_cpufreq_exit,
237 .name = "imx6q-cpufreq",
238 .ready = imx6q_cpufreq_ready,
239 .attr = cpufreq_generic_attr,
240 .suspend = cpufreq_generic_suspend,
243 static void imx6x_disable_freq_in_opp(struct device *dev, unsigned long freq)
245 int ret = dev_pm_opp_disable(dev, freq);
247 if (ret < 0 && ret != -ENODEV)
248 dev_warn(dev, "failed to disable %ldMHz OPP\n", freq / 1000000);
251 #define OCOTP_CFG3 0x440
252 #define OCOTP_CFG3_SPEED_SHIFT 16
253 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
254 #define OCOTP_CFG3_SPEED_996MHZ 0x2
255 #define OCOTP_CFG3_SPEED_852MHZ 0x1
257 static void imx6q_opp_check_speed_grading(struct device *dev)
259 struct device_node *np;
263 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
267 base = of_iomap(np, 0);
269 dev_err(dev, "failed to map ocotp\n");
274 * SPEED_GRADING[1:0] defines the max speed of ARM:
275 * 2b'11: 1200000000Hz;
276 * 2b'10: 996000000Hz;
277 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
278 * 2b'00: 792000000Hz;
279 * We need to set the max speed of ARM according to fuse map.
281 val = readl_relaxed(base + OCOTP_CFG3);
282 val >>= OCOTP_CFG3_SPEED_SHIFT;
285 if (val < OCOTP_CFG3_SPEED_996MHZ)
286 imx6x_disable_freq_in_opp(dev, 996000000);
288 if (of_machine_is_compatible("fsl,imx6q") ||
289 of_machine_is_compatible("fsl,imx6qp")) {
290 if (val != OCOTP_CFG3_SPEED_852MHZ)
291 imx6x_disable_freq_in_opp(dev, 852000000);
293 if (val != OCOTP_CFG3_SPEED_1P2GHZ)
294 imx6x_disable_freq_in_opp(dev, 1200000000);
301 #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
302 #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
303 #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
305 static int imx6ul_opp_check_speed_grading(struct device *dev)
310 if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
311 ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
315 struct device_node *np;
318 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
320 np = of_find_compatible_node(NULL, NULL,
321 "fsl,imx6ull-ocotp");
325 base = of_iomap(np, 0);
328 dev_err(dev, "failed to map ocotp\n");
332 val = readl_relaxed(base + OCOTP_CFG3);
337 * Speed GRADING[1:0] defines the max speed of ARM:
339 * 2b'01: 528000000Hz;
340 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
341 * 2b'11: 900000000Hz on i.MX6ULL only;
342 * We need to set the max speed of ARM according to fuse map.
344 val >>= OCOTP_CFG3_SPEED_SHIFT;
347 if (of_machine_is_compatible("fsl,imx6ul"))
348 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
349 imx6x_disable_freq_in_opp(dev, 696000000);
351 if (of_machine_is_compatible("fsl,imx6ull")) {
352 if (val < OCOTP_CFG3_6ULL_SPEED_792MHZ)
353 imx6x_disable_freq_in_opp(dev, 792000000);
355 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
356 imx6x_disable_freq_in_opp(dev, 900000000);
362 static int imx6q_cpufreq_probe(struct platform_device *pdev)
364 struct device_node *np;
365 struct dev_pm_opp *opp;
366 unsigned long min_volt, max_volt;
368 const struct property *prop;
372 cpu_dev = get_cpu_device(0);
374 pr_err("failed to get cpu0 device\n");
378 np = of_node_get(cpu_dev->of_node);
380 dev_err(cpu_dev, "failed to find cpu0 node\n");
384 if (of_machine_is_compatible("fsl,imx6ul") ||
385 of_machine_is_compatible("fsl,imx6ull"))
386 num_clks = IMX6UL_CPUFREQ_CLK_NUM;
388 num_clks = IMX6Q_CPUFREQ_CLK_NUM;
390 ret = clk_bulk_get(cpu_dev, num_clks, clks);
394 arm_reg = regulator_get(cpu_dev, "arm");
395 pu_reg = regulator_get_optional(cpu_dev, "pu");
396 soc_reg = regulator_get(cpu_dev, "soc");
397 if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
398 PTR_ERR(soc_reg) == -EPROBE_DEFER ||
399 PTR_ERR(pu_reg) == -EPROBE_DEFER) {
401 dev_dbg(cpu_dev, "regulators not ready, defer\n");
404 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
405 dev_err(cpu_dev, "failed to get regulators\n");
410 ret = dev_pm_opp_of_add_table(cpu_dev);
412 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
416 if (of_machine_is_compatible("fsl,imx6ul") ||
417 of_machine_is_compatible("fsl,imx6ull")) {
418 ret = imx6ul_opp_check_speed_grading(cpu_dev);
419 if (ret == -EPROBE_DEFER)
422 dev_err(cpu_dev, "failed to read ocotp: %d\n",
427 imx6q_opp_check_speed_grading(cpu_dev);
430 /* Because we have added the OPPs here, we must free them */
432 num = dev_pm_opp_get_opp_count(cpu_dev);
435 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
439 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
441 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
445 /* Make imx6_soc_volt array's size same as arm opp number */
446 imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
448 if (imx6_soc_volt == NULL) {
450 goto free_freq_table;
453 prop = of_find_property(np, "fsl,soc-operating-points", NULL);
454 if (!prop || !prop->value)
458 * Each OPP is a set of tuples consisting of frequency and
459 * voltage like <freq-kHz vol-uV>.
461 nr = prop->length / sizeof(u32);
462 if (nr % 2 || (nr / 2) < num)
465 for (j = 0; j < num; j++) {
467 for (i = 0; i < nr / 2; i++) {
468 unsigned long freq = be32_to_cpup(val++);
469 unsigned long volt = be32_to_cpup(val++);
470 if (freq_table[j].frequency == freq) {
471 imx6_soc_volt[soc_opp_count++] = volt;
478 /* use fixed soc opp volt if no valid soc opp info found in dtb */
479 if (soc_opp_count != num) {
480 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
481 for (j = 0; j < num; j++)
482 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
483 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
484 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
487 if (of_property_read_u32(np, "clock-latency", &transition_latency))
488 transition_latency = CPUFREQ_ETERNAL;
491 * Calculate the ramp time for max voltage change in the
492 * VDDSOC and VDDPU regulators.
494 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
496 transition_latency += ret * 1000;
497 if (!IS_ERR(pu_reg)) {
498 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
500 transition_latency += ret * 1000;
504 * OPP is maintained in order of increasing frequency, and
505 * freq_table initialised from OPP is therefore sorted in the
508 max_freq = freq_table[--num].frequency;
509 opp = dev_pm_opp_find_freq_exact(cpu_dev,
510 freq_table[0].frequency * 1000, true);
511 min_volt = dev_pm_opp_get_voltage(opp);
513 opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
514 max_volt = dev_pm_opp_get_voltage(opp);
517 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
519 transition_latency += ret * 1000;
521 ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
523 dev_err(cpu_dev, "failed register driver: %d\n", ret);
524 goto free_freq_table;
531 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
534 dev_pm_opp_of_remove_table(cpu_dev);
536 if (!IS_ERR(arm_reg))
537 regulator_put(arm_reg);
539 regulator_put(pu_reg);
540 if (!IS_ERR(soc_reg))
541 regulator_put(soc_reg);
543 clk_bulk_put(num_clks, clks);
550 static int imx6q_cpufreq_remove(struct platform_device *pdev)
552 cpufreq_unregister_driver(&imx6q_cpufreq_driver);
553 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
555 dev_pm_opp_of_remove_table(cpu_dev);
556 regulator_put(arm_reg);
558 regulator_put(pu_reg);
559 regulator_put(soc_reg);
561 clk_bulk_put(num_clks, clks);
566 static struct platform_driver imx6q_cpufreq_platdrv = {
568 .name = "imx6q-cpufreq",
570 .probe = imx6q_cpufreq_probe,
571 .remove = imx6q_cpufreq_remove,
573 module_platform_driver(imx6q_cpufreq_platdrv);
575 MODULE_ALIAS("platform:imx6q-cpufreq");
576 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
577 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
578 MODULE_LICENSE("GPL");