1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for Winsystems PC-104 based multifunction IO board.
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 2007 Calin A. Culianu <calin@ajvar.org>
12 * Description: A driver for the PCM-MIO multifunction board
13 * Devices: [Winsystems] PCM-MIO (pcmmio)
14 * Author: Calin Culianu <calin@ajvar.org>
15 * Updated: Wed, May 16 2007 16:21:10 -0500
18 * A driver for the PCM-MIO multifunction board from Winsystems. This
19 * is a PC-104 based I/O board. It contains four subdevices:
21 * subdevice 0 - 16 channels of 16-bit AI
22 * subdevice 1 - 8 channels of 16-bit AO
23 * subdevice 2 - first 24 channels of the 48 channel of DIO
24 * (with edge-triggered interrupt support)
25 * subdevice 3 - last 24 channels of the 48 channel DIO
26 * (no interrupt support for this bank of channels)
30 * Synchronous reads and writes are the only things implemented for analog
31 * input and output. The hardware itself can do streaming acquisition, etc.
33 * Asynchronous I/O for the DIO subdevices *is* implemented, however! They
34 * are basically edge-triggered interrupts for any configuration of the
35 * channels in subdevice 2.
37 * Also note that this interrupt support is untested.
39 * A few words about edge-detection IRQ support (commands on DIO):
41 * To use edge-detection IRQ support for the DIO subdevice, pass the IRQ
42 * of the board to the comedi_config command. The board IRQ is not jumpered
43 * but rather configured through software, so any IRQ from 1-15 is OK.
45 * Due to the genericity of the comedi API, you need to create a special
46 * comedi_command in order to use edge-triggered interrupts for DIO.
48 * Use comedi_commands with TRIG_NOW. Your callback will be called each
49 * time an edge is detected on the specified DIO line(s), and the data
50 * values will be two sample_t's, which should be concatenated to form
51 * one 32-bit unsigned int. This value is the mask of channels that had
52 * edges detected from your channel list. Note that the bits positions
53 * in the mask correspond to positions in your chanlist when you
54 * specified the command and *not* channel id's!
56 * To set the polarity of the edge-detection interrupts pass a nonzero value
57 * for either CR_RANGE or CR_AREF for edge-up polarity, or a zero
58 * value for both CR_RANGE and CR_AREF if you want edge-down polarity.
60 * Configuration Options:
61 * [0] - I/O port base address
62 * [1] - IRQ (optional -- for edge-detect interrupt support only,
63 * leave out if you don't need this feature)
66 #include <linux/module.h>
67 #include <linux/interrupt.h>
68 #include <linux/slab.h>
69 #include <linux/comedi/comedidev.h>
74 #define PCMMIO_AI_LSB_REG 0x00
75 #define PCMMIO_AI_MSB_REG 0x01
76 #define PCMMIO_AI_CMD_REG 0x02
77 #define PCMMIO_AI_CMD_SE BIT(7)
78 #define PCMMIO_AI_CMD_ODD_CHAN BIT(6)
79 #define PCMMIO_AI_CMD_CHAN_SEL(x) (((x) & 0x3) << 4)
80 #define PCMMIO_AI_CMD_RANGE(x) (((x) & 0x3) << 2)
81 #define PCMMIO_RESOURCE_REG 0x02
82 #define PCMMIO_RESOURCE_IRQ(x) (((x) & 0xf) << 0)
83 #define PCMMIO_AI_STATUS_REG 0x03
84 #define PCMMIO_AI_STATUS_DATA_READY BIT(7)
85 #define PCMMIO_AI_STATUS_DATA_DMA_PEND BIT(6)
86 #define PCMMIO_AI_STATUS_CMD_DMA_PEND BIT(5)
87 #define PCMMIO_AI_STATUS_IRQ_PEND BIT(4)
88 #define PCMMIO_AI_STATUS_DATA_DRQ_ENA BIT(2)
89 #define PCMMIO_AI_STATUS_REG_SEL BIT(3)
90 #define PCMMIO_AI_STATUS_CMD_DRQ_ENA BIT(1)
91 #define PCMMIO_AI_STATUS_IRQ_ENA BIT(0)
92 #define PCMMIO_AI_RES_ENA_REG 0x03
93 #define PCMMIO_AI_RES_ENA_CMD_REG_ACCESS (0 << 3)
94 #define PCMMIO_AI_RES_ENA_AI_RES_ACCESS BIT(3)
95 #define PCMMIO_AI_RES_ENA_DIO_RES_ACCESS BIT(4)
96 #define PCMMIO_AI_2ND_ADC_OFFSET 0x04
98 #define PCMMIO_AO_LSB_REG 0x08
99 #define PCMMIO_AO_LSB_SPAN(x) (((x) & 0xf) << 0)
100 #define PCMMIO_AO_MSB_REG 0x09
101 #define PCMMIO_AO_CMD_REG 0x0a
102 #define PCMMIO_AO_CMD_WR_SPAN (0x2 << 4)
103 #define PCMMIO_AO_CMD_WR_CODE (0x3 << 4)
104 #define PCMMIO_AO_CMD_UPDATE (0x4 << 4)
105 #define PCMMIO_AO_CMD_UPDATE_ALL (0x5 << 4)
106 #define PCMMIO_AO_CMD_WR_SPAN_UPDATE (0x6 << 4)
107 #define PCMMIO_AO_CMD_WR_CODE_UPDATE (0x7 << 4)
108 #define PCMMIO_AO_CMD_WR_SPAN_UPDATE_ALL (0x8 << 4)
109 #define PCMMIO_AO_CMD_WR_CODE_UPDATE_ALL (0x9 << 4)
110 #define PCMMIO_AO_CMD_RD_B1_SPAN (0xa << 4)
111 #define PCMMIO_AO_CMD_RD_B1_CODE (0xb << 4)
112 #define PCMMIO_AO_CMD_RD_B2_SPAN (0xc << 4)
113 #define PCMMIO_AO_CMD_RD_B2_CODE (0xd << 4)
114 #define PCMMIO_AO_CMD_NOP (0xf << 4)
115 #define PCMMIO_AO_CMD_CHAN_SEL(x) (((x) & 0x03) << 1)
116 #define PCMMIO_AO_CMD_CHAN_SEL_ALL (0x0f << 0)
117 #define PCMMIO_AO_STATUS_REG 0x0b
118 #define PCMMIO_AO_STATUS_DATA_READY BIT(7)
119 #define PCMMIO_AO_STATUS_DATA_DMA_PEND BIT(6)
120 #define PCMMIO_AO_STATUS_CMD_DMA_PEND BIT(5)
121 #define PCMMIO_AO_STATUS_IRQ_PEND BIT(4)
122 #define PCMMIO_AO_STATUS_DATA_DRQ_ENA BIT(2)
123 #define PCMMIO_AO_STATUS_REG_SEL BIT(3)
124 #define PCMMIO_AO_STATUS_CMD_DRQ_ENA BIT(1)
125 #define PCMMIO_AO_STATUS_IRQ_ENA BIT(0)
126 #define PCMMIO_AO_RESOURCE_ENA_REG 0x0b
127 #define PCMMIO_AO_2ND_DAC_OFFSET 0x04
132 * Offset Page 0 Page 1 Page 2 Page 3
133 * ------ ----------- ----------- ----------- -----------
134 * 0x10 Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O
135 * 0x11 Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O
136 * 0x12 Port 2 I/O Port 2 I/O Port 2 I/O Port 2 I/O
137 * 0x13 Port 3 I/O Port 3 I/O Port 3 I/O Port 3 I/O
138 * 0x14 Port 4 I/O Port 4 I/O Port 4 I/O Port 4 I/O
139 * 0x15 Port 5 I/O Port 5 I/O Port 5 I/O Port 5 I/O
140 * 0x16 INT_PENDING INT_PENDING INT_PENDING INT_PENDING
141 * 0x17 Page/Lock Page/Lock Page/Lock Page/Lock
142 * 0x18 N/A POL_0 ENAB_0 INT_ID0
143 * 0x19 N/A POL_1 ENAB_1 INT_ID1
144 * 0x1a N/A POL_2 ENAB_2 INT_ID2
146 #define PCMMIO_PORT_REG(x) (0x10 + (x))
147 #define PCMMIO_INT_PENDING_REG 0x16
148 #define PCMMIO_PAGE_LOCK_REG 0x17
149 #define PCMMIO_LOCK_PORT(x) ((1 << (x)) & 0x3f)
150 #define PCMMIO_PAGE(x) (((x) & 0x3) << 6)
151 #define PCMMIO_PAGE_MASK PCMUIO_PAGE(3)
152 #define PCMMIO_PAGE_POL 1
153 #define PCMMIO_PAGE_ENAB 2
154 #define PCMMIO_PAGE_INT_ID 3
155 #define PCMMIO_PAGE_REG(x) (0x18 + (x))
157 static const struct comedi_lrange pcmmio_ai_ranges = {
166 static const struct comedi_lrange pcmmio_ao_ranges = {
177 struct pcmmio_private {
178 spinlock_t pagelock; /* protects the page registers */
179 spinlock_t spinlock; /* protects the member variables */
180 unsigned int enabled_mask;
181 unsigned int active:1;
184 static void pcmmio_dio_write(struct comedi_device *dev, unsigned int val,
187 struct pcmmio_private *devpriv = dev->private;
188 unsigned long iobase = dev->iobase;
191 spin_lock_irqsave(&devpriv->pagelock, flags);
193 /* Port registers are valid for any page */
194 outb(val & 0xff, iobase + PCMMIO_PORT_REG(port + 0));
195 outb((val >> 8) & 0xff, iobase + PCMMIO_PORT_REG(port + 1));
196 outb((val >> 16) & 0xff, iobase + PCMMIO_PORT_REG(port + 2));
198 outb(PCMMIO_PAGE(page), iobase + PCMMIO_PAGE_LOCK_REG);
199 outb(val & 0xff, iobase + PCMMIO_PAGE_REG(0));
200 outb((val >> 8) & 0xff, iobase + PCMMIO_PAGE_REG(1));
201 outb((val >> 16) & 0xff, iobase + PCMMIO_PAGE_REG(2));
203 spin_unlock_irqrestore(&devpriv->pagelock, flags);
206 static unsigned int pcmmio_dio_read(struct comedi_device *dev,
209 struct pcmmio_private *devpriv = dev->private;
210 unsigned long iobase = dev->iobase;
214 spin_lock_irqsave(&devpriv->pagelock, flags);
216 /* Port registers are valid for any page */
217 val = inb(iobase + PCMMIO_PORT_REG(port + 0));
218 val |= (inb(iobase + PCMMIO_PORT_REG(port + 1)) << 8);
219 val |= (inb(iobase + PCMMIO_PORT_REG(port + 2)) << 16);
221 outb(PCMMIO_PAGE(page), iobase + PCMMIO_PAGE_LOCK_REG);
222 val = inb(iobase + PCMMIO_PAGE_REG(0));
223 val |= (inb(iobase + PCMMIO_PAGE_REG(1)) << 8);
224 val |= (inb(iobase + PCMMIO_PAGE_REG(2)) << 16);
226 spin_unlock_irqrestore(&devpriv->pagelock, flags);
232 * Each channel can be individually programmed for input or output.
233 * Writing a '0' to a channel causes the corresponding output pin
234 * to go to a high-z state (pulled high by an external 10K resistor).
235 * This allows it to be used as an input. When used in the input mode,
236 * a read reflects the inverted state of the I/O pin, such that a
237 * high on the pin will read as a '0' in the register. Writing a '1'
238 * to a bit position causes the pin to sink current (up to 12mA),
239 * effectively pulling it low.
241 static int pcmmio_dio_insn_bits(struct comedi_device *dev,
242 struct comedi_subdevice *s,
243 struct comedi_insn *insn,
246 /* subdevice 2 uses ports 0-2, subdevice 3 uses ports 3-5 */
247 int port = s->index == 2 ? 0 : 3;
248 unsigned int chanmask = (1 << s->n_chan) - 1;
252 mask = comedi_dio_update_state(s, data);
255 * Outputs are inverted, invert the state and
256 * update the channels.
258 * The s->io_bits mask makes sure the input channels
259 * are '0' so that the outputs pins stay in a high
262 val = ~s->state & chanmask;
264 pcmmio_dio_write(dev, val, 0, port);
267 /* get inverted state of the channels from the port */
268 val = pcmmio_dio_read(dev, 0, port);
270 /* return the true state of the channels */
271 data[1] = ~val & chanmask;
276 static int pcmmio_dio_insn_config(struct comedi_device *dev,
277 struct comedi_subdevice *s,
278 struct comedi_insn *insn,
281 /* subdevice 2 uses ports 0-2, subdevice 3 uses ports 3-5 */
282 int port = s->index == 2 ? 0 : 3;
285 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
289 if (data[0] == INSN_CONFIG_DIO_INPUT)
290 pcmmio_dio_write(dev, s->io_bits, 0, port);
295 static void pcmmio_reset(struct comedi_device *dev)
297 /* Clear all the DIO port bits */
298 pcmmio_dio_write(dev, 0, 0, 0);
299 pcmmio_dio_write(dev, 0, 0, 3);
301 /* Clear all the paged registers */
302 pcmmio_dio_write(dev, 0, PCMMIO_PAGE_POL, 0);
303 pcmmio_dio_write(dev, 0, PCMMIO_PAGE_ENAB, 0);
304 pcmmio_dio_write(dev, 0, PCMMIO_PAGE_INT_ID, 0);
307 /* devpriv->spinlock is already locked */
308 static void pcmmio_stop_intr(struct comedi_device *dev,
309 struct comedi_subdevice *s)
311 struct pcmmio_private *devpriv = dev->private;
313 devpriv->enabled_mask = 0;
315 s->async->inttrig = NULL;
317 /* disable all dio interrupts */
318 pcmmio_dio_write(dev, 0, PCMMIO_PAGE_ENAB, 0);
321 static void pcmmio_handle_dio_intr(struct comedi_device *dev,
322 struct comedi_subdevice *s,
323 unsigned int triggered)
325 struct pcmmio_private *devpriv = dev->private;
326 struct comedi_cmd *cmd = &s->async->cmd;
327 unsigned int val = 0;
331 spin_lock_irqsave(&devpriv->spinlock, flags);
333 if (!devpriv->active)
336 if (!(triggered & devpriv->enabled_mask))
339 for (i = 0; i < cmd->chanlist_len; i++) {
340 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
342 if (triggered & (1 << chan))
346 comedi_buf_write_samples(s, &val, 1);
348 if (cmd->stop_src == TRIG_COUNT &&
349 s->async->scans_done >= cmd->stop_arg)
350 s->async->events |= COMEDI_CB_EOA;
353 spin_unlock_irqrestore(&devpriv->spinlock, flags);
355 comedi_handle_events(dev, s);
358 static irqreturn_t interrupt_pcmmio(int irq, void *d)
360 struct comedi_device *dev = d;
361 struct comedi_subdevice *s = dev->read_subdev;
362 unsigned int triggered;
363 unsigned char int_pend;
365 /* are there any interrupts pending */
366 int_pend = inb(dev->iobase + PCMMIO_INT_PENDING_REG) & 0x07;
370 /* get, and clear, the pending interrupts */
371 triggered = pcmmio_dio_read(dev, PCMMIO_PAGE_INT_ID, 0);
372 pcmmio_dio_write(dev, 0, PCMMIO_PAGE_INT_ID, 0);
374 pcmmio_handle_dio_intr(dev, s, triggered);
379 /* devpriv->spinlock is already locked */
380 static void pcmmio_start_intr(struct comedi_device *dev,
381 struct comedi_subdevice *s)
383 struct pcmmio_private *devpriv = dev->private;
384 struct comedi_cmd *cmd = &s->async->cmd;
385 unsigned int bits = 0;
386 unsigned int pol_bits = 0;
389 devpriv->enabled_mask = 0;
392 for (i = 0; i < cmd->chanlist_len; i++) {
393 unsigned int chanspec = cmd->chanlist[i];
394 unsigned int chan = CR_CHAN(chanspec);
395 unsigned int range = CR_RANGE(chanspec);
396 unsigned int aref = CR_AREF(chanspec);
399 pol_bits |= (((aref || range) ? 1 : 0) << chan);
402 bits &= ((1 << s->n_chan) - 1);
403 devpriv->enabled_mask = bits;
405 /* set polarity and enable interrupts */
406 pcmmio_dio_write(dev, pol_bits, PCMMIO_PAGE_POL, 0);
407 pcmmio_dio_write(dev, bits, PCMMIO_PAGE_ENAB, 0);
410 static int pcmmio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
412 struct pcmmio_private *devpriv = dev->private;
415 spin_lock_irqsave(&devpriv->spinlock, flags);
417 pcmmio_stop_intr(dev, s);
418 spin_unlock_irqrestore(&devpriv->spinlock, flags);
423 static int pcmmio_inttrig_start_intr(struct comedi_device *dev,
424 struct comedi_subdevice *s,
425 unsigned int trig_num)
427 struct pcmmio_private *devpriv = dev->private;
428 struct comedi_cmd *cmd = &s->async->cmd;
431 if (trig_num != cmd->start_arg)
434 spin_lock_irqsave(&devpriv->spinlock, flags);
435 s->async->inttrig = NULL;
437 pcmmio_start_intr(dev, s);
438 spin_unlock_irqrestore(&devpriv->spinlock, flags);
444 * 'do_cmd' function for an 'INTERRUPT' subdevice.
446 static int pcmmio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
448 struct pcmmio_private *devpriv = dev->private;
449 struct comedi_cmd *cmd = &s->async->cmd;
452 spin_lock_irqsave(&devpriv->spinlock, flags);
455 /* Set up start of acquisition. */
456 if (cmd->start_src == TRIG_INT)
457 s->async->inttrig = pcmmio_inttrig_start_intr;
459 pcmmio_start_intr(dev, s);
461 spin_unlock_irqrestore(&devpriv->spinlock, flags);
466 static int pcmmio_cmdtest(struct comedi_device *dev,
467 struct comedi_subdevice *s,
468 struct comedi_cmd *cmd)
472 /* Step 1 : check if triggers are trivially valid */
474 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
475 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
476 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
477 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
478 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
483 /* Step 2a : make sure trigger sources are unique */
485 err |= comedi_check_trigger_is_unique(cmd->start_src);
486 err |= comedi_check_trigger_is_unique(cmd->stop_src);
488 /* Step 2b : and mutually compatible */
493 /* Step 3: check if arguments are trivially valid */
495 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
496 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
497 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
498 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
501 if (cmd->stop_src == TRIG_COUNT)
502 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
504 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
509 /* step 4: fix up any arguments */
511 /* if (err) return 4; */
516 static int pcmmio_ai_eoc(struct comedi_device *dev,
517 struct comedi_subdevice *s,
518 struct comedi_insn *insn,
519 unsigned long context)
521 unsigned char status;
523 status = inb(dev->iobase + PCMMIO_AI_STATUS_REG);
524 if (status & PCMMIO_AI_STATUS_DATA_READY)
529 static int pcmmio_ai_insn_read(struct comedi_device *dev,
530 struct comedi_subdevice *s,
531 struct comedi_insn *insn,
534 unsigned long iobase = dev->iobase;
535 unsigned int chan = CR_CHAN(insn->chanspec);
536 unsigned int range = CR_RANGE(insn->chanspec);
537 unsigned int aref = CR_AREF(insn->chanspec);
538 unsigned char cmd = 0;
544 * The PCM-MIO uses two Linear Tech LTC1859CG 8-channel A/D converters.
545 * The devices use a full duplex serial interface which transmits and
546 * receives data simultaneously. An 8-bit command is shifted into the
547 * ADC interface to configure it for the next conversion. At the same
548 * time, the data from the previous conversion is shifted out of the
549 * device. Consequently, the conversion result is delayed by one
550 * conversion from the command word.
552 * Setup the cmd for the conversions then do a dummy conversion to
553 * flush the junk data. Then do each conversion requested by the
554 * comedi_insn. Note that the last conversion will leave junk data
555 * in ADC which will get flushed on the next comedi_insn.
560 iobase += PCMMIO_AI_2ND_ADC_OFFSET;
563 if (aref == AREF_GROUND)
564 cmd |= PCMMIO_AI_CMD_SE;
566 cmd |= PCMMIO_AI_CMD_ODD_CHAN;
567 cmd |= PCMMIO_AI_CMD_CHAN_SEL(chan / 2);
568 cmd |= PCMMIO_AI_CMD_RANGE(range);
570 outb(cmd, iobase + PCMMIO_AI_CMD_REG);
572 ret = comedi_timeout(dev, s, insn, pcmmio_ai_eoc, 0);
576 val = inb(iobase + PCMMIO_AI_LSB_REG);
577 val |= inb(iobase + PCMMIO_AI_MSB_REG) << 8;
579 for (i = 0; i < insn->n; i++) {
580 outb(cmd, iobase + PCMMIO_AI_CMD_REG);
582 ret = comedi_timeout(dev, s, insn, pcmmio_ai_eoc, 0);
586 val = inb(iobase + PCMMIO_AI_LSB_REG);
587 val |= inb(iobase + PCMMIO_AI_MSB_REG) << 8;
589 /* bipolar data is two's complement */
590 if (comedi_range_is_bipolar(s, range))
591 val = comedi_offset_munge(s, val);
599 static int pcmmio_ao_eoc(struct comedi_device *dev,
600 struct comedi_subdevice *s,
601 struct comedi_insn *insn,
602 unsigned long context)
604 unsigned char status;
606 status = inb(dev->iobase + PCMMIO_AO_STATUS_REG);
607 if (status & PCMMIO_AO_STATUS_DATA_READY)
612 static int pcmmio_ao_insn_write(struct comedi_device *dev,
613 struct comedi_subdevice *s,
614 struct comedi_insn *insn,
617 unsigned long iobase = dev->iobase;
618 unsigned int chan = CR_CHAN(insn->chanspec);
619 unsigned int range = CR_RANGE(insn->chanspec);
620 unsigned char cmd = 0;
625 * The PCM-MIO has two Linear Tech LTC2704 DAC devices. Each device
626 * is a 4-channel converter with software-selectable output range.
630 cmd |= PCMMIO_AO_CMD_CHAN_SEL(chan - 4);
631 iobase += PCMMIO_AO_2ND_DAC_OFFSET;
633 cmd |= PCMMIO_AO_CMD_CHAN_SEL(chan);
636 /* set the range for the channel */
637 outb(PCMMIO_AO_LSB_SPAN(range), iobase + PCMMIO_AO_LSB_REG);
638 outb(0, iobase + PCMMIO_AO_MSB_REG);
639 outb(cmd | PCMMIO_AO_CMD_WR_SPAN_UPDATE, iobase + PCMMIO_AO_CMD_REG);
641 ret = comedi_timeout(dev, s, insn, pcmmio_ao_eoc, 0);
645 for (i = 0; i < insn->n; i++) {
646 unsigned int val = data[i];
648 /* write the data to the channel */
649 outb(val & 0xff, iobase + PCMMIO_AO_LSB_REG);
650 outb((val >> 8) & 0xff, iobase + PCMMIO_AO_MSB_REG);
651 outb(cmd | PCMMIO_AO_CMD_WR_CODE_UPDATE,
652 iobase + PCMMIO_AO_CMD_REG);
654 ret = comedi_timeout(dev, s, insn, pcmmio_ao_eoc, 0);
658 s->readback[chan] = val;
664 static int pcmmio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
666 struct pcmmio_private *devpriv;
667 struct comedi_subdevice *s;
670 ret = comedi_request_region(dev, it->options[0], 32);
674 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
678 spin_lock_init(&devpriv->pagelock);
679 spin_lock_init(&devpriv->spinlock);
683 if (it->options[1]) {
684 ret = request_irq(it->options[1], interrupt_pcmmio, 0,
685 dev->board_name, dev);
687 dev->irq = it->options[1];
689 /* configure the interrupt routing on the board */
690 outb(PCMMIO_AI_RES_ENA_DIO_RES_ACCESS,
691 dev->iobase + PCMMIO_AI_RES_ENA_REG);
692 outb(PCMMIO_RESOURCE_IRQ(dev->irq),
693 dev->iobase + PCMMIO_RESOURCE_REG);
697 ret = comedi_alloc_subdevices(dev, 4);
701 /* Analog Input subdevice */
702 s = &dev->subdevices[0];
703 s->type = COMEDI_SUBD_AI;
704 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF;
707 s->range_table = &pcmmio_ai_ranges;
708 s->insn_read = pcmmio_ai_insn_read;
710 /* initialize the resource enable register by clearing it */
711 outb(PCMMIO_AI_RES_ENA_CMD_REG_ACCESS,
712 dev->iobase + PCMMIO_AI_RES_ENA_REG);
713 outb(PCMMIO_AI_RES_ENA_CMD_REG_ACCESS,
714 dev->iobase + PCMMIO_AI_RES_ENA_REG + PCMMIO_AI_2ND_ADC_OFFSET);
716 /* Analog Output subdevice */
717 s = &dev->subdevices[1];
718 s->type = COMEDI_SUBD_AO;
719 s->subdev_flags = SDF_READABLE;
722 s->range_table = &pcmmio_ao_ranges;
723 s->insn_write = pcmmio_ao_insn_write;
725 ret = comedi_alloc_subdev_readback(s);
729 /* initialize the resource enable register by clearing it */
730 outb(0, dev->iobase + PCMMIO_AO_RESOURCE_ENA_REG);
731 outb(0, dev->iobase + PCMMIO_AO_2ND_DAC_OFFSET +
732 PCMMIO_AO_RESOURCE_ENA_REG);
734 /* Digital I/O subdevice with interrupt support */
735 s = &dev->subdevices[2];
736 s->type = COMEDI_SUBD_DIO;
737 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
741 s->range_table = &range_digital;
742 s->insn_bits = pcmmio_dio_insn_bits;
743 s->insn_config = pcmmio_dio_insn_config;
745 dev->read_subdev = s;
746 s->subdev_flags |= SDF_CMD_READ | SDF_LSAMPL | SDF_PACKED;
747 s->len_chanlist = s->n_chan;
748 s->cancel = pcmmio_cancel;
749 s->do_cmd = pcmmio_cmd;
750 s->do_cmdtest = pcmmio_cmdtest;
753 /* Digital I/O subdevice */
754 s = &dev->subdevices[3];
755 s->type = COMEDI_SUBD_DIO;
756 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
759 s->range_table = &range_digital;
760 s->insn_bits = pcmmio_dio_insn_bits;
761 s->insn_config = pcmmio_dio_insn_config;
766 static struct comedi_driver pcmmio_driver = {
767 .driver_name = "pcmmio",
768 .module = THIS_MODULE,
769 .attach = pcmmio_attach,
770 .detach = comedi_legacy_detach,
772 module_comedi_driver(pcmmio_driver);
774 MODULE_AUTHOR("Comedi https://www.comedi.org");
775 MODULE_DESCRIPTION("Comedi driver for Winsystems PCM-MIO PC/104 board");
776 MODULE_LICENSE("GPL");