1 // SPDX-License-Identifier: GPL-2.0+
3 * Support for NI general purpose counters
5 * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
10 * Description: National Instruments general purpose counters
11 * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
12 * Herman.Bruyninckx@mech.kuleuven.ac.be,
13 * Wim.Meeussen@mech.kuleuven.ac.be,
14 * Klaas.Gadeyne@mech.kuleuven.ac.be,
15 * Frank Mori Hess <fmhess@users.sourceforge.net>
16 * Updated: Thu Nov 16 09:50:32 EST 2006
19 * This module is not used directly by end-users. Rather, it
20 * is used by other drivers (for example ni_660x and ni_pcimio)
21 * to provide support for NI's general purpose counters. It was
22 * originally based on the counter code from ni_660x.c and
26 * DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
27 * DAQ 6601/6602 User Manual (NI 322137B-01)
28 * 340934b.pdf DAQ-STC reference manual
30 * TODO: Support use of both banks X and Y
33 #include <linux/module.h>
34 #include <linux/slab.h>
36 #include "ni_tio_internal.h"
39 * clock sources for ni e and m series boards,
40 * get bits with GI_SRC_SEL()
42 #define NI_M_TIMEBASE_1_CLK 0x0 /* 20MHz */
43 #define NI_M_PFI_CLK(x) (((x) < 10) ? (1 + (x)) : (0xb + (x)))
44 #define NI_M_RTSI_CLK(x) (((x) == 7) ? 0x1b : (0xb + (x)))
45 #define NI_M_TIMEBASE_2_CLK 0x12 /* 100KHz */
46 #define NI_M_NEXT_TC_CLK 0x13
47 #define NI_M_NEXT_GATE_CLK 0x14 /* Gi_Src_SubSelect=0 */
48 #define NI_M_PXI_STAR_TRIGGER_CLK 0x14 /* Gi_Src_SubSelect=1 */
49 #define NI_M_PXI10_CLK 0x1d
50 #define NI_M_TIMEBASE_3_CLK 0x1e /* 80MHz, Gi_Src_SubSelect=0 */
51 #define NI_M_ANALOG_TRIGGER_OUT_CLK 0x1e /* Gi_Src_SubSelect=1 */
52 #define NI_M_LOGIC_LOW_CLK 0x1f
53 #define NI_M_MAX_PFI_CHAN 15
54 #define NI_M_MAX_RTSI_CHAN 7
57 * clock sources for ni_660x boards,
58 * get bits with GI_SRC_SEL()
60 #define NI_660X_TIMEBASE_1_CLK 0x0 /* 20MHz */
61 #define NI_660X_SRC_PIN_I_CLK 0x1
62 #define NI_660X_SRC_PIN_CLK(x) (0x2 + (x))
63 #define NI_660X_NEXT_GATE_CLK 0xa
64 #define NI_660X_RTSI_CLK(x) (0xb + (x))
65 #define NI_660X_TIMEBASE_2_CLK 0x12 /* 100KHz */
66 #define NI_660X_NEXT_TC_CLK 0x13
67 #define NI_660X_TIMEBASE_3_CLK 0x1e /* 80MHz */
68 #define NI_660X_LOGIC_LOW_CLK 0x1f
69 #define NI_660X_MAX_SRC_PIN 7
70 #define NI_660X_MAX_RTSI_CHAN 6
72 /* ni m series gate_select */
73 #define NI_M_TIMESTAMP_MUX_GATE_SEL 0x0
74 #define NI_M_PFI_GATE_SEL(x) (((x) < 10) ? (1 + (x)) : (0xb + (x)))
75 #define NI_M_RTSI_GATE_SEL(x) (((x) == 7) ? 0x1b : (0xb + (x)))
76 #define NI_M_AI_START2_GATE_SEL 0x12
77 #define NI_M_PXI_STAR_TRIGGER_GATE_SEL 0x13
78 #define NI_M_NEXT_OUT_GATE_SEL 0x14
79 #define NI_M_AI_START1_GATE_SEL 0x1c
80 #define NI_M_NEXT_SRC_GATE_SEL 0x1d
81 #define NI_M_ANALOG_TRIG_OUT_GATE_SEL 0x1e
82 #define NI_M_LOGIC_LOW_GATE_SEL 0x1f
84 /* ni_660x gate select */
85 #define NI_660X_SRC_PIN_I_GATE_SEL 0x0
86 #define NI_660X_GATE_PIN_I_GATE_SEL 0x1
87 #define NI_660X_PIN_GATE_SEL(x) (0x2 + (x))
88 #define NI_660X_NEXT_SRC_GATE_SEL 0xa
89 #define NI_660X_RTSI_GATE_SEL(x) (0xb + (x))
90 #define NI_660X_NEXT_OUT_GATE_SEL 0x14
91 #define NI_660X_LOGIC_LOW_GATE_SEL 0x1f
92 #define NI_660X_MAX_GATE_PIN 7
94 /* ni_660x second gate select */
95 #define NI_660X_SRC_PIN_I_GATE2_SEL 0x0
96 #define NI_660X_UD_PIN_I_GATE2_SEL 0x1
97 #define NI_660X_UD_PIN_GATE2_SEL(x) (0x2 + (x))
98 #define NI_660X_NEXT_SRC_GATE2_SEL 0xa
99 #define NI_660X_RTSI_GATE2_SEL(x) (0xb + (x))
100 #define NI_660X_NEXT_OUT_GATE2_SEL 0x14
101 #define NI_660X_SELECTED_GATE2_SEL 0x1e
102 #define NI_660X_LOGIC_LOW_GATE2_SEL 0x1f
103 #define NI_660X_MAX_UP_DOWN_PIN 7
105 static inline unsigned int GI_PRESCALE_X2(enum ni_gpct_variant variant)
108 case ni_gpct_variant_e_series:
111 case ni_gpct_variant_m_series:
112 return GI_M_PRESCALE_X2;
113 case ni_gpct_variant_660x:
114 return GI_660X_PRESCALE_X2;
118 static inline unsigned int GI_PRESCALE_X8(enum ni_gpct_variant variant)
121 case ni_gpct_variant_e_series:
124 case ni_gpct_variant_m_series:
125 return GI_M_PRESCALE_X8;
126 case ni_gpct_variant_660x:
127 return GI_660X_PRESCALE_X8;
131 static bool ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev)
133 switch (counter_dev->variant) {
134 case ni_gpct_variant_e_series:
137 case ni_gpct_variant_m_series:
138 case ni_gpct_variant_660x:
144 * ni_tio_write() - Write a TIO register using the driver provided callback.
145 * @counter: struct ni_gpct counter.
146 * @value: the value to write
147 * @reg: the register to write.
149 void ni_tio_write(struct ni_gpct *counter, unsigned int value,
150 enum ni_gpct_register reg)
152 if (reg < NITIO_NUM_REGS)
153 counter->counter_dev->write(counter, value, reg);
155 EXPORT_SYMBOL_GPL(ni_tio_write);
158 * ni_tio_read() - Read a TIO register using the driver provided callback.
159 * @counter: struct ni_gpct counter.
160 * @reg: the register to read.
162 unsigned int ni_tio_read(struct ni_gpct *counter, enum ni_gpct_register reg)
164 if (reg < NITIO_NUM_REGS)
165 return counter->counter_dev->read(counter, reg);
168 EXPORT_SYMBOL_GPL(ni_tio_read);
170 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
172 unsigned int cidx = counter->counter_index;
174 ni_tio_write(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx));
177 static int ni_tio_clock_period_ps(const struct ni_gpct *counter,
178 unsigned int generic_clock_source,
183 switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
184 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
185 clock_period_ps = 50000;
187 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
188 clock_period_ps = 10000000;
190 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
191 clock_period_ps = 12500;
193 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
194 clock_period_ps = 100000;
198 * clock period is specified by user with prescaling
199 * already taken into account.
201 *period_ps = counter->clock_period_ps;
205 switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
206 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
208 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
209 clock_period_ps *= 2;
211 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
212 clock_period_ps *= 8;
217 *period_ps = clock_period_ps;
221 static void ni_tio_set_bits_transient(struct ni_gpct *counter,
222 enum ni_gpct_register reg,
223 unsigned int mask, unsigned int value,
224 unsigned int transient)
226 struct ni_gpct_device *counter_dev = counter->counter_dev;
227 unsigned int chip = counter->chip_index;
230 if (reg < NITIO_NUM_REGS && chip < counter_dev->num_chips) {
231 unsigned int *regs = counter_dev->regs[chip];
233 spin_lock_irqsave(&counter_dev->regs_lock, flags);
235 regs[reg] |= (value & mask);
236 ni_tio_write(counter, regs[reg] | transient, reg);
237 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
242 * ni_tio_set_bits() - Safely write a counter register.
243 * @counter: struct ni_gpct counter.
244 * @reg: the register to write.
245 * @mask: the bits to change.
246 * @value: the new bits value.
248 * Used to write to, and update the software copy, a register whose bits may
249 * be twiddled in interrupt context, or whose software copy may be read in
252 void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg,
253 unsigned int mask, unsigned int value)
255 ni_tio_set_bits_transient(counter, reg, mask, value, 0x0);
257 EXPORT_SYMBOL_GPL(ni_tio_set_bits);
260 * ni_tio_get_soft_copy() - Safely read the software copy of a counter register.
261 * @counter: struct ni_gpct counter.
262 * @reg: the register to read.
264 * Used to get the software copy of a register whose bits might be modified
265 * in interrupt context, or whose software copy might need to be read in
268 unsigned int ni_tio_get_soft_copy(const struct ni_gpct *counter,
269 enum ni_gpct_register reg)
271 struct ni_gpct_device *counter_dev = counter->counter_dev;
272 unsigned int chip = counter->chip_index;
273 unsigned int value = 0;
276 if (reg < NITIO_NUM_REGS && chip < counter_dev->num_chips) {
277 spin_lock_irqsave(&counter_dev->regs_lock, flags);
278 value = counter_dev->regs[chip][reg];
279 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
283 EXPORT_SYMBOL_GPL(ni_tio_get_soft_copy);
285 static unsigned int ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
287 struct ni_gpct_device *counter_dev = counter->counter_dev;
288 unsigned int cidx = counter->counter_index;
289 unsigned int counting_mode_bits =
290 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
291 unsigned int bits = 0;
293 if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
295 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
296 if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant))
297 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
298 if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant))
299 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
303 static int ni_m_series_clock_src_select(const struct ni_gpct *counter,
304 unsigned int *clk_src)
306 struct ni_gpct_device *counter_dev = counter->counter_dev;
307 unsigned int cidx = counter->counter_index;
308 unsigned int chip = counter->chip_index;
309 unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
310 unsigned int clock_source = 0;
314 src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
315 NITIO_INPUT_SEL_REG(cidx)));
318 case NI_M_TIMEBASE_1_CLK:
319 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
321 case NI_M_TIMEBASE_2_CLK:
322 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
324 case NI_M_TIMEBASE_3_CLK:
325 if (counter_dev->regs[chip][second_gate_reg] & GI_SRC_SUBSEL)
327 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
329 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
331 case NI_M_LOGIC_LOW_CLK:
332 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
334 case NI_M_NEXT_GATE_CLK:
335 if (counter_dev->regs[chip][second_gate_reg] & GI_SRC_SUBSEL)
336 clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
338 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
341 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
343 case NI_M_NEXT_TC_CLK:
344 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
347 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
348 if (src == NI_M_RTSI_CLK(i)) {
349 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
353 if (i <= NI_M_MAX_RTSI_CHAN)
355 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
356 if (src == NI_M_PFI_CLK(i)) {
357 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
361 if (i <= NI_M_MAX_PFI_CHAN)
365 clock_source |= ni_tio_clock_src_modifiers(counter);
366 *clk_src = clock_source;
370 static int ni_660x_clock_src_select(const struct ni_gpct *counter,
371 unsigned int *clk_src)
373 unsigned int clock_source = 0;
374 unsigned int cidx = counter->counter_index;
378 src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
379 NITIO_INPUT_SEL_REG(cidx)));
382 case NI_660X_TIMEBASE_1_CLK:
383 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
385 case NI_660X_TIMEBASE_2_CLK:
386 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
388 case NI_660X_TIMEBASE_3_CLK:
389 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
391 case NI_660X_LOGIC_LOW_CLK:
392 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
394 case NI_660X_SRC_PIN_I_CLK:
395 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
397 case NI_660X_NEXT_GATE_CLK:
398 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
400 case NI_660X_NEXT_TC_CLK:
401 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
404 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
405 if (src == NI_660X_RTSI_CLK(i)) {
406 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
410 if (i <= NI_660X_MAX_RTSI_CHAN)
412 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
413 if (src == NI_660X_SRC_PIN_CLK(i)) {
415 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
419 if (i <= NI_660X_MAX_SRC_PIN)
423 clock_source |= ni_tio_clock_src_modifiers(counter);
424 *clk_src = clock_source;
428 static int ni_tio_generic_clock_src_select(const struct ni_gpct *counter,
429 unsigned int *clk_src)
431 switch (counter->counter_dev->variant) {
432 case ni_gpct_variant_e_series:
433 case ni_gpct_variant_m_series:
435 return ni_m_series_clock_src_select(counter, clk_src);
436 case ni_gpct_variant_660x:
437 return ni_660x_clock_src_select(counter, clk_src);
441 static void ni_tio_set_sync_mode(struct ni_gpct *counter)
443 struct ni_gpct_device *counter_dev = counter->counter_dev;
444 unsigned int cidx = counter->counter_index;
445 static const u64 min_normal_sync_period_ps = 25000;
446 unsigned int mask = 0;
447 unsigned int bits = 0;
450 unsigned int clk_src = 0;
455 /* only m series and 660x variants have counting mode registers */
456 switch (counter_dev->variant) {
457 case ni_gpct_variant_e_series:
460 case ni_gpct_variant_m_series:
461 mask = GI_M_ALT_SYNC;
463 case ni_gpct_variant_660x:
464 mask = GI_660X_ALT_SYNC;
468 reg = NITIO_CNT_MODE_REG(cidx);
469 mode = ni_tio_get_soft_copy(counter, reg);
470 switch (mode & GI_CNT_MODE_MASK) {
471 case GI_CNT_MODE_QUADX1:
472 case GI_CNT_MODE_QUADX2:
473 case GI_CNT_MODE_QUADX4:
474 case GI_CNT_MODE_SYNC_SRC:
475 force_alt_sync = true;
478 force_alt_sync = false;
482 ret = ni_tio_generic_clock_src_select(counter, &clk_src);
485 ret = ni_tio_clock_period_ps(counter, clk_src, &ps);
489 * It's not clear what we should do if clock_period is unknown, so we
490 * are not using the alt sync bit in that case.
492 if (force_alt_sync || (ps && ps < min_normal_sync_period_ps))
495 ni_tio_set_bits(counter, reg, mask, bits);
498 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned int mode)
500 struct ni_gpct_device *counter_dev = counter->counter_dev;
501 unsigned int cidx = counter->counter_index;
502 unsigned int mode_reg_mask;
503 unsigned int mode_reg_values;
504 unsigned int input_select_bits = 0;
505 /* these bits map directly on to the mode register */
506 static const unsigned int mode_reg_direct_mask =
507 NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
508 NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
509 NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
510 NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
512 mode_reg_mask = mode_reg_direct_mask | GI_RELOAD_SRC_SWITCHING;
513 mode_reg_values = mode & mode_reg_direct_mask;
514 switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
515 case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
517 case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
518 mode_reg_values |= GI_RELOAD_SRC_SWITCHING;
520 case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
521 input_select_bits |= GI_GATE_SEL_LOAD_SRC;
522 mode_reg_mask |= GI_GATING_MODE_MASK;
523 mode_reg_values |= GI_LEVEL_GATING;
528 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
529 mode_reg_mask, mode_reg_values);
531 if (ni_tio_counting_mode_registers_present(counter_dev)) {
532 unsigned int bits = 0;
534 bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT);
535 bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT));
536 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
537 bits |= GI_INDEX_MODE;
538 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
539 GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK |
540 GI_INDEX_MODE, bits);
541 ni_tio_set_sync_mode(counter);
544 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_CNT_DIR_MASK,
545 GI_CNT_DIR(mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT));
547 if (mode & NI_GPCT_OR_GATE_BIT)
548 input_select_bits |= GI_OR_GATE;
549 if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
550 input_select_bits |= GI_OUTPUT_POL_INVERT;
551 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
552 GI_GATE_SEL_LOAD_SRC | GI_OR_GATE |
553 GI_OUTPUT_POL_INVERT, input_select_bits);
558 int ni_tio_arm(struct ni_gpct *counter, bool arm, unsigned int start_trigger)
560 struct ni_gpct_device *counter_dev = counter->counter_dev;
561 unsigned int cidx = counter->counter_index;
562 unsigned int transient_bits = 0;
565 unsigned int mask = 0;
566 unsigned int bits = 0;
568 /* only m series and 660x have counting mode registers */
569 switch (counter_dev->variant) {
570 case ni_gpct_variant_e_series:
573 case ni_gpct_variant_m_series:
574 mask = GI_M_HW_ARM_SEL_MASK;
576 case ni_gpct_variant_660x:
577 mask = GI_660X_HW_ARM_SEL_MASK;
581 switch (start_trigger) {
582 case NI_GPCT_ARM_IMMEDIATE:
583 transient_bits |= GI_ARM;
585 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
586 transient_bits |= GI_ARM | GI_ARM_COPY;
590 * for m series and 660x, pass-through the least
591 * significant bits so we can figure out what select
594 if (mask && (start_trigger & NI_GPCT_ARM_UNKNOWN)) {
595 bits |= GI_HW_ARM_ENA |
596 (GI_HW_ARM_SEL(start_trigger) & mask);
604 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
605 GI_HW_ARM_ENA | mask, bits);
607 transient_bits |= GI_DISARM;
609 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
610 0, 0, transient_bits);
613 EXPORT_SYMBOL_GPL(ni_tio_arm);
615 static int ni_660x_clk_src(unsigned int clock_source, unsigned int *bits)
617 unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
618 unsigned int ni_660x_clock;
622 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
623 ni_660x_clock = NI_660X_TIMEBASE_1_CLK;
625 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
626 ni_660x_clock = NI_660X_TIMEBASE_2_CLK;
628 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
629 ni_660x_clock = NI_660X_TIMEBASE_3_CLK;
631 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
632 ni_660x_clock = NI_660X_LOGIC_LOW_CLK;
634 case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
635 ni_660x_clock = NI_660X_SRC_PIN_I_CLK;
637 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
638 ni_660x_clock = NI_660X_NEXT_GATE_CLK;
640 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
641 ni_660x_clock = NI_660X_NEXT_TC_CLK;
644 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
645 if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
646 ni_660x_clock = NI_660X_RTSI_CLK(i);
650 if (i <= NI_660X_MAX_RTSI_CHAN)
652 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
653 if (clk_src == NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
654 ni_660x_clock = NI_660X_SRC_PIN_CLK(i);
658 if (i <= NI_660X_MAX_SRC_PIN)
662 *bits = GI_SRC_SEL(ni_660x_clock);
666 static int ni_m_clk_src(unsigned int clock_source, unsigned int *bits)
668 unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
669 unsigned int ni_m_series_clock;
673 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
674 ni_m_series_clock = NI_M_TIMEBASE_1_CLK;
676 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
677 ni_m_series_clock = NI_M_TIMEBASE_2_CLK;
679 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
680 ni_m_series_clock = NI_M_TIMEBASE_3_CLK;
682 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
683 ni_m_series_clock = NI_M_LOGIC_LOW_CLK;
685 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
686 ni_m_series_clock = NI_M_NEXT_GATE_CLK;
688 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
689 ni_m_series_clock = NI_M_NEXT_TC_CLK;
691 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
692 ni_m_series_clock = NI_M_PXI10_CLK;
694 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
695 ni_m_series_clock = NI_M_PXI_STAR_TRIGGER_CLK;
697 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
698 ni_m_series_clock = NI_M_ANALOG_TRIGGER_OUT_CLK;
701 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
702 if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
703 ni_m_series_clock = NI_M_RTSI_CLK(i);
707 if (i <= NI_M_MAX_RTSI_CHAN)
709 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
710 if (clk_src == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
711 ni_m_series_clock = NI_M_PFI_CLK(i);
715 if (i <= NI_M_MAX_PFI_CHAN)
719 *bits = GI_SRC_SEL(ni_m_series_clock);
723 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
724 unsigned int clock_source)
726 struct ni_gpct_device *counter_dev = counter->counter_dev;
727 unsigned int cidx = counter->counter_index;
728 unsigned int chip = counter->chip_index;
729 unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
731 if (counter_dev->variant != ni_gpct_variant_m_series)
733 switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
734 /* Gi_Source_Subselect is zero */
735 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
736 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
737 counter_dev->regs[chip][second_gate_reg] &= ~GI_SRC_SUBSEL;
739 /* Gi_Source_Subselect is one */
740 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
741 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
742 counter_dev->regs[chip][second_gate_reg] |= GI_SRC_SUBSEL;
744 /* Gi_Source_Subselect doesn't matter */
748 ni_tio_write(counter, counter_dev->regs[chip][second_gate_reg],
752 static int ni_tio_set_clock_src(struct ni_gpct *counter,
753 unsigned int clock_source,
754 unsigned int period_ns)
756 struct ni_gpct_device *counter_dev = counter->counter_dev;
757 unsigned int cidx = counter->counter_index;
758 unsigned int bits = 0;
761 switch (counter_dev->variant) {
762 case ni_gpct_variant_660x:
763 ret = ni_660x_clk_src(clock_source, &bits);
765 case ni_gpct_variant_e_series:
766 case ni_gpct_variant_m_series:
768 ret = ni_m_clk_src(clock_source, &bits);
772 struct comedi_device *dev = counter_dev->dev;
774 dev_err(dev->class_dev, "invalid clock source 0x%x\n",
779 if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
780 bits |= GI_SRC_POL_INVERT;
781 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
782 GI_SRC_SEL_MASK | GI_SRC_POL_INVERT, bits);
783 ni_tio_set_source_subselect(counter, clock_source);
785 if (ni_tio_counting_mode_registers_present(counter_dev)) {
787 switch (clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
788 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
790 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
791 bits |= GI_PRESCALE_X2(counter_dev->variant);
793 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
794 bits |= GI_PRESCALE_X8(counter_dev->variant);
799 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
800 GI_PRESCALE_X2(counter_dev->variant) |
801 GI_PRESCALE_X8(counter_dev->variant), bits);
803 counter->clock_period_ps = period_ns * 1000;
804 ni_tio_set_sync_mode(counter);
808 static int ni_tio_get_clock_src(struct ni_gpct *counter,
809 unsigned int *clock_source,
810 unsigned int *period_ns)
815 ret = ni_tio_generic_clock_src_select(counter, clock_source);
818 ret = ni_tio_clock_period_ps(counter, *clock_source, &temp64);
821 do_div(temp64, 1000); /* ps to ns */
826 static inline void ni_tio_set_gate_raw(struct ni_gpct *counter,
827 unsigned int gate_source)
829 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(counter->counter_index),
830 GI_GATE_SEL_MASK, GI_GATE_SEL(gate_source));
833 static inline void ni_tio_set_gate2_raw(struct ni_gpct *counter,
834 unsigned int gate_source)
836 ni_tio_set_bits(counter, NITIO_GATE2_REG(counter->counter_index),
837 GI_GATE2_SEL_MASK, GI_GATE2_SEL(gate_source));
840 /* Set the mode bits for gate. */
841 static inline void ni_tio_set_gate_mode(struct ni_gpct *counter,
844 unsigned int mode_bits = 0;
846 if (CR_CHAN(src) & NI_GPCT_DISABLED_GATE_SELECT) {
848 * Allowing bitwise comparison here to allow non-zero raw
849 * register value to be used for channel when disabling.
851 mode_bits = GI_GATING_DISABLED;
854 mode_bits |= GI_GATE_POL_INVERT;
856 mode_bits |= GI_RISING_EDGE_GATING;
858 mode_bits |= GI_LEVEL_GATING;
860 ni_tio_set_bits(counter, NITIO_MODE_REG(counter->counter_index),
861 GI_GATE_POL_INVERT | GI_GATING_MODE_MASK,
866 * Set the mode bits for gate2.
868 * Previously, the code this function represents did not actually write anything
869 * to the register. Rather, writing to this register was reserved for the code
870 * ni ni_tio_set_gate2_raw.
872 static inline void ni_tio_set_gate2_mode(struct ni_gpct *counter,
876 * The GI_GATE2_MODE bit was previously set in the code that also sets
878 * We'll set mode bits _after_ source bits now, and thus, this function
879 * will effectively enable the second gate after all bits are set.
881 unsigned int mode_bits = GI_GATE2_MODE;
883 if (CR_CHAN(src) & NI_GPCT_DISABLED_GATE_SELECT)
885 * Allowing bitwise comparison here to allow non-zero raw
886 * register value to be used for channel when disabling.
888 mode_bits = GI_GATING_DISABLED;
890 mode_bits |= GI_GATE2_POL_INVERT;
892 ni_tio_set_bits(counter, NITIO_GATE2_REG(counter->counter_index),
893 GI_GATE2_POL_INVERT | GI_GATE2_MODE, mode_bits);
896 static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source)
898 unsigned int chan = CR_CHAN(gate_source);
899 unsigned int gate_sel;
903 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
904 gate_sel = NI_660X_NEXT_SRC_GATE_SEL;
906 case NI_GPCT_NEXT_OUT_GATE_SELECT:
907 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
908 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
909 case NI_GPCT_GATE_PIN_i_GATE_SELECT:
910 gate_sel = chan & 0x1f;
913 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
914 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
915 gate_sel = chan & 0x1f;
919 if (i <= NI_660X_MAX_RTSI_CHAN)
921 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
922 if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
923 gate_sel = chan & 0x1f;
927 if (i <= NI_660X_MAX_GATE_PIN)
931 ni_tio_set_gate_raw(counter, gate_sel);
935 static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source)
937 unsigned int chan = CR_CHAN(gate_source);
938 unsigned int gate_sel;
942 case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
943 case NI_GPCT_AI_START2_GATE_SELECT:
944 case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
945 case NI_GPCT_NEXT_OUT_GATE_SELECT:
946 case NI_GPCT_AI_START1_GATE_SELECT:
947 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
948 case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
949 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
950 gate_sel = chan & 0x1f;
953 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
954 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
955 gate_sel = chan & 0x1f;
959 if (i <= NI_M_MAX_RTSI_CHAN)
961 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
962 if (chan == NI_GPCT_PFI_GATE_SELECT(i)) {
963 gate_sel = chan & 0x1f;
967 if (i <= NI_M_MAX_PFI_CHAN)
971 ni_tio_set_gate_raw(counter, gate_sel);
975 static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
977 unsigned int chan = CR_CHAN(gate_source);
978 unsigned int gate2_sel;
982 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
983 case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
984 case NI_GPCT_SELECTED_GATE_GATE_SELECT:
985 case NI_GPCT_NEXT_OUT_GATE_SELECT:
986 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
987 gate2_sel = chan & 0x1f;
989 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
990 gate2_sel = NI_660X_NEXT_SRC_GATE2_SEL;
993 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
994 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
995 gate2_sel = chan & 0x1f;
999 if (i <= NI_660X_MAX_RTSI_CHAN)
1001 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1002 if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
1003 gate2_sel = chan & 0x1f;
1007 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1011 ni_tio_set_gate2_raw(counter, gate2_sel);
1015 static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
1018 * FIXME: We don't know what the m-series second gate codes are,
1019 * so we'll just pass the bits through for now.
1021 ni_tio_set_gate2_raw(counter, gate_source);
1025 int ni_tio_set_gate_src_raw(struct ni_gpct *counter,
1026 unsigned int gate, unsigned int src)
1028 struct ni_gpct_device *counter_dev = counter->counter_dev;
1032 /* 1. start by disabling gate */
1033 ni_tio_set_gate_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1034 /* 2. set the requested gate source */
1035 ni_tio_set_gate_raw(counter, src);
1036 /* 3. reenable & set mode to starts things back up */
1037 ni_tio_set_gate_mode(counter, src);
1040 if (!ni_tio_has_gate2_registers(counter_dev))
1043 /* 1. start by disabling gate */
1044 ni_tio_set_gate2_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1045 /* 2. set the requested gate source */
1046 ni_tio_set_gate2_raw(counter, src);
1047 /* 3. reenable & set mode to starts things back up */
1048 ni_tio_set_gate2_mode(counter, src);
1055 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src_raw);
1057 int ni_tio_set_gate_src(struct ni_gpct *counter,
1058 unsigned int gate, unsigned int src)
1060 struct ni_gpct_device *counter_dev = counter->counter_dev;
1062 * mask off disable flag. This high bit still passes CR_CHAN.
1063 * Doing this allows one to both set the gate as disabled, but also
1064 * change the route value of the gate.
1066 int chan = CR_CHAN(src) & (~NI_GPCT_DISABLED_GATE_SELECT);
1071 /* 1. start by disabling gate */
1072 ni_tio_set_gate_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1073 /* 2. set the requested gate source */
1074 switch (counter_dev->variant) {
1075 case ni_gpct_variant_e_series:
1076 case ni_gpct_variant_m_series:
1077 ret = ni_m_set_gate(counter, chan);
1079 case ni_gpct_variant_660x:
1080 ret = ni_660x_set_gate(counter, chan);
1087 /* 3. reenable & set mode to starts things back up */
1088 ni_tio_set_gate_mode(counter, src);
1091 if (!ni_tio_has_gate2_registers(counter_dev))
1094 /* 1. start by disabling gate */
1095 ni_tio_set_gate2_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1096 /* 2. set the requested gate source */
1097 switch (counter_dev->variant) {
1098 case ni_gpct_variant_m_series:
1099 ret = ni_m_set_gate2(counter, chan);
1101 case ni_gpct_variant_660x:
1102 ret = ni_660x_set_gate2(counter, chan);
1109 /* 3. reenable & set mode to starts things back up */
1110 ni_tio_set_gate2_mode(counter, src);
1117 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1119 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned int index,
1120 unsigned int source)
1122 struct ni_gpct_device *counter_dev = counter->counter_dev;
1123 unsigned int cidx = counter->counter_index;
1124 unsigned int chip = counter->chip_index;
1125 unsigned int abz_reg, shift, mask;
1127 if (counter_dev->variant != ni_gpct_variant_m_series)
1130 abz_reg = NITIO_ABZ_REG(cidx);
1132 /* allow for new device-global names */
1133 if (index == NI_GPCT_SOURCE_ENCODER_A ||
1134 (index >= NI_CtrA(0) && index <= NI_CtrA(-1))) {
1136 } else if (index == NI_GPCT_SOURCE_ENCODER_B ||
1137 (index >= NI_CtrB(0) && index <= NI_CtrB(-1))) {
1139 } else if (index == NI_GPCT_SOURCE_ENCODER_Z ||
1140 (index >= NI_CtrZ(0) && index <= NI_CtrZ(-1))) {
1146 mask = 0x1f << shift;
1148 source = 0x1f; /* Disable gate */
1150 counter_dev->regs[chip][abz_reg] &= ~mask;
1151 counter_dev->regs[chip][abz_reg] |= (source << shift) & mask;
1152 ni_tio_write(counter, counter_dev->regs[chip][abz_reg], abz_reg);
1156 static int ni_tio_get_other_src(struct ni_gpct *counter, unsigned int index,
1157 unsigned int *source)
1159 struct ni_gpct_device *counter_dev = counter->counter_dev;
1160 unsigned int cidx = counter->counter_index;
1161 unsigned int abz_reg, shift, mask;
1163 if (counter_dev->variant != ni_gpct_variant_m_series)
1164 /* A,B,Z only valid for m-series */
1167 abz_reg = NITIO_ABZ_REG(cidx);
1169 /* allow for new device-global names */
1170 if (index == NI_GPCT_SOURCE_ENCODER_A ||
1171 (index >= NI_CtrA(0) && index <= NI_CtrA(-1))) {
1173 } else if (index == NI_GPCT_SOURCE_ENCODER_B ||
1174 (index >= NI_CtrB(0) && index <= NI_CtrB(-1))) {
1176 } else if (index == NI_GPCT_SOURCE_ENCODER_Z ||
1177 (index >= NI_CtrZ(0) && index <= NI_CtrZ(-1))) {
1185 *source = (ni_tio_get_soft_copy(counter, abz_reg) >> shift) & mask;
1189 static int ni_660x_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1191 unsigned int source;
1195 case NI_660X_SRC_PIN_I_GATE_SEL:
1196 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1198 case NI_660X_GATE_PIN_I_GATE_SEL:
1199 source = NI_GPCT_GATE_PIN_i_GATE_SELECT;
1201 case NI_660X_NEXT_SRC_GATE_SEL:
1202 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1204 case NI_660X_NEXT_OUT_GATE_SEL:
1205 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1207 case NI_660X_LOGIC_LOW_GATE_SEL:
1208 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1211 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1212 if (gate == NI_660X_RTSI_GATE_SEL(i)) {
1213 source = NI_GPCT_RTSI_GATE_SELECT(i);
1217 if (i <= NI_660X_MAX_RTSI_CHAN)
1219 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
1220 if (gate == NI_660X_PIN_GATE_SEL(i)) {
1221 source = NI_GPCT_GATE_PIN_GATE_SELECT(i);
1225 if (i <= NI_660X_MAX_GATE_PIN)
1233 static int ni_m_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1235 unsigned int source;
1239 case NI_M_TIMESTAMP_MUX_GATE_SEL:
1240 source = NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1242 case NI_M_AI_START2_GATE_SEL:
1243 source = NI_GPCT_AI_START2_GATE_SELECT;
1245 case NI_M_PXI_STAR_TRIGGER_GATE_SEL:
1246 source = NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1248 case NI_M_NEXT_OUT_GATE_SEL:
1249 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1251 case NI_M_AI_START1_GATE_SEL:
1252 source = NI_GPCT_AI_START1_GATE_SELECT;
1254 case NI_M_NEXT_SRC_GATE_SEL:
1255 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1257 case NI_M_ANALOG_TRIG_OUT_GATE_SEL:
1258 source = NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1260 case NI_M_LOGIC_LOW_GATE_SEL:
1261 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1264 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
1265 if (gate == NI_M_RTSI_GATE_SEL(i)) {
1266 source = NI_GPCT_RTSI_GATE_SELECT(i);
1270 if (i <= NI_M_MAX_RTSI_CHAN)
1272 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
1273 if (gate == NI_M_PFI_GATE_SEL(i)) {
1274 source = NI_GPCT_PFI_GATE_SELECT(i);
1278 if (i <= NI_M_MAX_PFI_CHAN)
1286 static int ni_660x_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1288 unsigned int source;
1292 case NI_660X_SRC_PIN_I_GATE2_SEL:
1293 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1295 case NI_660X_UD_PIN_I_GATE2_SEL:
1296 source = NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1298 case NI_660X_NEXT_SRC_GATE2_SEL:
1299 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1301 case NI_660X_NEXT_OUT_GATE2_SEL:
1302 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1304 case NI_660X_SELECTED_GATE2_SEL:
1305 source = NI_GPCT_SELECTED_GATE_GATE_SELECT;
1307 case NI_660X_LOGIC_LOW_GATE2_SEL:
1308 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1311 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1312 if (gate == NI_660X_RTSI_GATE2_SEL(i)) {
1313 source = NI_GPCT_RTSI_GATE_SELECT(i);
1317 if (i <= NI_660X_MAX_RTSI_CHAN)
1319 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1320 if (gate == NI_660X_UD_PIN_GATE2_SEL(i)) {
1321 source = NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1325 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1333 static int ni_m_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1336 * FIXME: the second gate sources for the m series are undocumented,
1337 * so we just return the raw bits for now.
1343 static inline unsigned int ni_tio_get_gate_mode(struct ni_gpct *counter)
1345 unsigned int mode = ni_tio_get_soft_copy(counter,
1346 NITIO_MODE_REG(counter->counter_index));
1347 unsigned int ret = 0;
1349 if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED)
1350 ret |= NI_GPCT_DISABLED_GATE_SELECT;
1351 if (mode & GI_GATE_POL_INVERT)
1353 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1359 static inline unsigned int ni_tio_get_gate2_mode(struct ni_gpct *counter)
1361 unsigned int mode = ni_tio_get_soft_copy(counter,
1362 NITIO_GATE2_REG(counter->counter_index));
1363 unsigned int ret = 0;
1365 if (!(mode & GI_GATE2_MODE))
1366 ret |= NI_GPCT_DISABLED_GATE_SELECT;
1367 if (mode & GI_GATE2_POL_INVERT)
1373 static inline unsigned int ni_tio_get_gate_val(struct ni_gpct *counter)
1375 return GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter,
1376 NITIO_INPUT_SEL_REG(counter->counter_index)));
1379 static inline unsigned int ni_tio_get_gate2_val(struct ni_gpct *counter)
1381 return GI_BITS_TO_GATE2(ni_tio_get_soft_copy(counter,
1382 NITIO_GATE2_REG(counter->counter_index)));
1385 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned int gate_index,
1386 unsigned int *gate_source)
1391 switch (gate_index) {
1393 gate = ni_tio_get_gate_val(counter);
1394 switch (counter->counter_dev->variant) {
1395 case ni_gpct_variant_e_series:
1396 case ni_gpct_variant_m_series:
1398 ret = ni_m_gate_to_generic_gate(gate, gate_source);
1400 case ni_gpct_variant_660x:
1401 ret = ni_660x_gate_to_generic_gate(gate, gate_source);
1406 *gate_source |= ni_tio_get_gate_mode(counter);
1409 gate = ni_tio_get_gate2_val(counter);
1410 switch (counter->counter_dev->variant) {
1411 case ni_gpct_variant_e_series:
1412 case ni_gpct_variant_m_series:
1414 ret = ni_m_gate2_to_generic_gate(gate, gate_source);
1416 case ni_gpct_variant_660x:
1417 ret = ni_660x_gate2_to_generic_gate(gate, gate_source);
1422 *gate_source |= ni_tio_get_gate2_mode(counter);
1430 static int ni_tio_get_gate_src_raw(struct ni_gpct *counter,
1431 unsigned int gate_index,
1432 unsigned int *gate_source)
1434 switch (gate_index) {
1436 *gate_source = ni_tio_get_gate_mode(counter)
1437 | ni_tio_get_gate_val(counter);
1440 *gate_source = ni_tio_get_gate2_mode(counter)
1441 | ni_tio_get_gate2_val(counter);
1449 int ni_tio_insn_config(struct comedi_device *dev,
1450 struct comedi_subdevice *s,
1451 struct comedi_insn *insn,
1454 struct ni_gpct *counter = s->private;
1455 unsigned int cidx = counter->counter_index;
1456 unsigned int status;
1460 case INSN_CONFIG_SET_COUNTER_MODE:
1461 ret = ni_tio_set_counter_mode(counter, data[1]);
1463 case INSN_CONFIG_ARM:
1464 ret = ni_tio_arm(counter, true, data[1]);
1466 case INSN_CONFIG_DISARM:
1467 ret = ni_tio_arm(counter, false, 0);
1469 case INSN_CONFIG_GET_COUNTER_STATUS:
1471 status = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1472 if (status & GI_ARMED(cidx)) {
1473 data[1] |= COMEDI_COUNTER_ARMED;
1474 if (status & GI_COUNTING(cidx))
1475 data[1] |= COMEDI_COUNTER_COUNTING;
1477 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
1479 case INSN_CONFIG_SET_CLOCK_SRC:
1480 ret = ni_tio_set_clock_src(counter, data[1], data[2]);
1482 case INSN_CONFIG_GET_CLOCK_SRC:
1483 ret = ni_tio_get_clock_src(counter, &data[1], &data[2]);
1485 case INSN_CONFIG_SET_GATE_SRC:
1486 ret = ni_tio_set_gate_src(counter, data[1], data[2]);
1488 case INSN_CONFIG_GET_GATE_SRC:
1489 ret = ni_tio_get_gate_src(counter, data[1], &data[2]);
1491 case INSN_CONFIG_SET_OTHER_SRC:
1492 ret = ni_tio_set_other_src(counter, data[1], data[2]);
1494 case INSN_CONFIG_RESET:
1495 ni_tio_reset_count_and_disarm(counter);
1500 return ret ? ret : insn->n;
1502 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1505 * Retrieves the register value of the current source of the output selector for
1506 * the given destination.
1508 * If the terminal for the destination is not already configured as an output,
1509 * this function returns -EINVAL as error.
1511 * Return: the register value of the destination output selector;
1512 * -EINVAL if terminal is not configured for output.
1514 int ni_tio_get_routing(struct ni_gpct_device *counter_dev, unsigned int dest)
1516 /* we need to know the actual counter below... */
1517 int ctr_index = (dest - NI_COUNTER_NAMES_BASE) % NI_MAX_COUNTERS;
1518 struct ni_gpct *counter = &counter_dev->counters[ctr_index];
1522 if (dest >= NI_CtrA(0) && dest <= NI_CtrZ(-1)) {
1523 ret = ni_tio_get_other_src(counter, dest, ®);
1524 } else if (dest >= NI_CtrGate(0) && dest <= NI_CtrGate(-1)) {
1525 ret = ni_tio_get_gate_src_raw(counter, 0, ®);
1526 } else if (dest >= NI_CtrAux(0) && dest <= NI_CtrAux(-1)) {
1527 ret = ni_tio_get_gate_src_raw(counter, 1, ®);
1529 * This case is not possible through this interface. A user must use
1530 * INSN_CONFIG_SET_CLOCK_SRC instead.
1531 * } else if (dest >= NI_CtrSource(0) && dest <= NI_CtrSource(-1)) {
1532 * ret = ni_tio_set_clock_src(counter, ®, &period_ns);
1541 EXPORT_SYMBOL_GPL(ni_tio_get_routing);
1544 * ni_tio_set_routing() - Sets the register value of the selector MUX for the given destination.
1545 * @counter_dev: Pointer to general counter device.
1546 * @dest: Device-global identifier of route destination.
1548 * The first several bits of this value should store the desired
1549 * value to write to the register. All other bits are for
1550 * transmitting information that modify the mode of the particular
1551 * destination/gate. These mode bits might include a bitwise or of
1552 * CR_INVERT and CR_EDGE. Note that the calling function should
1553 * have already validated the correctness of this value.
1555 int ni_tio_set_routing(struct ni_gpct_device *counter_dev, unsigned int dest,
1558 /* we need to know the actual counter below... */
1559 int ctr_index = (dest - NI_COUNTER_NAMES_BASE) % NI_MAX_COUNTERS;
1560 struct ni_gpct *counter = &counter_dev->counters[ctr_index];
1563 if (dest >= NI_CtrA(0) && dest <= NI_CtrZ(-1)) {
1564 ret = ni_tio_set_other_src(counter, dest, reg);
1565 } else if (dest >= NI_CtrGate(0) && dest <= NI_CtrGate(-1)) {
1566 ret = ni_tio_set_gate_src_raw(counter, 0, reg);
1567 } else if (dest >= NI_CtrAux(0) && dest <= NI_CtrAux(-1)) {
1568 ret = ni_tio_set_gate_src_raw(counter, 1, reg);
1570 * This case is not possible through this interface. A user must use
1571 * INSN_CONFIG_SET_CLOCK_SRC instead.
1572 * } else if (dest >= NI_CtrSource(0) && dest <= NI_CtrSource(-1)) {
1573 * ret = ni_tio_set_clock_src(counter, reg, period_ns);
1581 EXPORT_SYMBOL_GPL(ni_tio_set_routing);
1584 * Sets the given destination MUX to its default value or disable it.
1586 * Return: 0 if successful; -EINVAL if terminal is unknown.
1588 int ni_tio_unset_routing(struct ni_gpct_device *counter_dev, unsigned int dest)
1590 if (dest >= NI_GATES_NAMES_BASE && dest <= NI_GATES_NAMES_MAX)
1591 /* Disable gate (via mode bits) and set to default 0-value */
1592 return ni_tio_set_routing(counter_dev, dest,
1593 NI_GPCT_DISABLED_GATE_SELECT);
1595 * This case is not possible through this interface. A user must use
1596 * INSN_CONFIG_SET_CLOCK_SRC instead.
1597 * if (dest >= NI_CtrSource(0) && dest <= NI_CtrSource(-1))
1598 * return ni_tio_set_clock_src(counter, reg, period_ns);
1603 EXPORT_SYMBOL_GPL(ni_tio_unset_routing);
1605 static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev,
1606 struct comedi_subdevice *s)
1608 struct ni_gpct *counter = s->private;
1609 unsigned int cidx = counter->counter_index;
1612 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
1613 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1614 GI_SAVE_TRACE, GI_SAVE_TRACE);
1617 * The count doesn't get latched until the next clock edge, so it is
1618 * possible the count may change (once) while we are reading. Since
1619 * the read of the SW_Save_Reg isn't atomic (apparently even when it's
1620 * a 32 bit register according to 660x docs), we need to read twice
1621 * and make sure the reading hasn't changed. If it has, a third read
1622 * will be correct since the count value will definitely have latched
1625 val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1626 if (val != ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx)))
1627 val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1632 int ni_tio_insn_read(struct comedi_device *dev,
1633 struct comedi_subdevice *s,
1634 struct comedi_insn *insn,
1637 struct ni_gpct *counter = s->private;
1638 struct ni_gpct_device *counter_dev = counter->counter_dev;
1639 unsigned int channel = CR_CHAN(insn->chanspec);
1640 unsigned int cidx = counter->counter_index;
1641 unsigned int chip = counter->chip_index;
1644 for (i = 0; i < insn->n; i++) {
1647 data[i] = ni_tio_read_sw_save_reg(dev, s);
1651 counter_dev->regs[chip][NITIO_LOADA_REG(cidx)];
1655 counter_dev->regs[chip][NITIO_LOADB_REG(cidx)];
1661 EXPORT_SYMBOL_GPL(ni_tio_insn_read);
1663 static unsigned int ni_tio_next_load_register(struct ni_gpct *counter)
1665 unsigned int cidx = counter->counter_index;
1666 unsigned int bits = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1668 return (bits & GI_NEXT_LOAD_SRC(cidx))
1669 ? NITIO_LOADB_REG(cidx)
1670 : NITIO_LOADA_REG(cidx);
1673 int ni_tio_insn_write(struct comedi_device *dev,
1674 struct comedi_subdevice *s,
1675 struct comedi_insn *insn,
1678 struct ni_gpct *counter = s->private;
1679 struct ni_gpct_device *counter_dev = counter->counter_dev;
1680 unsigned int channel = CR_CHAN(insn->chanspec);
1681 unsigned int cidx = counter->counter_index;
1682 unsigned int chip = counter->chip_index;
1683 unsigned int load_reg;
1684 unsigned int load_val;
1688 load_val = data[insn->n - 1];
1692 * Unsafe if counter is armed.
1693 * Should probably check status and return -EBUSY if armed.
1697 * Don't disturb load source select, just use whichever
1698 * load register is already selected.
1700 load_reg = ni_tio_next_load_register(counter);
1701 ni_tio_write(counter, load_val, load_reg);
1702 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
1704 /* restore load reg */
1705 ni_tio_write(counter, counter_dev->regs[chip][load_reg],
1709 counter_dev->regs[chip][NITIO_LOADA_REG(cidx)] = load_val;
1710 ni_tio_write(counter, load_val, NITIO_LOADA_REG(cidx));
1713 counter_dev->regs[chip][NITIO_LOADB_REG(cidx)] = load_val;
1714 ni_tio_write(counter, load_val, NITIO_LOADB_REG(cidx));
1721 EXPORT_SYMBOL_GPL(ni_tio_insn_write);
1723 void ni_tio_init_counter(struct ni_gpct *counter)
1725 struct ni_gpct_device *counter_dev = counter->counter_dev;
1726 unsigned int cidx = counter->counter_index;
1727 unsigned int chip = counter->chip_index;
1729 ni_tio_reset_count_and_disarm(counter);
1731 /* initialize counter registers */
1732 counter_dev->regs[chip][NITIO_AUTO_INC_REG(cidx)] = 0x0;
1733 ni_tio_write(counter, 0x0, NITIO_AUTO_INC_REG(cidx));
1735 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1738 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
1740 counter_dev->regs[chip][NITIO_LOADA_REG(cidx)] = 0x0;
1741 ni_tio_write(counter, 0x0, NITIO_LOADA_REG(cidx));
1743 counter_dev->regs[chip][NITIO_LOADB_REG(cidx)] = 0x0;
1744 ni_tio_write(counter, 0x0, NITIO_LOADB_REG(cidx));
1746 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
1748 if (ni_tio_counting_mode_registers_present(counter_dev))
1749 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
1751 if (ni_tio_has_gate2_registers(counter_dev)) {
1752 counter_dev->regs[chip][NITIO_GATE2_REG(cidx)] = 0x0;
1753 ni_tio_write(counter, 0x0, NITIO_GATE2_REG(cidx));
1756 ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
1758 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
1760 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1762 struct ni_gpct_device *
1763 ni_gpct_device_construct(struct comedi_device *dev,
1764 void (*write)(struct ni_gpct *counter,
1766 enum ni_gpct_register reg),
1767 unsigned int (*read)(struct ni_gpct *counter,
1768 enum ni_gpct_register reg),
1769 enum ni_gpct_variant variant,
1770 unsigned int num_counters,
1771 unsigned int counters_per_chip,
1772 const struct ni_route_tables *routing_tables)
1774 struct ni_gpct_device *counter_dev;
1775 struct ni_gpct *counter;
1778 if (num_counters == 0 || counters_per_chip == 0)
1781 counter_dev = kzalloc(sizeof(*counter_dev), GFP_KERNEL);
1785 counter_dev->dev = dev;
1786 counter_dev->write = write;
1787 counter_dev->read = read;
1788 counter_dev->variant = variant;
1789 counter_dev->routing_tables = routing_tables;
1791 spin_lock_init(&counter_dev->regs_lock);
1793 counter_dev->num_counters = num_counters;
1794 counter_dev->num_chips = DIV_ROUND_UP(num_counters, counters_per_chip);
1796 counter_dev->counters = kcalloc(num_counters, sizeof(*counter),
1798 counter_dev->regs = kcalloc(counter_dev->num_chips,
1799 sizeof(*counter_dev->regs), GFP_KERNEL);
1800 if (!counter_dev->regs || !counter_dev->counters) {
1801 kfree(counter_dev->regs);
1802 kfree(counter_dev->counters);
1807 for (i = 0; i < num_counters; ++i) {
1808 counter = &counter_dev->counters[i];
1809 counter->counter_dev = counter_dev;
1810 counter->chip_index = i / counters_per_chip;
1811 counter->counter_index = i % counters_per_chip;
1812 spin_lock_init(&counter->lock);
1817 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1819 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
1823 kfree(counter_dev->regs);
1824 kfree(counter_dev->counters);
1827 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
1829 static int __init ni_tio_init_module(void)
1833 module_init(ni_tio_init_module);
1835 static void __exit ni_tio_cleanup_module(void)
1838 module_exit(ni_tio_cleanup_module);
1840 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
1841 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
1842 MODULE_LICENSE("GPL");