1 // SPDX-License-Identifier: GPL-2.0+
3 * Comedi driver for NI PCI-MIO E series cards
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
11 * Description: National Instruments PCI-MIO-E series and M series (all boards)
12 * Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
13 * Herman Bruyninckx, Terry Barnaby
15 * Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
16 * PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014,
17 * PCI-6040E, PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E,
18 * PCI-6071E, PCI-6023E, PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E,
19 * PCI-6035E, PCI-6052E, PCI-6110, PCI-6111, PCI-6220, PXI-6220,
20 * PCI-6221, PXI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
21 * PCI-6229, PXI-6229, PCI-6250, PXI-6250, PCI-6251, PXI-6251,
22 * PCIe-6251, PXIe-6251, PCI-6254, PXI-6254, PCI-6259, PXI-6259,
23 * PCIe-6259, PXIe-6259, PCI-6280, PXI-6280, PCI-6281, PXI-6281,
24 * PCI-6284, PXI-6284, PCI-6289, PXI-6289, PCI-6711, PXI-6711,
25 * PCI-6713, PXI-6713, PXI-6071E, PCI-6070E, PXI-6070E,
26 * PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
28 * Updated: Mon, 16 Jan 2017 12:56:04 +0000
30 * These boards are almost identical to the AT-MIO E series, except that
31 * they use the PCI bus instead of ISA (i.e., AT). See the notes for the
32 * ni_atmio.o driver for additional information about these boards.
34 * Autocalibration is supported on many of the devices, using the
35 * comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
36 * M-Series boards do analog input and analog output calibration entirely
37 * in software. The software calibration corrects the analog input for
38 * offset, gain and nonlinearity. The analog outputs are corrected for
39 * offset and gain. See the comedilib documentation on
40 * comedi_get_softcal_converter() for more information.
42 * By default, the driver uses DMA to transfer analog input data to
43 * memory. When DMA is enabled, not all triggering features are
46 * Digital I/O may not work on 673x.
48 * Note that the PCI-6143 is a simultaineous sampling device with 8
49 * convertors. With this board all of the convertors perform one
50 * simultaineous sample during a scan interval. The period for a scan
51 * is used for the convert time in a Comedi cmd. The convert trigger
52 * source is normally set to TRIG_NOW by default.
54 * The RTSI trigger bus is supported on these cards on subdevice 10.
55 * See the comedilib documentation for details.
57 * Information (number of channels, bits, etc.) for some devices may be
58 * incorrect. Please check this and submit a bug if there are problems
61 * SCXI is probably broken for m-series boards.
64 * - When DMA is enabled, COMEDI_EV_CONVERT does not work correctly.
68 * The PCI-MIO E series driver was originally written by
69 * Tomasz Motylewski <...>, and ported to comedi by ds.
72 * 341079b.pdf PCI E Series Register-Level Programmer Manual
73 * 340934b.pdf DAQ-STC reference manual
75 * 322080b.pdf 6711/6713/6715 User Manual
77 * 320945c.pdf PCI E Series User Manual
78 * 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
81 * - need to deal with external reference for DAC, and other DAC
82 * properties in board properties
83 * - deal with at-mio-16de-10 revision D to N changes, etc.
84 * - need to add other CALDAC type
85 * - need to slow down DAC loading. I don't trust NI's claim that
86 * two writes to the PCI bus slows IO enough. I would prefer to
88 * Timing specs: (clock)
95 #include <linux/module.h>
96 #include <linux/delay.h>
97 #include <linux/comedi/comedi_pci.h>
98 #include <asm/byteorder.h>
106 * These are not all the possible ao ranges for 628x boards.
107 * They can do OFFSET +- REFERENCE where OFFSET can be
108 * 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
109 * be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
110 * 63 different possibilities. An AO channel
111 * can not act as it's own OFFSET or REFERENCE.
113 static const struct comedi_lrange range_ni_M_628x_ao = {
127 static const struct comedi_lrange range_ni_M_625x_ao = {
135 enum ni_pcimio_boardid {
136 BOARD_PCIMIO_16XE_50,
137 BOARD_PCIMIO_16XE_10,
206 static const struct ni_board_struct ni_boards[] = {
207 [BOARD_PCIMIO_16XE_50] = {
208 .name = "pci-mio-16xe-50",
210 .ai_maxdata = 0xffff,
211 .ai_fifo_depth = 2048,
213 .gainlkup = ai_gain_8,
216 .ao_maxdata = 0x0fff,
217 .ao_range_table = &range_bipolar10,
219 .caldac = { dac8800, dac8043 },
221 [BOARD_PCIMIO_16XE_10] = {
222 .name = "pci-mio-16xe-10", /* aka pci-6030E */
224 .ai_maxdata = 0xffff,
225 .ai_fifo_depth = 512,
227 .gainlkup = ai_gain_14,
230 .ao_maxdata = 0xffff,
231 .ao_fifo_depth = 2048,
232 .ao_range_table = &range_ni_E_ao_ext,
234 .caldac = { dac8800, dac8043, ad8522 },
239 .ai_maxdata = 0xffff,
240 .ai_fifo_depth = 512,
242 .gainlkup = ai_gain_4,
245 .ao_maxdata = 0xffff,
246 .ao_range_table = &range_bipolar10,
248 .caldac = { ad8804_debug },
253 .ai_maxdata = 0xffff,
254 .ai_fifo_depth = 512,
256 .gainlkup = ai_gain_14,
259 .ao_maxdata = 0xffff,
260 .ao_fifo_depth = 2048,
261 .ao_range_table = &range_ni_E_ao_ext,
263 .caldac = { dac8800, dac8043, ad8522 },
265 [BOARD_PCIMIO_16E_1] = {
266 .name = "pci-mio-16e-1", /* aka pci-6070e */
268 .ai_maxdata = 0x0fff,
269 .ai_fifo_depth = 512,
270 .gainlkup = ai_gain_16,
273 .ao_maxdata = 0x0fff,
274 .ao_fifo_depth = 2048,
275 .ao_range_table = &range_ni_E_ao_ext,
277 .caldac = { mb88341 },
279 [BOARD_PCIMIO_16E_4] = {
280 .name = "pci-mio-16e-4", /* aka pci-6040e */
282 .ai_maxdata = 0x0fff,
283 .ai_fifo_depth = 512,
284 .gainlkup = ai_gain_16,
286 * there have been reported problems with
287 * full speed on this board
291 .ao_maxdata = 0x0fff,
292 .ao_fifo_depth = 512,
293 .ao_range_table = &range_ni_E_ao_ext,
295 .caldac = { ad8804_debug }, /* doc says mb88341 */
300 .ai_maxdata = 0x0fff,
301 .ai_fifo_depth = 512,
302 .gainlkup = ai_gain_16,
305 .ao_maxdata = 0x0fff,
306 .ao_fifo_depth = 512,
307 .ao_range_table = &range_ni_E_ao_ext,
309 .caldac = { mb88341 },
314 .ai_maxdata = 0xffff,
315 .ai_fifo_depth = 512,
317 .gainlkup = ai_gain_14,
320 .ao_maxdata = 0xffff,
321 .ao_fifo_depth = 2048,
322 .ao_range_table = &range_ni_E_ao_ext,
324 .caldac = { dac8800, dac8043, ad8522 },
329 .ai_maxdata = 0xffff,
330 .ai_fifo_depth = 512,
332 .gainlkup = ai_gain_14,
334 .caldac = { dac8800, dac8043, ad8522 },
339 .ai_maxdata = 0xffff,
340 .ai_fifo_depth = 512,
342 .gainlkup = ai_gain_14,
344 .caldac = { dac8800, dac8043, ad8522 },
349 .ai_maxdata = 0x0fff,
350 .ai_fifo_depth = 512,
352 .gainlkup = ai_gain_16,
355 .ao_maxdata = 0x0fff,
356 .ao_fifo_depth = 2048,
357 .ao_range_table = &range_ni_E_ao_ext,
359 .caldac = { ad8804_debug },
364 .ai_maxdata = 0x0fff,
365 .ai_fifo_depth = 512,
366 .gainlkup = ai_gain_4,
368 .caldac = { ad8804_debug }, /* manual is wrong */
373 .ai_maxdata = 0x0fff,
374 .ai_fifo_depth = 512,
375 .gainlkup = ai_gain_4,
378 .ao_maxdata = 0x0fff,
379 .ao_range_table = &range_bipolar10,
381 .caldac = { ad8804_debug }, /* manual is wrong */
386 .ai_maxdata = 0x0fff,
387 .ai_fifo_depth = 512,
388 .gainlkup = ai_gain_4,
391 .ao_maxdata = 0x0fff,
392 .ao_range_table = &range_bipolar10,
394 .caldac = { ad8804_debug }, /* manual is wrong */
400 .ai_maxdata = 0x0fff,
401 .ai_fifo_depth = 512,
402 .gainlkup = ai_gain_4,
405 .ao_maxdata = 0x0fff,
406 .ao_range_table = &range_ni_E_ao_ext,
408 .caldac = { ad8804_debug }, /* manual is wrong */
414 .ai_maxdata = 0xffff,
415 .ai_fifo_depth = 512,
417 .gainlkup = ai_gain_4,
419 .caldac = { ad8804_debug },
424 .ai_maxdata = 0xffff,
425 .ai_fifo_depth = 512,
427 .gainlkup = ai_gain_4,
430 .ao_maxdata = 0x0fff,
431 .ao_range_table = &range_bipolar10,
433 .caldac = { ad8804_debug },
438 .ai_maxdata = 0xffff,
439 .ai_fifo_depth = 512,
441 .gainlkup = ai_gain_16,
444 .ao_maxdata = 0xffff,
445 .ao_fifo_depth = 2048,
446 .ao_range_table = &range_ni_E_ao_ext,
448 /* manual is wrong */
449 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
454 .ai_maxdata = 0x0fff,
455 .ai_fifo_depth = 8192,
457 .gainlkup = ai_gain_611x,
460 .ao_maxdata = 0xffff,
461 .reg_type = ni_reg_611x,
462 .ao_range_table = &range_bipolar10,
463 .ao_fifo_depth = 2048,
465 .caldac = { ad8804, ad8804 },
470 .ai_maxdata = 0x0fff,
471 .ai_fifo_depth = 8192,
472 .gainlkup = ai_gain_611x,
475 .ao_maxdata = 0xffff,
476 .reg_type = ni_reg_611x,
477 .ao_range_table = &range_bipolar10,
478 .ao_fifo_depth = 2048,
480 .caldac = { ad8804, ad8804 },
483 /* The 6115 boards probably need their own driver */
484 [BOARD_PCI6115] = { /* .device_id = 0x2ed0, */
487 .ai_maxdata = 0x0fff,
488 .ai_fifo_depth = 8192,
489 .gainlkup = ai_gain_611x,
492 .ao_maxdata = 0xffff,
494 .ao_fifo_depth = 2048,
498 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
502 [BOARD_PXI6115] = { /* .device_id = ????, */
505 .ai_maxdata = 0x0fff,
506 .ai_fifo_depth = 8192,
507 .gainlkup = ai_gain_611x,
510 .ao_maxdata = 0xffff,
512 .ao_fifo_depth = 2048,
516 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
522 .ao_maxdata = 0x0fff,
523 /* data sheet says 8192, but fifo really holds 16384 samples */
524 .ao_fifo_depth = 16384,
525 .ao_range_table = &range_bipolar10,
527 .reg_type = ni_reg_6711,
528 .caldac = { ad8804_debug },
533 .ao_maxdata = 0x0fff,
534 .ao_fifo_depth = 16384,
535 .ao_range_table = &range_bipolar10,
537 .reg_type = ni_reg_6711,
538 .caldac = { ad8804_debug },
543 .ao_maxdata = 0x0fff,
544 .ao_fifo_depth = 16384,
545 .ao_range_table = &range_bipolar10,
547 .reg_type = ni_reg_6713,
548 .caldac = { ad8804_debug, ad8804_debug },
553 .ao_maxdata = 0x0fff,
554 .ao_fifo_depth = 16384,
555 .ao_range_table = &range_bipolar10,
557 .reg_type = ni_reg_6713,
558 .caldac = { ad8804_debug, ad8804_debug },
563 .ao_maxdata = 0xffff,
564 .ao_fifo_depth = 8192,
565 .ao_range_table = &range_bipolar10,
567 .reg_type = ni_reg_6711,
568 .caldac = { ad8804_debug },
571 [BOARD_PXI6731] = { /* .device_id = ????, */
574 .ao_maxdata = 0xffff,
575 .ao_fifo_depth = 8192,
576 .ao_range_table = &range_bipolar10,
577 .reg_type = ni_reg_6711,
578 .caldac = { ad8804_debug },
584 .ao_maxdata = 0xffff,
585 .ao_fifo_depth = 16384,
586 .ao_range_table = &range_bipolar10,
588 .reg_type = ni_reg_6713,
589 .caldac = { ad8804_debug, ad8804_debug },
594 .ao_maxdata = 0xffff,
595 .ao_fifo_depth = 16384,
596 .ao_range_table = &range_bipolar10,
598 .reg_type = ni_reg_6713,
599 .caldac = { ad8804_debug, ad8804_debug },
604 .ai_maxdata = 0x0fff,
605 .ai_fifo_depth = 512,
607 .gainlkup = ai_gain_16,
610 .ao_maxdata = 0x0fff,
611 .ao_fifo_depth = 2048,
612 .ao_range_table = &range_ni_E_ao_ext,
614 .caldac = { ad8804_debug },
619 .ai_maxdata = 0x0fff,
620 .ai_fifo_depth = 512,
622 .gainlkup = ai_gain_16,
625 .ao_maxdata = 0x0fff,
626 .ao_fifo_depth = 2048,
627 .ao_range_table = &range_ni_E_ao_ext,
629 .caldac = { ad8804_debug },
634 .ai_maxdata = 0xffff,
635 .ai_fifo_depth = 512,
637 .gainlkup = ai_gain_16,
640 .ao_maxdata = 0xffff,
641 .ao_fifo_depth = 2048,
642 .ao_range_table = &range_ni_E_ao_ext,
644 .caldac = { mb88341, mb88341, ad8522 },
649 .ai_maxdata = 0xffff,
650 .ai_fifo_depth = 512,
652 .gainlkup = ai_gain_14,
655 .ao_maxdata = 0xffff,
656 .ao_fifo_depth = 2048,
657 .ao_range_table = &range_ni_E_ao_ext,
659 .caldac = { dac8800, dac8043, ad8522 },
664 .ai_maxdata = 0xffff,
665 .ai_fifo_depth = 512,
667 .gainlkup = ai_gain_4,
670 .ao_maxdata = 0xffff,
671 .ao_range_table = &range_bipolar10,
673 .caldac = { ad8804_debug },
678 .ai_maxdata = 0xffff,
679 .ai_fifo_depth = 512, /* FIXME: guess */
680 .gainlkup = ai_gain_622x,
682 .reg_type = ni_reg_622x,
683 .caldac = { caldac_none },
688 .ai_maxdata = 0xffff,
689 .ai_fifo_depth = 512, /* FIXME: guess */
690 .gainlkup = ai_gain_622x,
692 .reg_type = ni_reg_622x,
693 .caldac = { caldac_none },
699 .ai_maxdata = 0xffff,
700 .ai_fifo_depth = 4095,
701 .gainlkup = ai_gain_622x,
704 .ao_maxdata = 0xffff,
705 .ao_fifo_depth = 8191,
706 .ao_range_table = &range_bipolar10,
707 .reg_type = ni_reg_622x,
709 .caldac = { caldac_none },
712 [BOARD_PCI6221_37PIN] = {
713 .name = "pci-6221_37pin",
715 .ai_maxdata = 0xffff,
716 .ai_fifo_depth = 4095,
717 .gainlkup = ai_gain_622x,
720 .ao_maxdata = 0xffff,
721 .ao_fifo_depth = 8191,
722 .ao_range_table = &range_bipolar10,
723 .reg_type = ni_reg_622x,
725 .caldac = { caldac_none },
730 .ai_maxdata = 0xffff,
731 .ai_fifo_depth = 4095,
732 .gainlkup = ai_gain_622x,
735 .ao_maxdata = 0xffff,
736 .ao_fifo_depth = 8191,
737 .ao_range_table = &range_bipolar10,
738 .reg_type = ni_reg_622x,
740 .caldac = { caldac_none },
746 .ai_maxdata = 0xffff,
747 .ai_fifo_depth = 4095,
748 .gainlkup = ai_gain_622x,
750 .reg_type = ni_reg_622x,
752 .caldac = { caldac_none },
758 .ai_maxdata = 0xffff,
759 .ai_fifo_depth = 4095,
760 .gainlkup = ai_gain_622x,
762 .reg_type = ni_reg_622x,
764 .caldac = { caldac_none },
770 .ai_maxdata = 0xffff,
771 .ai_fifo_depth = 4095,
772 .gainlkup = ai_gain_622x,
775 .ao_maxdata = 0xffff,
776 .ao_fifo_depth = 8191,
777 .ao_range_table = &range_bipolar10,
778 .reg_type = ni_reg_622x,
781 .caldac = { caldac_none },
787 .ai_maxdata = 0xffff,
788 .ai_fifo_depth = 4095,
789 .gainlkup = ai_gain_622x,
792 .ao_maxdata = 0xffff,
793 .ao_fifo_depth = 8191,
794 .ao_range_table = &range_bipolar10,
795 .reg_type = ni_reg_622x,
798 .caldac = { caldac_none },
804 .ai_maxdata = 0xffff,
805 .ai_fifo_depth = 4095,
806 .gainlkup = ai_gain_622x,
809 .ao_maxdata = 0xffff,
810 .ao_fifo_depth = 8191,
811 .ao_range_table = &range_bipolar10,
812 .reg_type = ni_reg_622x,
815 .caldac = { caldac_none },
820 .ai_maxdata = 0xffff,
821 .ai_fifo_depth = 4095,
822 .gainlkup = ai_gain_622x,
825 .ao_maxdata = 0xffff,
826 .ao_fifo_depth = 8191,
827 .ao_range_table = &range_bipolar10,
828 .reg_type = ni_reg_622x,
831 .caldac = { caldac_none },
837 .ai_maxdata = 0xffff,
838 .ai_fifo_depth = 4095,
839 .gainlkup = ai_gain_628x,
841 .reg_type = ni_reg_625x,
842 .caldac = { caldac_none },
847 .ai_maxdata = 0xffff,
848 .ai_fifo_depth = 4095,
849 .gainlkup = ai_gain_628x,
851 .reg_type = ni_reg_625x,
852 .caldac = { caldac_none },
858 .ai_maxdata = 0xffff,
859 .ai_fifo_depth = 4095,
860 .gainlkup = ai_gain_628x,
863 .ao_maxdata = 0xffff,
864 .ao_fifo_depth = 8191,
865 .ao_range_table = &range_ni_M_625x_ao,
866 .reg_type = ni_reg_625x,
868 .caldac = { caldac_none },
874 .ai_maxdata = 0xffff,
875 .ai_fifo_depth = 4095,
876 .gainlkup = ai_gain_628x,
879 .ao_maxdata = 0xffff,
880 .ao_fifo_depth = 8191,
881 .ao_range_table = &range_ni_M_625x_ao,
882 .reg_type = ni_reg_625x,
884 .caldac = { caldac_none },
889 .alt_route_name = "pci-6251",
891 .ai_maxdata = 0xffff,
892 .ai_fifo_depth = 4095,
893 .gainlkup = ai_gain_628x,
896 .ao_maxdata = 0xffff,
897 .ao_fifo_depth = 8191,
898 .ao_range_table = &range_ni_M_625x_ao,
899 .reg_type = ni_reg_625x,
901 .caldac = { caldac_none },
907 .ai_maxdata = 0xffff,
908 .ai_fifo_depth = 4095,
909 .gainlkup = ai_gain_628x,
912 .ao_maxdata = 0xffff,
913 .ao_fifo_depth = 8191,
914 .ao_range_table = &range_ni_M_625x_ao,
915 .reg_type = ni_reg_625x,
917 .caldac = { caldac_none },
923 .ai_maxdata = 0xffff,
924 .ai_fifo_depth = 4095,
925 .gainlkup = ai_gain_628x,
927 .reg_type = ni_reg_625x,
929 .caldac = { caldac_none },
934 .ai_maxdata = 0xffff,
935 .ai_fifo_depth = 4095,
936 .gainlkup = ai_gain_628x,
938 .reg_type = ni_reg_625x,
940 .caldac = { caldac_none },
946 .ai_maxdata = 0xffff,
947 .ai_fifo_depth = 4095,
948 .gainlkup = ai_gain_628x,
951 .ao_maxdata = 0xffff,
952 .ao_fifo_depth = 8191,
953 .ao_range_table = &range_ni_M_625x_ao,
954 .reg_type = ni_reg_625x,
957 .caldac = { caldac_none },
962 .ai_maxdata = 0xffff,
963 .ai_fifo_depth = 4095,
964 .gainlkup = ai_gain_628x,
967 .ao_maxdata = 0xffff,
968 .ao_fifo_depth = 8191,
969 .ao_range_table = &range_ni_M_625x_ao,
970 .reg_type = ni_reg_625x,
973 .caldac = { caldac_none },
978 .alt_route_name = "pci-6259",
980 .ai_maxdata = 0xffff,
981 .ai_fifo_depth = 4095,
982 .gainlkup = ai_gain_628x,
985 .ao_maxdata = 0xffff,
986 .ao_fifo_depth = 8191,
987 .ao_range_table = &range_ni_M_625x_ao,
988 .reg_type = ni_reg_625x,
991 .caldac = { caldac_none },
996 .ai_maxdata = 0xffff,
997 .ai_fifo_depth = 4095,
998 .gainlkup = ai_gain_628x,
1001 .ao_maxdata = 0xffff,
1002 .ao_fifo_depth = 8191,
1003 .ao_range_table = &range_ni_M_625x_ao,
1004 .reg_type = ni_reg_625x,
1006 .has_32dio_chan = 1,
1007 .caldac = { caldac_none },
1013 .ai_maxdata = 0x3ffff,
1014 .ai_fifo_depth = 2047,
1015 .gainlkup = ai_gain_628x,
1017 .ao_fifo_depth = 8191,
1018 .reg_type = ni_reg_628x,
1019 .caldac = { caldac_none },
1024 .ai_maxdata = 0x3ffff,
1025 .ai_fifo_depth = 2047,
1026 .gainlkup = ai_gain_628x,
1028 .ao_fifo_depth = 8191,
1029 .reg_type = ni_reg_628x,
1030 .caldac = { caldac_none },
1036 .ai_maxdata = 0x3ffff,
1037 .ai_fifo_depth = 2047,
1038 .gainlkup = ai_gain_628x,
1041 .ao_maxdata = 0xffff,
1042 .ao_fifo_depth = 8191,
1043 .ao_range_table = &range_ni_M_628x_ao,
1044 .reg_type = ni_reg_628x,
1046 .caldac = { caldac_none },
1052 .ai_maxdata = 0x3ffff,
1053 .ai_fifo_depth = 2047,
1054 .gainlkup = ai_gain_628x,
1057 .ao_maxdata = 0xffff,
1058 .ao_fifo_depth = 8191,
1059 .ao_range_table = &range_ni_M_628x_ao,
1060 .reg_type = ni_reg_628x,
1062 .caldac = { caldac_none },
1068 .ai_maxdata = 0x3ffff,
1069 .ai_fifo_depth = 2047,
1070 .gainlkup = ai_gain_628x,
1072 .reg_type = ni_reg_628x,
1073 .has_32dio_chan = 1,
1074 .caldac = { caldac_none },
1079 .ai_maxdata = 0x3ffff,
1080 .ai_fifo_depth = 2047,
1081 .gainlkup = ai_gain_628x,
1083 .reg_type = ni_reg_628x,
1084 .has_32dio_chan = 1,
1085 .caldac = { caldac_none },
1091 .ai_maxdata = 0x3ffff,
1092 .ai_fifo_depth = 2047,
1093 .gainlkup = ai_gain_628x,
1096 .ao_maxdata = 0xffff,
1097 .ao_fifo_depth = 8191,
1098 .ao_range_table = &range_ni_M_628x_ao,
1099 .reg_type = ni_reg_628x,
1101 .has_32dio_chan = 1,
1102 .caldac = { caldac_none },
1107 .ai_maxdata = 0x3ffff,
1108 .ai_fifo_depth = 2047,
1109 .gainlkup = ai_gain_628x,
1112 .ao_maxdata = 0xffff,
1113 .ao_fifo_depth = 8191,
1114 .ao_range_table = &range_ni_M_628x_ao,
1115 .reg_type = ni_reg_628x,
1117 .has_32dio_chan = 1,
1118 .caldac = { caldac_none },
1124 .ai_maxdata = 0xffff,
1125 .ai_fifo_depth = 1024,
1126 .gainlkup = ai_gain_6143,
1128 .reg_type = ni_reg_6143,
1129 .caldac = { ad8804_debug, ad8804_debug },
1134 .ai_maxdata = 0xffff,
1135 .ai_fifo_depth = 1024,
1136 .gainlkup = ai_gain_6143,
1138 .reg_type = ni_reg_6143,
1139 .caldac = { ad8804_debug, ad8804_debug },
1143 #include "ni_mio_common.c"
1145 static int pcimio_ai_change(struct comedi_device *dev,
1146 struct comedi_subdevice *s)
1148 struct ni_private *devpriv = dev->private;
1151 ret = mite_buf_change(devpriv->ai_mite_ring, s);
1158 static int pcimio_ao_change(struct comedi_device *dev,
1159 struct comedi_subdevice *s)
1161 struct ni_private *devpriv = dev->private;
1164 ret = mite_buf_change(devpriv->ao_mite_ring, s);
1171 static int pcimio_gpct0_change(struct comedi_device *dev,
1172 struct comedi_subdevice *s)
1174 struct ni_private *devpriv = dev->private;
1177 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s);
1184 static int pcimio_gpct1_change(struct comedi_device *dev,
1185 struct comedi_subdevice *s)
1187 struct ni_private *devpriv = dev->private;
1190 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s);
1197 static int pcimio_dio_change(struct comedi_device *dev,
1198 struct comedi_subdevice *s)
1200 struct ni_private *devpriv = dev->private;
1203 ret = mite_buf_change(devpriv->cdo_mite_ring, s);
1210 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1212 struct ni_private *devpriv = dev->private;
1213 struct mite *mite = devpriv->mite;
1214 resource_size_t daq_phys_addr;
1215 static const int start_cal_eeprom = 0x400;
1216 static const unsigned int window_size = 10;
1217 unsigned int old_iodwbsr_bits;
1218 unsigned int old_iodwbsr1_bits;
1219 unsigned int old_iodwcr1_bits;
1222 /* IO Window 1 needs to be temporarily mapped to read the eeprom */
1223 daq_phys_addr = pci_resource_start(mite->pcidev, 1);
1225 old_iodwbsr_bits = readl(mite->mmio + MITE_IODWBSR);
1226 old_iodwbsr1_bits = readl(mite->mmio + MITE_IODWBSR_1);
1227 old_iodwcr1_bits = readl(mite->mmio + MITE_IODWCR_1);
1228 writel(0x0, mite->mmio + MITE_IODWBSR);
1229 writel(((0x80 | window_size) | daq_phys_addr),
1230 mite->mmio + MITE_IODWBSR_1);
1231 writel(0x1 | old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1232 writel(0xf, mite->mmio + 0x30);
1234 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1235 devpriv->eeprom_buffer[i] = ni_readb(dev, start_cal_eeprom + i);
1237 writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1);
1238 writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR);
1239 writel(old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1240 writel(0x0, mite->mmio + 0x30);
1243 static void init_6143(struct comedi_device *dev)
1245 const struct ni_board_struct *board = dev->board_ptr;
1246 struct ni_private *devpriv = dev->private;
1248 /* Disable interrupts */
1249 ni_stc_writew(dev, 0, NISTC_INT_CTRL_REG);
1251 /* Initialise 6143 AI specific bits */
1253 /* Set G0,G1 DMA mode to E series version */
1254 ni_writeb(dev, 0x00, NI6143_MAGIC_REG);
1255 /* Set EOCMode, ADCMode and pipelinedelay */
1256 ni_writeb(dev, 0x80, NI6143_PIPELINE_DELAY_REG);
1258 ni_writeb(dev, 0x00, NI6143_EOC_SET_REG);
1260 /* Set the FIFO half full level */
1261 ni_writel(dev, board->ai_fifo_depth / 2, NI6143_AI_FIFO_FLAG_REG);
1263 /* Strobe Relay disable bit */
1264 devpriv->ai_calib_source_enabled = 0;
1265 ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF,
1266 NI6143_CALIB_CHAN_REG);
1267 ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG);
1270 static void pcimio_detach(struct comedi_device *dev)
1272 struct ni_private *devpriv = dev->private;
1274 mio_common_detach(dev);
1276 free_irq(dev->irq, dev);
1278 mite_free_ring(devpriv->ai_mite_ring);
1279 mite_free_ring(devpriv->ao_mite_ring);
1280 mite_free_ring(devpriv->cdo_mite_ring);
1281 mite_free_ring(devpriv->gpct_mite_ring[0]);
1282 mite_free_ring(devpriv->gpct_mite_ring[1]);
1283 mite_detach(devpriv->mite);
1287 comedi_pci_disable(dev);
1290 static int pcimio_auto_attach(struct comedi_device *dev,
1291 unsigned long context)
1293 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1294 const struct ni_board_struct *board = NULL;
1295 struct ni_private *devpriv;
1299 if (context < ARRAY_SIZE(ni_boards))
1300 board = &ni_boards[context];
1303 dev->board_ptr = board;
1304 dev->board_name = board->name;
1306 ret = comedi_pci_enable(dev);
1310 ret = ni_alloc_private(dev);
1313 devpriv = dev->private;
1315 devpriv->mite = mite_attach(dev, false); /* use win0 */
1319 if (board->reg_type & ni_reg_m_series_mask)
1320 devpriv->is_m_series = 1;
1321 if (board->reg_type & ni_reg_6xxx_mask)
1322 devpriv->is_6xxx = 1;
1323 if (board->reg_type == ni_reg_611x)
1324 devpriv->is_611x = 1;
1325 if (board->reg_type == ni_reg_6143)
1326 devpriv->is_6143 = 1;
1327 if (board->reg_type == ni_reg_622x)
1328 devpriv->is_622x = 1;
1329 if (board->reg_type == ni_reg_625x)
1330 devpriv->is_625x = 1;
1331 if (board->reg_type == ni_reg_628x)
1332 devpriv->is_628x = 1;
1333 if (board->reg_type & ni_reg_67xx_mask)
1334 devpriv->is_67xx = 1;
1335 if (board->reg_type == ni_reg_6711)
1336 devpriv->is_6711 = 1;
1337 if (board->reg_type == ni_reg_6713)
1338 devpriv->is_6713 = 1;
1340 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1341 if (!devpriv->ai_mite_ring)
1343 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1344 if (!devpriv->ao_mite_ring)
1346 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1347 if (!devpriv->cdo_mite_ring)
1349 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1350 if (!devpriv->gpct_mite_ring[0])
1352 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1353 if (!devpriv->gpct_mite_ring[1])
1356 if (devpriv->is_m_series)
1357 m_series_init_eeprom_buffer(dev);
1358 if (devpriv->is_6143)
1363 ret = request_irq(irq, ni_E_interrupt, IRQF_SHARED,
1364 dev->board_name, dev);
1369 ret = ni_E_init(dev, 0, 1);
1373 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1374 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1375 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1376 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1377 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1382 static struct comedi_driver ni_pcimio_driver = {
1383 .driver_name = "ni_pcimio",
1384 .module = THIS_MODULE,
1385 .auto_attach = pcimio_auto_attach,
1386 .detach = pcimio_detach,
1389 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1390 const struct pci_device_id *id)
1392 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1395 static const struct pci_device_id ni_pcimio_pci_table[] = {
1396 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 }, /* 0x1620? */
1397 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1398 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1399 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1400 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1401 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1402 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1403 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1404 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1405 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1406 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1407 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1408 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1409 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1410 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1411 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1412 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1413 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1414 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1415 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1416 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1417 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1418 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1419 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1420 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1421 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1422 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1423 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1424 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1425 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1426 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1427 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1428 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1429 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1430 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1431 { PCI_VDEVICE(NI, 0x70ad), BOARD_PXI6251 },
1432 { PCI_VDEVICE(NI, 0x70ae), BOARD_PXI6220 },
1433 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1434 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1435 { PCI_VDEVICE(NI, 0x70b1), BOARD_PXI6229 },
1436 { PCI_VDEVICE(NI, 0x70b2), BOARD_PXI6259 },
1437 { PCI_VDEVICE(NI, 0x70b3), BOARD_PXI6289 },
1438 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1439 { PCI_VDEVICE(NI, 0x70b5), BOARD_PXI6221 },
1440 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1441 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1442 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1443 { PCI_VDEVICE(NI, 0x70b9), BOARD_PXI6250 },
1444 { PCI_VDEVICE(NI, 0x70ba), BOARD_PXI6254 },
1445 { PCI_VDEVICE(NI, 0x70bb), BOARD_PXI6280 },
1446 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1447 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1448 { PCI_VDEVICE(NI, 0x70be), BOARD_PXI6284 },
1449 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1450 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1451 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1452 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1453 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1454 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1455 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1456 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1457 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1458 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1459 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1460 { PCI_VDEVICE(NI, 0x72e9), BOARD_PXIE6259 },
1463 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1465 static struct pci_driver ni_pcimio_pci_driver = {
1466 .name = "ni_pcimio",
1467 .id_table = ni_pcimio_pci_table,
1468 .probe = ni_pcimio_pci_probe,
1469 .remove = comedi_pci_auto_unconfig,
1471 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1473 MODULE_AUTHOR("Comedi https://www.comedi.org");
1474 MODULE_DESCRIPTION("Comedi low-level driver");
1475 MODULE_LICENSE("GPL");