1 // SPDX-License-Identifier: GPL-2.0+
3 * Comedi driver for National Instruments PCI-DIO-32HS
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
11 * Description: National Instruments PCI-DIO32HS, PCI-6533
14 * Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
15 * [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
16 * [National Instruments] PCI-6534 (pci-6534)
17 * Updated: Mon, 09 Jan 2012 14:27:23 +0000
19 * The DIO32HS board appears as one subdevice, with 32 channels. Each
20 * channel is individually I/O configurable. The channel order is 0=A0,
21 * 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only supports simple
22 * digital I/O; no handshaking is supported.
24 * DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
26 * The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
27 * scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
28 * scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
31 * This driver could be easily modified to support AT-MIO32HS and AT-MIO96.
33 * The PCI-6534 requires a firmware upload after power-up to work, the
34 * firmware data and instructions for loading it with comedi_config
35 * it are contained in the comedi_nonfree_firmware tarball available from
36 * https://www.comedi.org
41 #include <linux/module.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/sched.h>
45 #include <linux/comedi/comedi_pci.h>
49 /* defines for the PCI-DIO-32HS */
51 #define WINDOW_ADDRESS 4 /* W */
52 #define INTERRUPT_AND_WINDOW_STATUS 4 /* R */
53 #define INT_STATUS_1 BIT(0)
54 #define INT_STATUS_2 BIT(1)
55 #define WINDOW_ADDRESS_STATUS_MASK 0x7c
57 #define MASTER_DMA_AND_INTERRUPT_CONTROL 5 /* W */
58 #define INTERRUPT_LINE(x) ((x) & 3)
59 #define OPEN_INT BIT(2)
60 #define GROUP_STATUS 5 /* R */
61 #define DATA_LEFT BIT(0)
63 #define STOP_TRIG BIT(3)
65 #define GROUP_1_FLAGS 6 /* R */
66 #define GROUP_2_FLAGS 7 /* R */
67 #define TRANSFER_READY BIT(0)
68 #define COUNT_EXPIRED BIT(1)
70 #define PRIMARY_TC BIT(6)
71 #define SECONDARY_TC BIT(7)
72 /* #define SerialRose */
76 #define GROUP_1_FIRST_CLEAR 6 /* W */
77 #define GROUP_2_FIRST_CLEAR 7 /* W */
78 #define CLEAR_WAITED BIT(3)
79 #define CLEAR_PRIMARY_TC BIT(4)
80 #define CLEAR_SECONDARY_TC BIT(5)
81 #define DMA_RESET BIT(6)
82 #define FIFO_RESET BIT(7)
83 #define CLEAR_ALL 0xf8
85 #define GROUP_1_FIFO 8 /* W */
86 #define GROUP_2_FIFO 12 /* W */
88 #define TRANSFER_COUNT 20
92 #define CHIP_VERSION 27
93 #define PORT_IO(x) (28 + (x))
94 #define PORT_PIN_DIRECTIONS(x) (32 + (x))
95 #define PORT_PIN_MASK(x) (36 + (x))
96 #define PORT_PIN_POLARITIES(x) (40 + (x))
98 #define MASTER_CLOCK_ROUTING 45
99 #define RTSI_CLOCKING(x) (((x) & 3) << 4)
101 #define GROUP_1_SECOND_CLEAR 46 /* W */
102 #define GROUP_2_SECOND_CLEAR 47 /* W */
103 #define CLEAR_EXPIRED BIT(0)
105 #define PORT_PATTERN(x) (48 + (x))
108 #define FIFO_ENABLE_A BIT(0)
109 #define FIFO_ENABLE_B BIT(1)
110 #define FIFO_ENABLE_C BIT(2)
111 #define FIFO_ENABLE_D BIT(3)
112 #define FUNNELING(x) (((x) & 3) << 4)
113 #define GROUP_DIRECTION BIT(7)
115 #define PROTOCOL_REGISTER_1 65
116 #define OP_MODE PROTOCOL_REGISTER_1
117 #define RUN_MODE(x) ((x) & 7)
118 #define NUMBERED BIT(3)
120 #define PROTOCOL_REGISTER_2 66
121 #define CLOCK_REG PROTOCOL_REGISTER_2
122 #define CLOCK_LINE(x) (((x) & 3) << 5)
123 #define INVERT_STOP_TRIG BIT(7)
124 #define DATA_LATCHING(x) (((x) & 3) << 5)
126 #define PROTOCOL_REGISTER_3 67
127 #define SEQUENCE PROTOCOL_REGISTER_3
129 #define PROTOCOL_REGISTER_14 68 /* 16 bit */
130 #define CLOCK_SPEED PROTOCOL_REGISTER_14
132 #define PROTOCOL_REGISTER_4 70
133 #define REQ_REG PROTOCOL_REGISTER_4
134 #define REQ_CONDITIONING(x) (((x) & 7) << 3)
136 #define PROTOCOL_REGISTER_5 71
137 #define BLOCK_MODE PROTOCOL_REGISTER_5
139 #define FIFO_Control 72
140 #define READY_LEVEL(x) ((x) & 7)
142 #define PROTOCOL_REGISTER_6 73
143 #define LINE_POLARITIES PROTOCOL_REGISTER_6
144 #define INVERT_ACK BIT(0)
145 #define INVERT_REQ BIT(1)
146 #define INVERT_CLOCK BIT(2)
147 #define INVERT_SERIAL BIT(3)
148 #define OPEN_ACK BIT(4)
149 #define OPEN_CLOCK BIT(5)
151 #define PROTOCOL_REGISTER_7 74
152 #define ACK_SER PROTOCOL_REGISTER_7
153 #define ACK_LINE(x) (((x) & 3) << 2)
154 #define EXCHANGE_PINS BIT(7)
156 #define INTERRUPT_CONTROL 75
157 /* bits same as flags */
159 #define DMA_LINE_CONTROL_GROUP1 76
160 #define DMA_LINE_CONTROL_GROUP2 108
162 /* channel zero is none */
163 static inline unsigned int primary_DMAChannel_bits(unsigned int channel)
165 return channel & 0x3;
168 static inline unsigned int secondary_DMAChannel_bits(unsigned int channel)
170 return (channel << 2) & 0xc;
173 #define TRANSFER_SIZE_CONTROL 77
174 #define TRANSFER_WIDTH(x) ((x) & 3)
175 #define TRANSFER_LENGTH(x) (((x) & 3) << 3)
176 #define REQUIRE_R_LEVEL BIT(5)
178 #define PROTOCOL_REGISTER_15 79
179 #define DAQ_OPTIONS PROTOCOL_REGISTER_15
180 #define START_SOURCE(x) ((x) & 0x3)
181 #define INVERT_START BIT(2)
182 #define STOP_SOURCE(x) (((x) & 0x3) << 3)
183 #define REQ_START BIT(6)
184 #define PRE_START BIT(7)
186 #define PATTERN_DETECTION 81
187 #define DETECTION_METHOD BIT(0)
188 #define INVERT_MATCH BIT(1)
189 #define IE_PATTERN_DETECTION BIT(2)
191 #define PROTOCOL_REGISTER_9 82
192 #define REQ_DELAY PROTOCOL_REGISTER_9
194 #define PROTOCOL_REGISTER_10 83
195 #define REQ_NOT_DELAY PROTOCOL_REGISTER_10
197 #define PROTOCOL_REGISTER_11 84
198 #define ACK_DELAY PROTOCOL_REGISTER_11
200 #define PROTOCOL_REGISTER_12 85
201 #define ACK_NOT_DELAY PROTOCOL_REGISTER_12
203 #define PROTOCOL_REGISTER_13 86
204 #define DATA_1_DELAY PROTOCOL_REGISTER_13
206 #define PROTOCOL_REGISTER_8 88 /* 32 bit */
207 #define START_DELAY PROTOCOL_REGISTER_8
209 /* Firmware files for PCI-6524 */
210 #define FW_PCI_6534_MAIN "/*(DEBLOBBED)*/"
211 #define FW_PCI_6534_SCARAB_DI "/*(DEBLOBBED)*/"
212 #define FW_PCI_6534_SCARAB_DO "/*(DEBLOBBED)*/"
215 enum pci_6534_firmware_registers { /* 16 bit */
216 Firmware_Control_Register = 0x100,
217 Firmware_Status_Register = 0x104,
218 Firmware_Data_Register = 0x108,
219 Firmware_Mask_Register = 0x10c,
220 Firmware_Debug_Register = 0x110,
223 /* main fpga registers (32 bit)*/
224 enum pci_6534_fpga_registers {
225 FPGA_Control1_Register = 0x200,
226 FPGA_Control2_Register = 0x204,
227 FPGA_Irq_Mask_Register = 0x208,
228 FPGA_Status_Register = 0x20c,
229 FPGA_Signature_Register = 0x210,
230 FPGA_SCALS_Counter_Register = 0x280, /*write-clear */
231 FPGA_SCAMS_Counter_Register = 0x284, /*write-clear */
232 FPGA_SCBLS_Counter_Register = 0x288, /*write-clear */
233 FPGA_SCBMS_Counter_Register = 0x28c, /*write-clear */
234 FPGA_Temp_Control_Register = 0x2a0,
235 FPGA_DAR_Register = 0x2a8,
236 FPGA_ELC_Read_Register = 0x2b8,
237 FPGA_ELC_Write_Register = 0x2bc,
240 enum FPGA_Control_Bits {
241 FPGA_Enable_Bit = 0x8000,
244 #define TIMER_BASE 50 /* nanoseconds */
247 #define INT_EN (COUNT_EXPIRED | WAITED | PRIMARY_TC | SECONDARY_TC)
249 #define INT_EN (TRANSFER_READY | COUNT_EXPIRED | WAITED \
250 | PRIMARY_TC | SECONDARY_TC)
261 unsigned int uses_firmware:1;
262 unsigned int dio_speed;
265 static const struct nidio_board nidio_boards[] = {
266 [BOARD_PCIDIO_32HS] = {
267 .name = "pci-dio-32hs",
281 struct nidio96_private {
285 unsigned short OP_MODEBits;
286 struct mite_channel *di_mite_chan;
287 struct mite_ring *di_mite_ring;
288 spinlock_t mite_channel_lock;
291 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
293 struct nidio96_private *devpriv = dev->private;
296 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
297 BUG_ON(devpriv->di_mite_chan);
298 devpriv->di_mite_chan =
299 mite_request_channel_in_range(devpriv->mite,
300 devpriv->di_mite_ring, 1, 2);
301 if (!devpriv->di_mite_chan) {
302 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
303 dev_err(dev->class_dev, "failed to reserve mite dma channel\n");
306 devpriv->di_mite_chan->dir = COMEDI_INPUT;
307 writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
308 secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
309 dev->mmio + DMA_LINE_CONTROL_GROUP1);
310 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
314 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
316 struct nidio96_private *devpriv = dev->private;
319 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
320 if (devpriv->di_mite_chan) {
321 mite_release_channel(devpriv->di_mite_chan);
322 devpriv->di_mite_chan = NULL;
323 writeb(primary_DMAChannel_bits(0) |
324 secondary_DMAChannel_bits(0),
325 dev->mmio + DMA_LINE_CONTROL_GROUP1);
327 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
330 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
332 struct nidio96_private *devpriv = dev->private;
336 retval = ni_pcidio_request_di_mite_channel(dev);
340 /* write alloc the entire buffer */
341 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
343 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
344 if (devpriv->di_mite_chan) {
345 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
346 mite_dma_arm(devpriv->di_mite_chan);
350 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
355 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
357 struct nidio96_private *devpriv = dev->private;
358 unsigned long irq_flags;
361 spin_lock_irqsave(&dev->spinlock, irq_flags);
362 spin_lock(&devpriv->mite_channel_lock);
363 if (devpriv->di_mite_chan)
364 mite_sync_dma(devpriv->di_mite_chan, s);
365 spin_unlock(&devpriv->mite_channel_lock);
366 count = comedi_buf_n_bytes_ready(s);
367 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
371 static irqreturn_t nidio_interrupt(int irq, void *d)
373 struct comedi_device *dev = d;
374 struct nidio96_private *devpriv = dev->private;
375 struct comedi_subdevice *s = dev->read_subdev;
376 struct comedi_async *async = s->async;
377 unsigned int auxdata;
382 /* interrupcions parasites */
383 if (!dev->attached) {
384 /* assume it's from another card */
388 /* Lock to avoid race with comedi_poll */
389 spin_lock(&dev->spinlock);
391 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
392 flags = readb(dev->mmio + GROUP_1_FLAGS);
394 spin_lock(&devpriv->mite_channel_lock);
395 if (devpriv->di_mite_chan) {
396 mite_ack_linkc(devpriv->di_mite_chan, s, false);
397 /* XXX need to byteswap sync'ed dma */
399 spin_unlock(&devpriv->mite_channel_lock);
401 while (status & DATA_LEFT) {
404 dev_dbg(dev->class_dev, "too much work in interrupt\n");
406 dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
412 if (flags & TRANSFER_READY) {
413 while (flags & TRANSFER_READY) {
416 dev_dbg(dev->class_dev,
417 "too much work in interrupt\n");
418 writeb(0x00, dev->mmio +
419 MASTER_DMA_AND_INTERRUPT_CONTROL
423 auxdata = readl(dev->mmio + GROUP_1_FIFO);
424 comedi_buf_write_samples(s, &auxdata, 1);
425 flags = readb(dev->mmio + GROUP_1_FLAGS);
429 if (flags & COUNT_EXPIRED) {
430 writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR);
431 async->events |= COMEDI_CB_EOA;
433 writeb(0x00, dev->mmio + OP_MODE);
435 } else if (flags & WAITED) {
436 writeb(CLEAR_WAITED, dev->mmio + GROUP_1_FIRST_CLEAR);
437 async->events |= COMEDI_CB_ERROR;
439 } else if (flags & PRIMARY_TC) {
440 writeb(CLEAR_PRIMARY_TC,
441 dev->mmio + GROUP_1_FIRST_CLEAR);
442 async->events |= COMEDI_CB_EOA;
443 } else if (flags & SECONDARY_TC) {
444 writeb(CLEAR_SECONDARY_TC,
445 dev->mmio + GROUP_1_FIRST_CLEAR);
446 async->events |= COMEDI_CB_EOA;
449 flags = readb(dev->mmio + GROUP_1_FLAGS);
450 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
454 comedi_handle_events(dev, s);
457 writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
460 spin_unlock(&dev->spinlock);
464 static int ni_pcidio_insn_config(struct comedi_device *dev,
465 struct comedi_subdevice *s,
466 struct comedi_insn *insn,
471 if (data[0] == INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS) {
472 const struct nidio_board *board = dev->board_ptr;
474 /* we don't care about actual channels */
475 data[1] = board->dio_speed;
480 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
484 writel(s->io_bits, dev->mmio + PORT_PIN_DIRECTIONS(0));
489 static int ni_pcidio_insn_bits(struct comedi_device *dev,
490 struct comedi_subdevice *s,
491 struct comedi_insn *insn,
494 if (comedi_dio_update_state(s, data))
495 writel(s->state, dev->mmio + PORT_IO(0));
497 data[1] = readl(dev->mmio + PORT_IO(0));
502 static int ni_pcidio_ns_to_timer(int *nanosec, unsigned int flags)
508 switch (flags & CMDF_ROUND_MASK) {
509 case CMDF_ROUND_NEAREST:
511 divider = DIV_ROUND_CLOSEST(*nanosec, base);
513 case CMDF_ROUND_DOWN:
514 divider = (*nanosec) / base;
517 divider = DIV_ROUND_UP(*nanosec, base);
521 *nanosec = base * divider;
525 static int ni_pcidio_cmdtest(struct comedi_device *dev,
526 struct comedi_subdevice *s, struct comedi_cmd *cmd)
531 /* Step 1 : check if triggers are trivially valid */
533 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
534 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
535 TRIG_TIMER | TRIG_EXT);
536 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
537 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
538 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
543 /* Step 2a : make sure trigger sources are unique */
545 err |= comedi_check_trigger_is_unique(cmd->start_src);
546 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
547 err |= comedi_check_trigger_is_unique(cmd->stop_src);
549 /* Step 2b : and mutually compatible */
554 /* Step 3: check if arguments are trivially valid */
556 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
558 #define MAX_SPEED (TIMER_BASE) /* in nanoseconds */
560 if (cmd->scan_begin_src == TRIG_TIMER) {
561 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
563 /* no minimum speed */
566 /* should be level/edge, hi/lo specification here */
567 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
568 cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
573 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
574 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
577 if (cmd->stop_src == TRIG_COUNT)
578 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
580 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
585 /* step 4: fix up any arguments */
587 if (cmd->scan_begin_src == TRIG_TIMER) {
588 arg = cmd->scan_begin_arg;
589 ni_pcidio_ns_to_timer(&arg, cmd->flags);
590 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
599 static int ni_pcidio_inttrig(struct comedi_device *dev,
600 struct comedi_subdevice *s,
601 unsigned int trig_num)
603 struct nidio96_private *devpriv = dev->private;
604 struct comedi_cmd *cmd = &s->async->cmd;
606 if (trig_num != cmd->start_arg)
609 writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
610 s->async->inttrig = NULL;
615 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
617 struct nidio96_private *devpriv = dev->private;
618 struct comedi_cmd *cmd = &s->async->cmd;
620 /* XXX configure ports for input */
621 writel(0x0000, dev->mmio + PORT_PIN_DIRECTIONS(0));
624 /* enable fifos A B C D */
625 writeb(0x0f, dev->mmio + DATA_PATH);
627 /* set transfer width a 32 bits */
628 writeb(TRANSFER_WIDTH(0) | TRANSFER_LENGTH(0),
629 dev->mmio + TRANSFER_SIZE_CONTROL);
631 writeb(0x03, dev->mmio + DATA_PATH);
632 writeb(TRANSFER_WIDTH(3) | TRANSFER_LENGTH(0),
633 dev->mmio + TRANSFER_SIZE_CONTROL);
636 /* protocol configuration */
637 if (cmd->scan_begin_src == TRIG_TIMER) {
638 /* page 4-5, "input with internal REQs" */
639 writeb(0, dev->mmio + OP_MODE);
640 writeb(0x00, dev->mmio + CLOCK_REG);
641 writeb(1, dev->mmio + SEQUENCE);
642 writeb(0x04, dev->mmio + REQ_REG);
643 writeb(4, dev->mmio + BLOCK_MODE);
644 writeb(3, dev->mmio + LINE_POLARITIES);
645 writeb(0xc0, dev->mmio + ACK_SER);
646 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
648 dev->mmio + START_DELAY);
649 writeb(1, dev->mmio + REQ_DELAY);
650 writeb(1, dev->mmio + REQ_NOT_DELAY);
651 writeb(1, dev->mmio + ACK_DELAY);
652 writeb(0x0b, dev->mmio + ACK_NOT_DELAY);
653 writeb(0x01, dev->mmio + DATA_1_DELAY);
656 * CLOCK_SPEED comment is incorrectly listed on DAQ_OPTIONS
658 writew(0, dev->mmio + CLOCK_SPEED);
659 writeb(0, dev->mmio + DAQ_OPTIONS);
662 /* page 4-5, "input with external REQs" */
663 writeb(0, dev->mmio + OP_MODE);
664 writeb(0x00, dev->mmio + CLOCK_REG);
665 writeb(0, dev->mmio + SEQUENCE);
666 writeb(0x00, dev->mmio + REQ_REG);
667 writeb(4, dev->mmio + BLOCK_MODE);
668 if (!(cmd->scan_begin_arg & CR_INVERT)) /* Leading Edge */
669 writeb(0, dev->mmio + LINE_POLARITIES);
670 else /* Trailing Edge */
671 writeb(2, dev->mmio + LINE_POLARITIES);
672 writeb(0x00, dev->mmio + ACK_SER);
673 writel(1, dev->mmio + START_DELAY);
674 writeb(1, dev->mmio + REQ_DELAY);
675 writeb(1, dev->mmio + REQ_NOT_DELAY);
676 writeb(1, dev->mmio + ACK_DELAY);
677 writeb(0x0C, dev->mmio + ACK_NOT_DELAY);
678 writeb(0x10, dev->mmio + DATA_1_DELAY);
679 writew(0, dev->mmio + CLOCK_SPEED);
680 writeb(0x60, dev->mmio + DAQ_OPTIONS);
683 if (cmd->stop_src == TRIG_COUNT) {
684 writel(cmd->stop_arg,
685 dev->mmio + TRANSFER_COUNT);
691 writeb(CLEAR_PRIMARY_TC | CLEAR_SECONDARY_TC,
692 dev->mmio + GROUP_1_FIRST_CLEAR);
695 int retval = setup_mite_dma(dev, s);
701 writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP1);
703 writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP2);
705 /* clear and enable interrupts */
706 writeb(0xff, dev->mmio + GROUP_1_FIRST_CLEAR);
707 /* writeb(CLEAR_EXPIRED, dev->mmio+GROUP_1_SECOND_CLEAR); */
709 writeb(INT_EN, dev->mmio + INTERRUPT_CONTROL);
710 writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
712 if (cmd->stop_src == TRIG_NONE) {
713 devpriv->OP_MODEBits = DATA_LATCHING(0) | RUN_MODE(7);
714 } else { /* TRIG_TIMER */
715 devpriv->OP_MODEBits = NUMBERED | RUN_MODE(7);
717 if (cmd->start_src == TRIG_NOW) {
719 writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
720 s->async->inttrig = NULL;
723 s->async->inttrig = ni_pcidio_inttrig;
729 static int ni_pcidio_cancel(struct comedi_device *dev,
730 struct comedi_subdevice *s)
732 writeb(0x00, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
733 ni_pcidio_release_di_mite_channel(dev);
738 static int ni_pcidio_change(struct comedi_device *dev,
739 struct comedi_subdevice *s)
741 struct nidio96_private *devpriv = dev->private;
744 ret = mite_buf_change(devpriv->di_mite_ring, s);
748 memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
753 static int pci_6534_load_fpga(struct comedi_device *dev,
754 const u8 *data, size_t data_len,
755 unsigned long context)
757 static const int timeout = 1000;
758 int fpga_index = context;
762 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
763 writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register);
765 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 &&
770 dev_warn(dev->class_dev,
771 "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
775 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
777 readw(dev->mmio + Firmware_Status_Register) != 0x3 &&
782 dev_warn(dev->class_dev,
783 "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
787 for (j = 0; j + 1 < data_len;) {
788 unsigned int value = data[j++];
790 value |= data[j++] << 8;
791 writew(value, dev->mmio + Firmware_Data_Register);
793 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0
794 && i < timeout; ++i) {
798 dev_warn(dev->class_dev,
799 "ni_pcidio: failed to load word into fpga %i\n",
806 writew(0x0, dev->mmio + Firmware_Control_Register);
810 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
812 return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
815 static int pci_6534_reset_fpgas(struct comedi_device *dev)
820 writew(0x0, dev->mmio + Firmware_Control_Register);
821 for (i = 0; i < 3; ++i) {
822 ret = pci_6534_reset_fpga(dev, i);
826 writew(0x0, dev->mmio + Firmware_Mask_Register);
830 static void pci_6534_init_main_fpga(struct comedi_device *dev)
832 writel(0, dev->mmio + FPGA_Control1_Register);
833 writel(0, dev->mmio + FPGA_Control2_Register);
834 writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
835 writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
836 writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
837 writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
840 static int pci_6534_upload_firmware(struct comedi_device *dev)
842 struct nidio96_private *devpriv = dev->private;
843 static const char *const fw_file[3] = {
844 FW_PCI_6534_SCARAB_DI, /* loaded into scarab A for DI */
845 FW_PCI_6534_SCARAB_DO, /* loaded into scarab B for DO */
846 FW_PCI_6534_MAIN, /* loaded into main FPGA */
851 ret = pci_6534_reset_fpgas(dev);
854 /* load main FPGA first, then the two scarabs */
855 for (n = 2; n >= 0; n--) {
856 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
858 pci_6534_load_fpga, n);
859 if (ret == 0 && n == 2)
860 pci_6534_init_main_fpga(dev);
867 static void nidio_reset_board(struct comedi_device *dev)
869 writel(0, dev->mmio + PORT_IO(0));
870 writel(0, dev->mmio + PORT_PIN_DIRECTIONS(0));
871 writel(0, dev->mmio + PORT_PIN_MASK(0));
873 /* disable interrupts on board */
874 writeb(0, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
877 static int nidio_auto_attach(struct comedi_device *dev,
878 unsigned long context)
880 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
881 const struct nidio_board *board = NULL;
882 struct nidio96_private *devpriv;
883 struct comedi_subdevice *s;
887 if (context < ARRAY_SIZE(nidio_boards))
888 board = &nidio_boards[context];
891 dev->board_ptr = board;
892 dev->board_name = board->name;
894 ret = comedi_pci_enable(dev);
898 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
902 spin_lock_init(&devpriv->mite_channel_lock);
904 devpriv->mite = mite_attach(dev, false); /* use win0 */
908 devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
909 if (!devpriv->di_mite_ring)
912 if (board->uses_firmware) {
913 ret = pci_6534_upload_firmware(dev);
918 nidio_reset_board(dev);
920 ret = comedi_alloc_subdevices(dev, 1);
924 dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
925 readb(dev->mmio + CHIP_VERSION));
927 s = &dev->subdevices[0];
929 dev->read_subdev = s;
930 s->type = COMEDI_SUBD_DIO;
932 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
935 s->range_table = &range_digital;
937 s->insn_config = &ni_pcidio_insn_config;
938 s->insn_bits = &ni_pcidio_insn_bits;
939 s->do_cmd = &ni_pcidio_cmd;
940 s->do_cmdtest = &ni_pcidio_cmdtest;
941 s->cancel = &ni_pcidio_cancel;
942 s->len_chanlist = 32; /* XXX */
943 s->buf_change = &ni_pcidio_change;
944 s->async_dma_dir = DMA_BIDIRECTIONAL;
945 s->poll = &ni_pcidio_poll;
949 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
950 dev->board_name, dev);
958 static void nidio_detach(struct comedi_device *dev)
960 struct nidio96_private *devpriv = dev->private;
963 free_irq(dev->irq, dev);
965 if (devpriv->di_mite_ring) {
966 mite_free_ring(devpriv->di_mite_ring);
967 devpriv->di_mite_ring = NULL;
969 mite_detach(devpriv->mite);
973 comedi_pci_disable(dev);
976 static struct comedi_driver ni_pcidio_driver = {
977 .driver_name = "ni_pcidio",
978 .module = THIS_MODULE,
979 .auto_attach = nidio_auto_attach,
980 .detach = nidio_detach,
983 static int ni_pcidio_pci_probe(struct pci_dev *dev,
984 const struct pci_device_id *id)
986 return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
989 static const struct pci_device_id ni_pcidio_pci_table[] = {
990 { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
991 { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
992 { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
995 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
997 static struct pci_driver ni_pcidio_pci_driver = {
999 .id_table = ni_pcidio_pci_table,
1000 .probe = ni_pcidio_pci_probe,
1001 .remove = comedi_pci_auto_unconfig,
1003 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1005 MODULE_AUTHOR("Comedi https://www.comedi.org");
1006 MODULE_DESCRIPTION("Comedi low-level driver");
1007 MODULE_LICENSE("GPL");