1 // SPDX-License-Identifier: GPL-2.0+
3 * comedi/drivers/me_daq.c
4 * Hardware driver for Meilhaus data acquisition cards:
5 * ME-2000i, ME-2600i, ME-3000vm1
7 * Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
12 * Description: Meilhaus PCI data acquisition cards
13 * Devices: [Meilhaus] ME-2600i (me-2600i), ME-2000i (me-2000i)
14 * Author: Michael Hillmann <hillmann@syscongroup.de>
15 * Status: experimental
17 * Configuration options: not applicable, uses PCI auto config
20 * Analog Input, Analog Output, Digital I/O
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/comedi/comedi_pci.h>
30 #define ME2600_FIRMWARE "/*(DEBLOBBED)*/"
32 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
35 * PCI BAR2 Memory map (dev->mmio)
37 #define ME_CTRL1_REG 0x00 /* R (ai start) | W */
38 #define ME_CTRL1_INT_ENA BIT(15)
39 #define ME_CTRL1_COUNTER_B_IRQ BIT(12)
40 #define ME_CTRL1_COUNTER_A_IRQ BIT(11)
41 #define ME_CTRL1_CHANLIST_READY_IRQ BIT(10)
42 #define ME_CTRL1_EXT_IRQ BIT(9)
43 #define ME_CTRL1_ADFIFO_HALFFULL_IRQ BIT(8)
44 #define ME_CTRL1_SCAN_COUNT_ENA BIT(5)
45 #define ME_CTRL1_SIMULTANEOUS_ENA BIT(4)
46 #define ME_CTRL1_TRIGGER_FALLING_EDGE BIT(3)
47 #define ME_CTRL1_CONTINUOUS_MODE BIT(2)
48 #define ME_CTRL1_ADC_MODE(x) (((x) & 0x3) << 0)
49 #define ME_CTRL1_ADC_MODE_DISABLE ME_CTRL1_ADC_MODE(0)
50 #define ME_CTRL1_ADC_MODE_SOFT_TRIG ME_CTRL1_ADC_MODE(1)
51 #define ME_CTRL1_ADC_MODE_SCAN_TRIG ME_CTRL1_ADC_MODE(2)
52 #define ME_CTRL1_ADC_MODE_EXT_TRIG ME_CTRL1_ADC_MODE(3)
53 #define ME_CTRL1_ADC_MODE_MASK ME_CTRL1_ADC_MODE(3)
54 #define ME_CTRL2_REG 0x02 /* R (dac update) | W */
55 #define ME_CTRL2_ADFIFO_ENA BIT(10)
56 #define ME_CTRL2_CHANLIST_ENA BIT(9)
57 #define ME_CTRL2_PORT_B_ENA BIT(7)
58 #define ME_CTRL2_PORT_A_ENA BIT(6)
59 #define ME_CTRL2_COUNTER_B_ENA BIT(4)
60 #define ME_CTRL2_COUNTER_A_ENA BIT(3)
61 #define ME_CTRL2_DAC_ENA BIT(1)
62 #define ME_CTRL2_BUFFERED_DAC BIT(0)
63 #define ME_STATUS_REG 0x04 /* R | W (clears interrupts) */
64 #define ME_STATUS_COUNTER_B_IRQ BIT(12)
65 #define ME_STATUS_COUNTER_A_IRQ BIT(11)
66 #define ME_STATUS_CHANLIST_READY_IRQ BIT(10)
67 #define ME_STATUS_EXT_IRQ BIT(9)
68 #define ME_STATUS_ADFIFO_HALFFULL_IRQ BIT(8)
69 #define ME_STATUS_ADFIFO_FULL BIT(4)
70 #define ME_STATUS_ADFIFO_HALFFULL BIT(3)
71 #define ME_STATUS_ADFIFO_EMPTY BIT(2)
72 #define ME_STATUS_CHANLIST_FULL BIT(1)
73 #define ME_STATUS_FST_ACTIVE BIT(0)
74 #define ME_DIO_PORT_A_REG 0x06 /* R | W */
75 #define ME_DIO_PORT_B_REG 0x08 /* R | W */
76 #define ME_TIMER_DATA_REG(x) (0x0a + ((x) * 2)) /* - | W */
77 #define ME_AI_FIFO_REG 0x10 /* R (fifo) | W (chanlist) */
78 #define ME_AI_FIFO_CHANLIST_DIFF BIT(7)
79 #define ME_AI_FIFO_CHANLIST_UNIPOLAR BIT(6)
80 #define ME_AI_FIFO_CHANLIST_GAIN(x) (((x) & 0x3) << 4)
81 #define ME_AI_FIFO_CHANLIST_CHAN(x) (((x) & 0xf) << 0)
82 #define ME_DAC_CTRL_REG 0x12 /* R (updates) | W */
83 #define ME_DAC_CTRL_BIPOLAR(x) BIT(7 - ((x) & 0x3))
84 #define ME_DAC_CTRL_GAIN(x) BIT(11 - ((x) & 0x3))
85 #define ME_DAC_CTRL_MASK(x) (ME_DAC_CTRL_BIPOLAR(x) | \
87 #define ME_AO_DATA_REG(x) (0x14 + ((x) * 2)) /* - | W */
88 #define ME_COUNTER_ENDDATA_REG(x) (0x1c + ((x) * 2)) /* - | W */
89 #define ME_COUNTER_STARTDATA_REG(x) (0x20 + ((x) * 2)) /* - | W */
90 #define ME_COUNTER_VALUE_REG(x) (0x20 + ((x) * 2)) /* R | - */
92 static const struct comedi_lrange me_ai_range = {
105 static const struct comedi_lrange me_ao_range = {
124 static const struct me_board me_boards[] = {
135 struct me_private_data {
136 void __iomem *plx_regbase; /* PLX configuration base address */
138 unsigned short ctrl1; /* Mirror of CONTROL_1 register */
139 unsigned short ctrl2; /* Mirror of CONTROL_2 register */
140 unsigned short dac_ctrl; /* Mirror of the DAC_CONTROL register */
143 static inline void sleep(unsigned int sec)
145 schedule_timeout_interruptible(sec * HZ);
148 static int me_dio_insn_config(struct comedi_device *dev,
149 struct comedi_subdevice *s,
150 struct comedi_insn *insn,
153 struct me_private_data *devpriv = dev->private;
154 unsigned int chan = CR_CHAN(insn->chanspec);
163 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
167 if (s->io_bits & 0x0000ffff)
168 devpriv->ctrl2 |= ME_CTRL2_PORT_A_ENA;
170 devpriv->ctrl2 &= ~ME_CTRL2_PORT_A_ENA;
171 if (s->io_bits & 0xffff0000)
172 devpriv->ctrl2 |= ME_CTRL2_PORT_B_ENA;
174 devpriv->ctrl2 &= ~ME_CTRL2_PORT_B_ENA;
176 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
181 static int me_dio_insn_bits(struct comedi_device *dev,
182 struct comedi_subdevice *s,
183 struct comedi_insn *insn,
186 void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A_REG;
187 void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B_REG;
191 mask = comedi_dio_update_state(s, data);
193 if (mask & 0x0000ffff)
194 writew((s->state & 0xffff), mmio_porta);
195 if (mask & 0xffff0000)
196 writew(((s->state >> 16) & 0xffff), mmio_portb);
199 if (s->io_bits & 0x0000ffff)
200 val = s->state & 0xffff;
202 val = readw(mmio_porta);
204 if (s->io_bits & 0xffff0000)
205 val |= (s->state & 0xffff0000);
207 val |= (readw(mmio_portb) << 16);
214 static int me_ai_eoc(struct comedi_device *dev,
215 struct comedi_subdevice *s,
216 struct comedi_insn *insn,
217 unsigned long context)
221 status = readw(dev->mmio + ME_STATUS_REG);
222 if ((status & ME_STATUS_ADFIFO_EMPTY) == 0)
227 static int me_ai_insn_read(struct comedi_device *dev,
228 struct comedi_subdevice *s,
229 struct comedi_insn *insn,
232 struct me_private_data *devpriv = dev->private;
233 unsigned int chan = CR_CHAN(insn->chanspec);
234 unsigned int range = CR_RANGE(insn->chanspec);
235 unsigned int aref = CR_AREF(insn->chanspec);
241 * For differential operation, there are only 8 input channels
242 * and only bipolar ranges are available.
244 if (aref & AREF_DIFF) {
245 if (chan > 7 || comedi_range_is_unipolar(s, range))
249 /* clear chanlist and ad fifo */
250 devpriv->ctrl2 &= ~(ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA);
251 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
253 writew(0x00, dev->mmio + ME_STATUS_REG); /* clear interrupts */
255 /* enable the chanlist and ADC fifo */
256 devpriv->ctrl2 |= (ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA);
257 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
259 /* write to channel list fifo */
260 val = ME_AI_FIFO_CHANLIST_CHAN(chan) | ME_AI_FIFO_CHANLIST_GAIN(range);
261 if (comedi_range_is_unipolar(s, range))
262 val |= ME_AI_FIFO_CHANLIST_UNIPOLAR;
263 if (aref & AREF_DIFF)
264 val |= ME_AI_FIFO_CHANLIST_DIFF;
265 writew(val, dev->mmio + ME_AI_FIFO_REG);
267 /* set ADC mode to software trigger */
268 devpriv->ctrl1 |= ME_CTRL1_ADC_MODE_SOFT_TRIG;
269 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);
271 for (i = 0; i < insn->n; i++) {
272 /* start ai conversion */
273 readw(dev->mmio + ME_CTRL1_REG);
275 /* wait for ADC fifo not empty flag */
276 ret = comedi_timeout(dev, s, insn, me_ai_eoc, 0);
280 /* get value from ADC fifo */
281 val = readw(dev->mmio + ME_AI_FIFO_REG) & s->maxdata;
283 /* munge 2's complement value to offset binary */
284 data[i] = comedi_offset_munge(s, val);
287 /* stop any running conversion */
288 devpriv->ctrl1 &= ~ME_CTRL1_ADC_MODE_MASK;
289 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);
291 return ret ? ret : insn->n;
294 static int me_ao_insn_write(struct comedi_device *dev,
295 struct comedi_subdevice *s,
296 struct comedi_insn *insn,
299 struct me_private_data *devpriv = dev->private;
300 unsigned int chan = CR_CHAN(insn->chanspec);
301 unsigned int range = CR_RANGE(insn->chanspec);
302 unsigned int val = s->readback[chan];
306 devpriv->ctrl2 |= ME_CTRL2_DAC_ENA;
307 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
309 /* and set DAC to "buffered" mode */
310 devpriv->ctrl2 |= ME_CTRL2_BUFFERED_DAC;
311 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
313 /* Set dac-control register */
314 devpriv->dac_ctrl &= ~ME_DAC_CTRL_MASK(chan);
316 devpriv->dac_ctrl |= ME_DAC_CTRL_GAIN(chan);
317 if (comedi_range_is_bipolar(s, range))
318 devpriv->dac_ctrl |= ME_DAC_CTRL_BIPOLAR(chan);
319 writew(devpriv->dac_ctrl, dev->mmio + ME_DAC_CTRL_REG);
321 /* Update dac-control register */
322 readw(dev->mmio + ME_DAC_CTRL_REG);
324 /* Set data register */
325 for (i = 0; i < insn->n; i++) {
328 writew(val, dev->mmio + ME_AO_DATA_REG(chan));
330 s->readback[chan] = val;
332 /* Update dac with data registers */
333 readw(dev->mmio + ME_CTRL2_REG);
338 static int me2600_xilinx_download(struct comedi_device *dev,
339 const u8 *data, size_t size,
340 unsigned long context)
342 struct me_private_data *devpriv = dev->private;
344 unsigned int file_length;
347 /* disable irq's on PLX */
348 writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR);
350 /* First, make a dummy read to reset xilinx */
351 value = readw(dev->mmio + XILINX_DOWNLOAD_RESET);
353 /* Wait until reset is over */
356 /* Write a dummy value to Xilinx */
357 writeb(0x00, dev->mmio + 0x0);
361 * Format of the firmware
362 * Build longs from the byte-wise coded header
363 * Byte 1-3: length of the array
366 * Byte 12-15: reserved
371 file_length = (((unsigned int)data[0] & 0xff) << 24) +
372 (((unsigned int)data[1] & 0xff) << 16) +
373 (((unsigned int)data[2] & 0xff) << 8) +
374 ((unsigned int)data[3] & 0xff);
377 * Loop for writing firmware byte by byte to xilinx
378 * Firmware data start at offset 16
380 for (i = 0; i < file_length; i++)
381 writeb((data[16 + i] & 0xff), dev->mmio + 0x0);
383 /* Write 5 dummy values to xilinx */
384 for (i = 0; i < 5; i++)
385 writeb(0x00, dev->mmio + 0x0);
387 /* Test if there was an error during download -> INTB was thrown */
388 value = readl(devpriv->plx_regbase + PLX9052_INTCSR);
389 if (value & PLX9052_INTCSR_LI2STAT) {
390 /* Disable interrupt */
391 writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR);
392 dev_err(dev->class_dev, "Xilinx download failed\n");
396 /* Wait until the Xilinx is ready for real work */
399 /* Enable PLX-Interrupts */
400 writel(PLX9052_INTCSR_LI1ENAB |
401 PLX9052_INTCSR_LI1POL |
402 PLX9052_INTCSR_PCIENAB,
403 devpriv->plx_regbase + PLX9052_INTCSR);
408 static int me_reset(struct comedi_device *dev)
410 struct me_private_data *devpriv = dev->private;
413 writew(0x00, dev->mmio + ME_CTRL1_REG);
414 writew(0x00, dev->mmio + ME_CTRL2_REG);
415 writew(0x00, dev->mmio + ME_STATUS_REG); /* clear interrupts */
416 writew(0x00, dev->mmio + ME_DAC_CTRL_REG);
418 /* Save values in the board context */
419 devpriv->dac_ctrl = 0;
426 static int me_auto_attach(struct comedi_device *dev,
427 unsigned long context)
429 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
430 const struct me_board *board = NULL;
431 struct me_private_data *devpriv;
432 struct comedi_subdevice *s;
435 if (context < ARRAY_SIZE(me_boards))
436 board = &me_boards[context];
439 dev->board_ptr = board;
440 dev->board_name = board->name;
442 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
446 ret = comedi_pci_enable(dev);
450 devpriv->plx_regbase = pci_ioremap_bar(pcidev, 0);
451 if (!devpriv->plx_regbase)
454 dev->mmio = pci_ioremap_bar(pcidev, 2);
458 /* Download firmware and reset card */
459 if (board->needs_firmware) {
460 ret = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
462 me2600_xilinx_download, 0);
468 ret = comedi_alloc_subdevices(dev, 3);
472 s = &dev->subdevices[0];
473 s->type = COMEDI_SUBD_AI;
474 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_DIFF;
477 s->len_chanlist = 16;
478 s->range_table = &me_ai_range;
479 s->insn_read = me_ai_insn_read;
481 s = &dev->subdevices[1];
483 s->type = COMEDI_SUBD_AO;
484 s->subdev_flags = SDF_WRITABLE | SDF_COMMON;
488 s->range_table = &me_ao_range;
489 s->insn_write = me_ao_insn_write;
491 ret = comedi_alloc_subdev_readback(s);
495 s->type = COMEDI_SUBD_UNUSED;
498 s = &dev->subdevices[2];
499 s->type = COMEDI_SUBD_DIO;
500 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
503 s->len_chanlist = 32;
504 s->range_table = &range_digital;
505 s->insn_bits = me_dio_insn_bits;
506 s->insn_config = me_dio_insn_config;
511 static void me_detach(struct comedi_device *dev)
513 struct me_private_data *devpriv = dev->private;
518 if (devpriv->plx_regbase)
519 iounmap(devpriv->plx_regbase);
521 comedi_pci_detach(dev);
524 static struct comedi_driver me_daq_driver = {
525 .driver_name = "me_daq",
526 .module = THIS_MODULE,
527 .auto_attach = me_auto_attach,
531 static int me_daq_pci_probe(struct pci_dev *dev,
532 const struct pci_device_id *id)
534 return comedi_pci_auto_config(dev, &me_daq_driver, id->driver_data);
537 static const struct pci_device_id me_daq_pci_table[] = {
538 { PCI_VDEVICE(MEILHAUS, 0x2600), BOARD_ME2600 },
539 { PCI_VDEVICE(MEILHAUS, 0x2000), BOARD_ME2000 },
542 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
544 static struct pci_driver me_daq_pci_driver = {
546 .id_table = me_daq_pci_table,
547 .probe = me_daq_pci_probe,
548 .remove = comedi_pci_auto_unconfig,
550 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
552 MODULE_AUTHOR("Comedi https://www.comedi.org");
553 MODULE_DESCRIPTION("Comedi low-level driver");
554 MODULE_LICENSE("GPL");