1 // SPDX-License-Identifier: GPL-2.0+
3 * comedi/drivers/amplc_dio200_common.c
5 * Common support code for "amplc_dio200" and "amplc_dio200_pci".
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/comedi/comedidev.h>
16 #include <linux/comedi/comedi_8255.h> /* only for register defines */
17 #include <linux/comedi/comedi_8254.h>
19 #include "amplc_dio200.h"
21 /* 200 series registers */
22 #define DIO200_IO_SIZE 0x20
23 #define DIO200_PCIE_IO_SIZE 0x4000
24 #define DIO200_CLK_SCE(x) (0x18 + (x)) /* Group X/Y/Z clock sel reg */
25 #define DIO200_GAT_SCE(x) (0x1b + (x)) /* Group X/Y/Z gate sel reg */
26 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
27 /* Extra registers for new PCIe boards */
28 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
29 #define DIO200_VERSION 0x24 /* Hardware version register */
30 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
31 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
34 * Functions for constructing value for DIO_200_?CLK_SCE and
35 * DIO_200_?GAT_SCE registers:
37 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
38 * 'chan' is the channel: 0, 1 or 2.
39 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
41 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
44 return (which << 5) | (chan << 3) |
45 ((source & 030) << 3) | (source & 007);
49 * Periods of the internal clock sources in nanoseconds.
51 static const unsigned int clock_period[32] = {
52 [1] = 100, /* 10 MHz */
53 [2] = 1000, /* 1 MHz */
54 [3] = 10000, /* 100 kHz */
55 [4] = 100000, /* 10 kHz */
56 [5] = 1000000, /* 1 kHz */
57 [11] = 50, /* 20 MHz (enhanced boards) */
58 /* clock sources 12 and later reserved for enhanced boards */
62 * Timestamp timer configuration register (for new PCIe boards).
64 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
65 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
66 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
69 * Periods of the timestamp timer clock sources in nanoseconds.
71 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
72 1, /* 1 nanosecond (but with 20 ns granularity). */
73 1000, /* 1 microsecond. */
74 1000000, /* 1 millisecond. */
77 struct dio200_subdev_8255 {
78 unsigned int ofs; /* DIO base offset */
81 struct dio200_subdev_intr {
82 spinlock_t spinlock; /* protects the 'active' flag */
84 unsigned int valid_isns;
85 unsigned int enabled_isns;
86 unsigned int active:1;
89 #ifdef CONFIG_HAS_IOPORT
91 static unsigned char dio200___read8(struct comedi_device *dev,
95 return readb(dev->mmio + offset);
96 return inb(dev->iobase + offset);
99 static void dio200___write8(struct comedi_device *dev,
100 unsigned int offset, unsigned char val)
103 writeb(val, dev->mmio + offset);
105 outb(val, dev->iobase + offset);
108 static unsigned int dio200___read32(struct comedi_device *dev,
112 return readl(dev->mmio + offset);
113 return inl(dev->iobase + offset);
116 static void dio200___write32(struct comedi_device *dev,
117 unsigned int offset, unsigned int val)
120 writel(val, dev->mmio + offset);
122 outl(val, dev->iobase + offset);
125 #else /* CONFIG_HAS_IOPORT */
127 static unsigned char dio200___read8(struct comedi_device *dev,
130 return readb(dev->mmio + offset);
133 static void dio200___write8(struct comedi_device *dev,
134 unsigned int offset, unsigned char val)
136 writeb(val, dev->mmio + offset);
139 static unsigned int dio200___read32(struct comedi_device *dev,
142 return readl(dev->mmio + offset);
145 static void dio200___write32(struct comedi_device *dev,
146 unsigned int offset, unsigned int val)
148 writel(val, dev->mmio + offset);
151 #endif /* CONFIG_HAS_IOPORT */
153 static unsigned char dio200_read8(struct comedi_device *dev,
156 const struct dio200_board *board = dev->board_ptr;
161 return dio200___read8(dev, offset);
164 static void dio200_write8(struct comedi_device *dev,
165 unsigned int offset, unsigned char val)
167 const struct dio200_board *board = dev->board_ptr;
172 dio200___write8(dev, offset, val);
175 static unsigned int dio200_read32(struct comedi_device *dev,
178 const struct dio200_board *board = dev->board_ptr;
183 return dio200___read32(dev, offset);
186 static void dio200_write32(struct comedi_device *dev,
187 unsigned int offset, unsigned int val)
189 const struct dio200_board *board = dev->board_ptr;
194 dio200___write32(dev, offset, val);
197 static unsigned int dio200_subdev_8254_offset(struct comedi_device *dev,
198 struct comedi_subdevice *s)
200 const struct dio200_board *board = dev->board_ptr;
201 struct comedi_8254 *i8254 = s->private;
204 /* get the offset that was passed to comedi_8254_*_init() */
206 offset = (void __iomem *)i8254->context - dev->mmio;
208 offset = i8254->context - dev->iobase;
210 /* remove the shift that was added for PCIe boards */
214 /* this offset now works for the dio200_{read,write} helpers */
218 static int dio200_subdev_intr_insn_bits(struct comedi_device *dev,
219 struct comedi_subdevice *s,
220 struct comedi_insn *insn,
223 const struct dio200_board *board = dev->board_ptr;
224 struct dio200_subdev_intr *subpriv = s->private;
226 if (board->has_int_sce) {
227 /* Just read the interrupt status register. */
228 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
230 /* No interrupt status register. */
237 static void dio200_stop_intr(struct comedi_device *dev,
238 struct comedi_subdevice *s)
240 const struct dio200_board *board = dev->board_ptr;
241 struct dio200_subdev_intr *subpriv = s->private;
243 subpriv->active = false;
244 subpriv->enabled_isns = 0;
245 if (board->has_int_sce)
246 dio200_write8(dev, subpriv->ofs, 0);
249 static void dio200_start_intr(struct comedi_device *dev,
250 struct comedi_subdevice *s)
252 const struct dio200_board *board = dev->board_ptr;
253 struct dio200_subdev_intr *subpriv = s->private;
254 struct comedi_cmd *cmd = &s->async->cmd;
256 unsigned int isn_bits;
258 /* Determine interrupt sources to enable. */
261 for (n = 0; n < cmd->chanlist_len; n++)
262 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
264 isn_bits &= subpriv->valid_isns;
265 /* Enable interrupt sources. */
266 subpriv->enabled_isns = isn_bits;
267 if (board->has_int_sce)
268 dio200_write8(dev, subpriv->ofs, isn_bits);
271 static int dio200_inttrig_start_intr(struct comedi_device *dev,
272 struct comedi_subdevice *s,
273 unsigned int trig_num)
275 struct dio200_subdev_intr *subpriv = s->private;
276 struct comedi_cmd *cmd = &s->async->cmd;
279 if (trig_num != cmd->start_arg)
282 spin_lock_irqsave(&subpriv->spinlock, flags);
283 s->async->inttrig = NULL;
285 dio200_start_intr(dev, s);
287 spin_unlock_irqrestore(&subpriv->spinlock, flags);
292 static void dio200_read_scan_intr(struct comedi_device *dev,
293 struct comedi_subdevice *s,
294 unsigned int triggered)
296 struct comedi_cmd *cmd = &s->async->cmd;
301 for (n = 0; n < cmd->chanlist_len; n++) {
302 ch = CR_CHAN(cmd->chanlist[n]);
303 if (triggered & (1U << ch))
307 comedi_buf_write_samples(s, &val, 1);
309 if (cmd->stop_src == TRIG_COUNT &&
310 s->async->scans_done >= cmd->stop_arg)
311 s->async->events |= COMEDI_CB_EOA;
314 static int dio200_handle_read_intr(struct comedi_device *dev,
315 struct comedi_subdevice *s)
317 const struct dio200_board *board = dev->board_ptr;
318 struct dio200_subdev_intr *subpriv = s->private;
319 unsigned int triggered;
320 unsigned int intstat;
321 unsigned int cur_enabled;
326 spin_lock_irqsave(&subpriv->spinlock, flags);
327 if (board->has_int_sce) {
329 * Collect interrupt sources that have triggered and disable
330 * them temporarily. Loop around until no extra interrupt
331 * sources have triggered, at which point, the valid part of
332 * the interrupt status register will read zero, clearing the
333 * cause of the interrupt.
335 * Mask off interrupt sources already seen to avoid infinite
336 * loop in case of misconfiguration.
338 cur_enabled = subpriv->enabled_isns;
339 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
340 subpriv->valid_isns & ~triggered)) != 0) {
341 triggered |= intstat;
342 cur_enabled &= ~triggered;
343 dio200_write8(dev, subpriv->ofs, cur_enabled);
347 * No interrupt status register. Assume the single interrupt
348 * source has triggered.
350 triggered = subpriv->enabled_isns;
355 * Some interrupt sources have triggered and have been
356 * temporarily disabled to clear the cause of the interrupt.
358 * Reenable them NOW to minimize the time they are disabled.
360 cur_enabled = subpriv->enabled_isns;
361 if (board->has_int_sce)
362 dio200_write8(dev, subpriv->ofs, cur_enabled);
364 if (subpriv->active) {
366 * The command is still active.
368 * Ignore interrupt sources that the command isn't
369 * interested in (just in case there's a race
372 if (triggered & subpriv->enabled_isns) {
373 /* Collect scan data. */
374 dio200_read_scan_intr(dev, s, triggered);
378 spin_unlock_irqrestore(&subpriv->spinlock, flags);
380 comedi_handle_events(dev, s);
382 return (triggered != 0);
385 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
386 struct comedi_subdevice *s)
388 struct dio200_subdev_intr *subpriv = s->private;
391 spin_lock_irqsave(&subpriv->spinlock, flags);
393 dio200_stop_intr(dev, s);
395 spin_unlock_irqrestore(&subpriv->spinlock, flags);
400 static int dio200_subdev_intr_cmdtest(struct comedi_device *dev,
401 struct comedi_subdevice *s,
402 struct comedi_cmd *cmd)
406 /* Step 1 : check if triggers are trivially valid */
408 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
409 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
410 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
411 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
412 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
417 /* Step 2a : make sure trigger sources are unique */
419 err |= comedi_check_trigger_is_unique(cmd->start_src);
420 err |= comedi_check_trigger_is_unique(cmd->stop_src);
422 /* Step 2b : and mutually compatible */
427 /* Step 3: check if arguments are trivially valid */
429 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
430 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
431 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
432 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
435 if (cmd->stop_src == TRIG_COUNT)
436 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
438 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
443 /* step 4: fix up any arguments */
445 /* if (err) return 4; */
450 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
451 struct comedi_subdevice *s)
453 struct comedi_cmd *cmd = &s->async->cmd;
454 struct dio200_subdev_intr *subpriv = s->private;
457 spin_lock_irqsave(&subpriv->spinlock, flags);
459 subpriv->active = true;
461 if (cmd->start_src == TRIG_INT)
462 s->async->inttrig = dio200_inttrig_start_intr;
464 dio200_start_intr(dev, s);
466 spin_unlock_irqrestore(&subpriv->spinlock, flags);
471 static int dio200_subdev_intr_init(struct comedi_device *dev,
472 struct comedi_subdevice *s,
474 unsigned int valid_isns)
476 const struct dio200_board *board = dev->board_ptr;
477 struct dio200_subdev_intr *subpriv;
479 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
483 subpriv->ofs = offset;
484 subpriv->valid_isns = valid_isns;
485 spin_lock_init(&subpriv->spinlock);
487 if (board->has_int_sce)
488 /* Disable interrupt sources. */
489 dio200_write8(dev, subpriv->ofs, 0);
491 s->type = COMEDI_SUBD_DI;
492 s->subdev_flags = SDF_READABLE | SDF_CMD_READ | SDF_PACKED;
493 if (board->has_int_sce) {
494 s->n_chan = DIO200_MAX_ISNS;
495 s->len_chanlist = DIO200_MAX_ISNS;
497 /* No interrupt source register. Support single channel. */
501 s->range_table = &range_digital;
503 s->insn_bits = dio200_subdev_intr_insn_bits;
504 s->do_cmdtest = dio200_subdev_intr_cmdtest;
505 s->do_cmd = dio200_subdev_intr_cmd;
506 s->cancel = dio200_subdev_intr_cancel;
511 static irqreturn_t dio200_interrupt(int irq, void *d)
513 struct comedi_device *dev = d;
514 struct comedi_subdevice *s = dev->read_subdev;
520 handled = dio200_handle_read_intr(dev, s);
522 return IRQ_RETVAL(handled);
525 static void dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
526 struct comedi_subdevice *s,
530 unsigned int offset = dio200_subdev_8254_offset(dev, s);
532 dio200_write8(dev, DIO200_GAT_SCE(offset >> 3),
533 clk_gat_sce((offset >> 2) & 1, chan, src));
536 static void dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
537 struct comedi_subdevice *s,
541 unsigned int offset = dio200_subdev_8254_offset(dev, s);
543 dio200_write8(dev, DIO200_CLK_SCE(offset >> 3),
544 clk_gat_sce((offset >> 2) & 1, chan, src));
547 static int dio200_subdev_8254_config(struct comedi_device *dev,
548 struct comedi_subdevice *s,
549 struct comedi_insn *insn,
552 const struct dio200_board *board = dev->board_ptr;
553 struct comedi_8254 *i8254 = s->private;
554 unsigned int chan = CR_CHAN(insn->chanspec);
555 unsigned int max_src = board->is_pcie ? 31 : 7;
558 if (!board->has_clk_gat_sce)
562 case INSN_CONFIG_SET_GATE_SRC:
567 dio200_subdev_8254_set_gate_src(dev, s, chan, src);
568 i8254->gate_src[chan] = src;
570 case INSN_CONFIG_GET_GATE_SRC:
571 data[2] = i8254->gate_src[chan];
573 case INSN_CONFIG_SET_CLOCK_SRC:
578 dio200_subdev_8254_set_clock_src(dev, s, chan, src);
579 i8254->clock_src[chan] = src;
581 case INSN_CONFIG_GET_CLOCK_SRC:
582 data[1] = i8254->clock_src[chan];
583 data[2] = clock_period[i8254->clock_src[chan]];
592 static int dio200_subdev_8254_init(struct comedi_device *dev,
593 struct comedi_subdevice *s,
596 const struct dio200_board *board = dev->board_ptr;
597 struct comedi_8254 *i8254;
598 unsigned int regshift;
602 * PCIe boards need the offset shifted in order to get the
603 * correct base address of the timer.
605 if (board->is_pcie) {
613 i8254 = comedi_8254_mm_alloc(dev->mmio + offset,
614 0, I8254_IO8, regshift);
616 i8254 = comedi_8254_io_alloc(dev->iobase + offset,
617 0, I8254_IO8, regshift);
620 return PTR_ERR(i8254);
622 comedi_8254_subdevice_init(s, i8254);
624 i8254->insn_config = dio200_subdev_8254_config;
627 * There could be multiple timers so this driver does not
628 * use dev->pacer to save the i8254 pointer. Instead,
629 * comedi_8254_subdevice_init() saved the i8254 pointer in
630 * s->private. Mark the subdevice as having private data
631 * to be automatically freed when the device is detached.
633 comedi_set_spriv_auto_free(s);
635 /* Initialize channels. */
636 if (board->has_clk_gat_sce) {
637 for (chan = 0; chan < 3; chan++) {
638 /* Gate source 0 is VCC (logic 1). */
639 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
640 /* Clock source 0 is the dedicated clock input. */
641 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
648 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
649 struct comedi_subdevice *s)
651 struct dio200_subdev_8255 *subpriv = s->private;
654 config = I8255_CTRL_CW;
655 /* 1 in io_bits indicates output, 1 in config indicates input */
656 if (!(s->io_bits & 0x0000ff))
657 config |= I8255_CTRL_A_IO;
658 if (!(s->io_bits & 0x00ff00))
659 config |= I8255_CTRL_B_IO;
660 if (!(s->io_bits & 0x0f0000))
661 config |= I8255_CTRL_C_LO_IO;
662 if (!(s->io_bits & 0xf00000))
663 config |= I8255_CTRL_C_HI_IO;
664 dio200_write8(dev, subpriv->ofs + I8255_CTRL_REG, config);
667 static int dio200_subdev_8255_bits(struct comedi_device *dev,
668 struct comedi_subdevice *s,
669 struct comedi_insn *insn,
672 struct dio200_subdev_8255 *subpriv = s->private;
676 mask = comedi_dio_update_state(s, data);
679 dio200_write8(dev, subpriv->ofs + I8255_DATA_A_REG,
683 dio200_write8(dev, subpriv->ofs + I8255_DATA_B_REG,
684 (s->state >> 8) & 0xff);
686 if (mask & 0xff0000) {
687 dio200_write8(dev, subpriv->ofs + I8255_DATA_C_REG,
688 (s->state >> 16) & 0xff);
692 val = dio200_read8(dev, subpriv->ofs + I8255_DATA_A_REG);
693 val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_B_REG) << 8;
694 val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_C_REG) << 16;
701 static int dio200_subdev_8255_config(struct comedi_device *dev,
702 struct comedi_subdevice *s,
703 struct comedi_insn *insn,
706 unsigned int chan = CR_CHAN(insn->chanspec);
719 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
723 dio200_subdev_8255_set_dir(dev, s);
728 static int dio200_subdev_8255_init(struct comedi_device *dev,
729 struct comedi_subdevice *s,
732 struct dio200_subdev_8255 *subpriv;
734 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
738 subpriv->ofs = offset;
740 s->type = COMEDI_SUBD_DIO;
741 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
743 s->range_table = &range_digital;
745 s->insn_bits = dio200_subdev_8255_bits;
746 s->insn_config = dio200_subdev_8255_config;
747 dio200_subdev_8255_set_dir(dev, s);
751 static int dio200_subdev_timer_read(struct comedi_device *dev,
752 struct comedi_subdevice *s,
753 struct comedi_insn *insn,
758 for (n = 0; n < insn->n; n++)
759 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
763 static void dio200_subdev_timer_reset(struct comedi_device *dev,
764 struct comedi_subdevice *s)
768 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
769 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
770 dio200_write32(dev, DIO200_TS_CONFIG, clock);
773 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
774 struct comedi_subdevice *s,
776 unsigned int *period)
780 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
782 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
783 ts_clock_period[clk] : 0;
786 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
787 struct comedi_subdevice *s,
790 if (src > TS_CONFIG_MAX_CLK_SRC)
792 dio200_write32(dev, DIO200_TS_CONFIG, src);
796 static int dio200_subdev_timer_config(struct comedi_device *dev,
797 struct comedi_subdevice *s,
798 struct comedi_insn *insn,
804 case INSN_CONFIG_RESET:
805 dio200_subdev_timer_reset(dev, s);
807 case INSN_CONFIG_SET_CLOCK_SRC:
808 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
812 case INSN_CONFIG_GET_CLOCK_SRC:
813 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
819 return ret < 0 ? ret : insn->n;
822 void amplc_dio200_set_enhance(struct comedi_device *dev, unsigned char val)
824 dio200_write8(dev, DIO200_ENHANCE, val);
826 EXPORT_SYMBOL_GPL(amplc_dio200_set_enhance);
828 int amplc_dio200_common_attach(struct comedi_device *dev, unsigned int irq,
829 unsigned long req_irq_flags)
831 const struct dio200_board *board = dev->board_ptr;
832 struct comedi_subdevice *s;
836 if (!IS_ENABLED(CONFIG_HAS_IOPORT) && !dev->mmio) {
837 dev_err(dev->class_dev,
838 "error! need I/O port support\n");
842 ret = comedi_alloc_subdevices(dev, board->n_subdevs);
846 for (n = 0; n < dev->n_subdevices; n++) {
847 s = &dev->subdevices[n];
848 switch (board->sdtype[n]) {
850 /* counter subdevice (8254) */
851 ret = dio200_subdev_8254_init(dev, s,
857 /* digital i/o subdevice (8255) */
858 ret = dio200_subdev_8255_init(dev, s,
864 /* 'INTERRUPT' subdevice */
865 if (irq && !dev->read_subdev) {
866 ret = dio200_subdev_intr_init(dev, s,
871 dev->read_subdev = s;
873 s->type = COMEDI_SUBD_UNUSED;
877 s->type = COMEDI_SUBD_TIMER;
878 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
880 s->maxdata = 0xffffffff;
881 s->insn_read = dio200_subdev_timer_read;
882 s->insn_config = dio200_subdev_timer_config;
885 s->type = COMEDI_SUBD_UNUSED;
890 if (irq && dev->read_subdev) {
891 if (request_irq(irq, dio200_interrupt, req_irq_flags,
892 dev->board_name, dev) >= 0) {
895 dev_warn(dev->class_dev,
896 "warning! irq %u unavailable!\n", irq);
902 EXPORT_SYMBOL_GPL(amplc_dio200_common_attach);
904 static int __init amplc_dio200_common_init(void)
908 module_init(amplc_dio200_common_init);
910 static void __exit amplc_dio200_common_exit(void)
913 module_exit(amplc_dio200_common_exit);
915 MODULE_AUTHOR("Comedi https://www.comedi.org");
916 MODULE_DESCRIPTION("Comedi helper for amplc_dio200 and amplc_dio200_pci");
917 MODULE_LICENSE("GPL");