drivers/comedi/drivers/adv_pci_dio.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * comedi/drivers/adv_pci_dio.c
   4  *
   5  * Author: Michal Dobes <dobes@tesnet.cz>
   6  *
   7  *  Hardware driver for Advantech PCI DIO cards.
   8  */
   9
  10 /*
  11  * Driver: adv_pci_dio
  12  * Description: Advantech Digital I/O Cards
  13  * Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
  14  *   PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
  15  *   PCI-1751, PCI-1752, PCI-1753, PCI-1753+PCI-1753E,
  16  *   PCI-1754, PCI-1756, PCI-1761, PCI-1762
  17  * Author: Michal Dobes <dobes@tesnet.cz>
  18  * Updated: Fri, 25 Aug 2017 07:23:06 +0300
  19  * Status: untested
  20  *
  21  * Configuration Options: not applicable, uses PCI auto config
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/delay.h>
  26 #include <linux/comedi/comedi_pci.h>
  27 #include <linux/comedi/comedi_8255.h>
  28 #include <linux/comedi/comedi_8254.h>
  29
  30 /*
  31  * Register offset definitions
  32  */
  33
  34 /* PCI-1730, PCI-1733, PCI-1736 interrupt control registers */
  35 #define PCI173X_INT_EN_REG      0x0008  /* R/W: enable/disable */
  36 #define PCI173X_INT_RF_REG      0x000c  /* R/W: falling/rising edge */
  37 #define PCI173X_INT_FLAG_REG    0x0010  /* R: status */
  38 #define PCI173X_INT_CLR_REG     0x0010  /* W: clear */
  39
  40 #define PCI173X_INT_IDI0 0x01  /* IDI0 edge occurred */
  41 #define PCI173X_INT_IDI1 0x02  /* IDI1 edge occurred */
  42 #define PCI173X_INT_DI0  0x04  /* DI0 edge occurred */
  43 #define PCI173X_INT_DI1  0x08  /* DI1 edge occurred */
  44
  45 /* PCI-1739U, PCI-1750, PCI1751 interrupt control registers */
  46 #define PCI1750_INT_REG         0x20    /* R/W: status/control */
  47
  48 /* PCI-1753, PCI-1753E interrupt control registers */
  49 #define PCI1753_INT_REG(x)      (0x10 + (x)) /* R/W: control group 0 to 3 */
  50 #define PCI1753E_INT_REG(x)     (0x30 + (x)) /* R/W: control group 0 to 3 */
  51
  52 /* PCI-1754, PCI-1756 interrupt control registers */
  53 #define PCI1754_INT_REG(x)      (0x08 + (x) * 2) /* R/W: control group 0 to 3 */
  54
  55 /* PCI-1752, PCI-1756 special registers */
  56 #define PCI1752_CFC_REG         0x12    /* R/W: channel freeze function */
  57
  58 /* PCI-1761 interrupt control registers */
  59 #define PCI1761_INT_EN_REG      0x03    /* R/W: enable/disable interrupts */
  60 #define PCI1761_INT_RF_REG      0x04    /* R/W: falling/rising edge */
  61 #define PCI1761_INT_CLR_REG     0x05    /* R/W: clear interrupts */
  62
  63 /* PCI-1762 interrupt control registers */
  64 #define PCI1762_INT_REG         0x06    /* R/W: status/control */
  65
  66 /* maximum number of subdevice descriptions in the boardinfo */
  67 #define PCI_DIO_MAX_DI_SUBDEVS  2       /* 2 x 8/16/32 input channels max */
  68 #define PCI_DIO_MAX_DO_SUBDEVS  2       /* 2 x 8/16/32 output channels max */
  69 #define PCI_DIO_MAX_DIO_SUBDEVG 2       /* 2 x any number of 8255 devices max */
  70 #define PCI_DIO_MAX_IRQ_SUBDEVS 4       /* 4 x 1 input IRQ channels max */
  71
  72 enum pci_dio_boardid {
  73         TYPE_PCI1730,
  74         TYPE_PCI1733,
  75         TYPE_PCI1734,
  76         TYPE_PCI1735,
  77         TYPE_PCI1736,
  78         TYPE_PCI1739,
  79         TYPE_PCI1750,
  80         TYPE_PCI1751,
  81         TYPE_PCI1752,
  82         TYPE_PCI1753,
  83         TYPE_PCI1753E,
  84         TYPE_PCI1754,
  85         TYPE_PCI1756,
  86         TYPE_PCI1761,
  87         TYPE_PCI1762
  88 };
  89
  90 struct diosubd_data {
  91         int chans;              /*  num of chans or 8255 devices */
  92         unsigned long addr;     /*  PCI address offset */
  93 };
  94
  95 struct dio_irq_subd_data {
  96         unsigned short int_en;          /* interrupt enable/status bit */
  97         unsigned long addr;             /* PCI address offset */
  98 };
  99
 100 struct dio_boardtype {
 101         const char *name;       /*  board name */
 102         int nsubdevs;
 103         struct diosubd_data sdi[PCI_DIO_MAX_DI_SUBDEVS];
 104         struct diosubd_data sdo[PCI_DIO_MAX_DO_SUBDEVS];
 105         struct diosubd_data sdio[PCI_DIO_MAX_DIO_SUBDEVG];
 106         struct dio_irq_subd_data sdirq[PCI_DIO_MAX_IRQ_SUBDEVS];
 107         unsigned long id_reg;
 108         unsigned long timer_regbase;
 109         unsigned int is_16bit:1;
 110 };
 111
 112 static const struct dio_boardtype boardtypes[] = {
 113         [TYPE_PCI1730] = {
 114                 .name           = "pci1730",
 115                 /* DI, IDI, DO, IDO, ID, IRQ_DI0, IRQ_DI1, IRQ_IDI0, IRQ_IDI1 */
 116                 .nsubdevs       = 9,
 117                 .sdi[0]         = { 16, 0x02, },        /* DI 0-15 */
 118                 .sdi[1]         = { 16, 0x00, },        /* ISO DI 0-15 */
 119                 .sdo[0]         = { 16, 0x02, },        /* DO 0-15 */
 120                 .sdo[1]         = { 16, 0x00, },        /* ISO DO 0-15 */
 121                 .id_reg         = 0x04,
 122                 .sdirq[0]       = { PCI173X_INT_DI0,  0x02, },  /* DI 0 */
 123                 .sdirq[1]       = { PCI173X_INT_DI1,  0x02, },  /* DI 1 */
 124                 .sdirq[2]       = { PCI173X_INT_IDI0, 0x00, },  /* ISO DI 0 */
 125                 .sdirq[3]       = { PCI173X_INT_IDI1, 0x00, },  /* ISO DI 1 */
 126         },
 127         [TYPE_PCI1733] = {
 128                 .name           = "pci1733",
 129                 .nsubdevs       = 2,
 130                 .sdi[1]         = { 32, 0x00, },        /* ISO DI 0-31 */
 131                 .id_reg         = 0x04,
 132         },
 133         [TYPE_PCI1734] = {
 134                 .name           = "pci1734",
 135                 .nsubdevs       = 2,
 136                 .sdo[1]         = { 32, 0x00, },        /* ISO DO 0-31 */
 137                 .id_reg         = 0x04,
 138         },
 139         [TYPE_PCI1735] = {
 140                 .name           = "pci1735",
 141                 .nsubdevs       = 4,
 142                 .sdi[0]         = { 32, 0x00, },        /* DI 0-31 */
 143                 .sdo[0]         = { 32, 0x00, },        /* DO 0-31 */
 144                 .id_reg         = 0x08,
 145                 .timer_regbase  = 0x04,
 146         },
 147         [TYPE_PCI1736] = {
 148                 .name           = "pci1736",
 149                 .nsubdevs       = 3,
 150                 .sdi[1]         = { 16, 0x00, },        /* ISO DI 0-15 */
 151                 .sdo[1]         = { 16, 0x00, },        /* ISO DO 0-15 */
 152                 .id_reg         = 0x04,
 153         },
 154         [TYPE_PCI1739] = {
 155                 .name           = "pci1739",
 156                 .nsubdevs       = 3,
 157                 .sdio[0]        = { 2, 0x00, },         /* 8255 DIO */
 158                 .id_reg         = 0x08,
 159         },
 160         [TYPE_PCI1750] = {
 161                 .name           = "pci1750",
 162                 .nsubdevs       = 2,
 163                 .sdi[1]         = { 16, 0x00, },        /* ISO DI 0-15 */
 164                 .sdo[1]         = { 16, 0x00, },        /* ISO DO 0-15 */
 165         },
 166         [TYPE_PCI1751] = {
 167                 .name           = "pci1751",
 168                 .nsubdevs       = 3,
 169                 .sdio[0]        = { 2, 0x00, },         /* 8255 DIO */
 170                 .timer_regbase  = 0x18,
 171         },
 172         [TYPE_PCI1752] = {
 173                 .name           = "pci1752",
 174                 .nsubdevs       = 3,
 175                 .sdo[0]         = { 32, 0x00, },        /* DO 0-31 */
 176                 .sdo[1]         = { 32, 0x04, },        /* DO 32-63 */
 177                 .id_reg         = 0x10,
 178                 .is_16bit       = 1,
 179         },
 180         [TYPE_PCI1753] = {
 181                 .name           = "pci1753",
 182                 .nsubdevs       = 4,
 183                 .sdio[0]        = { 4, 0x00, },         /* 8255 DIO */
 184         },
 185         [TYPE_PCI1753E] = {
 186                 .name           = "pci1753e",
 187                 .nsubdevs       = 8,
 188                 .sdio[0]        = { 4, 0x00, },         /* 8255 DIO */
 189                 .sdio[1]        = { 4, 0x20, },         /* 8255 DIO */
 190         },
 191         [TYPE_PCI1754] = {
 192                 .name           = "pci1754",
 193                 .nsubdevs       = 3,
 194                 .sdi[0]         = { 32, 0x00, },        /* DI 0-31 */
 195                 .sdi[1]         = { 32, 0x04, },        /* DI 32-63 */
 196                 .id_reg         = 0x10,
 197                 .is_16bit       = 1,
 198         },
 199         [TYPE_PCI1756] = {
 200                 .name           = "pci1756",
 201                 .nsubdevs       = 3,
 202                 .sdi[1]         = { 32, 0x00, },        /* DI 0-31 */
 203                 .sdo[1]         = { 32, 0x04, },        /* DO 0-31 */
 204                 .id_reg         = 0x10,
 205                 .is_16bit       = 1,
 206         },
 207         [TYPE_PCI1761] = {
 208                 .name           = "pci1761",
 209                 .nsubdevs       = 3,
 210                 .sdi[1]         = { 8, 0x01 },          /* ISO DI 0-7 */
 211                 .sdo[1]         = { 8, 0x00 },          /* RELAY DO 0-7 */
 212                 .id_reg         = 0x02,
 213         },
 214         [TYPE_PCI1762] = {
 215                 .name           = "pci1762",
 216                 .nsubdevs       = 3,
 217                 .sdi[1]         = { 16, 0x02, },        /* ISO DI 0-15 */
 218                 .sdo[1]         = { 16, 0x00, },        /* ISO DO 0-15 */
 219                 .id_reg         = 0x04,
 220                 .is_16bit       = 1,
 221         },
 222 };
 223
 224 struct pci_dio_dev_private_data {
 225         int boardtype;
 226         int irq_subd;
 227         unsigned short int_ctrl;
 228         unsigned short int_rf;
 229 };
 230
 231 struct pci_dio_sd_private_data {
 232         spinlock_t subd_slock;          /* spin-lock for cmd_running */
 233         unsigned long port_offset;
 234         short int cmd_running;
 235 };
 236
 237 static void process_irq(struct comedi_device *dev, unsigned int subdev,
 238                         unsigned char irqflags)
 239 {
 240         struct comedi_subdevice *s = &dev->subdevices[subdev];
 241         struct pci_dio_sd_private_data *sd_priv = s->private;
 242         unsigned long reg = sd_priv->port_offset;
 243         struct comedi_async *async_p = s->async;
 244
 245         if (async_p) {
 246                 unsigned short val = inw(dev->iobase + reg);
 247
 248                 spin_lock(&sd_priv->subd_slock);
 249                 if (sd_priv->cmd_running)
 250                         comedi_buf_write_samples(s, &val, 1);
 251                 spin_unlock(&sd_priv->subd_slock);
 252                 comedi_handle_events(dev, s);
 253         }
 254 }
 255
 256 static irqreturn_t pci_dio_interrupt(int irq, void *p_device)
 257 {
 258         struct comedi_device *dev = p_device;
 259         struct pci_dio_dev_private_data *dev_private = dev->private;
 260         const struct dio_boardtype *board = dev->board_ptr;
 261         unsigned long cpu_flags;
 262         unsigned char irqflags;
 263         int i;
 264
 265         if (!dev->attached) {
 266                 /* Ignore interrupt before device fully attached. */
 267                 /* Might not even have allocated subdevices yet! */
 268                 return IRQ_NONE;
 269         }
 270
 271         /* Check if we are source of interrupt */
 272         spin_lock_irqsave(&dev->spinlock, cpu_flags);
 273         irqflags = inb(dev->iobase + PCI173X_INT_FLAG_REG);
 274         if (!(irqflags & 0x0F)) {
 275                 spin_unlock_irqrestore(&dev->spinlock, cpu_flags);
 276                 return IRQ_NONE;
 277         }
 278
 279         /* clear all current interrupt flags */
 280         outb(irqflags, dev->iobase + PCI173X_INT_CLR_REG);
 281         spin_unlock_irqrestore(&dev->spinlock, cpu_flags);
 282
 283         /* check irq subdevice triggers */
 284         for (i = 0; i < PCI_DIO_MAX_IRQ_SUBDEVS; i++) {
 285                 if (irqflags & board->sdirq[i].int_en)
 286                         process_irq(dev, dev_private->irq_subd + i, irqflags);
 287         }
 288
 289         return IRQ_HANDLED;
 290 }
 291
 292 static int pci_dio_asy_cmdtest(struct comedi_device *dev,
 293                                struct comedi_subdevice *s,
 294                                struct comedi_cmd *cmd)
 295 {
 296         int err = 0;
 297
 298         /* Step 1 : check if triggers are trivially valid */
 299
 300         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
 301         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
 302         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
 303         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 304         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
 305
 306         if (err)
 307                 return 1;
 308
 309         /* Step 2a : make sure trigger sources are unique */
 310         /* Step 2b : and mutually compatible */
 311
 312         /* Step 3: check if arguments are trivially valid */
 313
 314         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
 315         /*
 316          * For scan_begin_arg, the trigger number must be 0 and the only
 317          * allowed flags are CR_EDGE and CR_INVERT.  CR_EDGE is ignored,
 318          * CR_INVERT sets the trigger to falling edge.
 319          */
 320         if (cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) {
 321                 cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
 322                 err |= -EINVAL;
 323         }
 324         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
 325         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
 326                                            cmd->chanlist_len);
 327         err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
 328
 329         if (err)
 330                 return 3;
 331
 332         /* Step 4: fix up any arguments */
 333
 334         /* Step 5: check channel list if it exists */
 335
 336         return 0;
 337 }
 338
 339 static int pci_dio_asy_cmd(struct comedi_device *dev,
 340                            struct comedi_subdevice *s)
 341 {
 342         struct pci_dio_dev_private_data *dev_private = dev->private;
 343         struct pci_dio_sd_private_data *sd_priv = s->private;
 344         const struct dio_boardtype *board = dev->board_ptr;
 345         struct comedi_cmd *cmd = &s->async->cmd;
 346         unsigned long cpu_flags;
 347         unsigned short int_en;
 348
 349         int_en = board->sdirq[s->index - dev_private->irq_subd].int_en;
 350
 351         spin_lock_irqsave(&dev->spinlock, cpu_flags);
 352         if (cmd->scan_begin_arg & CR_INVERT)
 353                 dev_private->int_rf |= int_en;  /* falling edge */
 354         else
 355                 dev_private->int_rf &= ~int_en; /* rising edge */
 356         outb(dev_private->int_rf, dev->iobase + PCI173X_INT_RF_REG);
 357         dev_private->int_ctrl |= int_en;        /* enable interrupt source */
 358         outb(dev_private->int_ctrl, dev->iobase + PCI173X_INT_EN_REG);
 359         spin_unlock_irqrestore(&dev->spinlock, cpu_flags);
 360
 361         spin_lock_irqsave(&sd_priv->subd_slock, cpu_flags);
 362         sd_priv->cmd_running = 1;
 363         spin_unlock_irqrestore(&sd_priv->subd_slock, cpu_flags);
 364
 365         return 0;
 366 }
 367
 368 static int pci_dio_asy_cancel(struct comedi_device *dev,
 369                               struct comedi_subdevice *s)
 370 {
 371         struct pci_dio_dev_private_data *dev_private = dev->private;
 372         struct pci_dio_sd_private_data *sd_priv = s->private;
 373         const struct dio_boardtype *board = dev->board_ptr;
 374         unsigned long cpu_flags;
 375         unsigned short int_en;
 376
 377         spin_lock_irqsave(&sd_priv->subd_slock, cpu_flags);
 378         sd_priv->cmd_running = 0;
 379         spin_unlock_irqrestore(&sd_priv->subd_slock, cpu_flags);
 380
 381         int_en = board->sdirq[s->index - dev_private->irq_subd].int_en;
 382
 383         spin_lock_irqsave(&dev->spinlock, cpu_flags);
 384         dev_private->int_ctrl &= ~int_en;
 385         outb(dev_private->int_ctrl, dev->iobase + PCI173X_INT_EN_REG);
 386         spin_unlock_irqrestore(&dev->spinlock, cpu_flags);
 387
 388         return 0;
 389 }
 390
 391 /* same as _insn_bits_di_ because the IRQ-pins are the DI-ports  */
 392 static int pci_dio_insn_bits_dirq_b(struct comedi_device *dev,
 393                                     struct comedi_subdevice *s,
 394                                     struct comedi_insn *insn,
 395                                     unsigned int *data)
 396 {
 397         struct pci_dio_sd_private_data *sd_priv = s->private;
 398         unsigned long reg = (unsigned long)sd_priv->port_offset;
 399         unsigned long iobase = dev->iobase + reg;
 400
 401         data[1] = inb(iobase);
 402
 403         return insn->n;
 404 }
 405
 406 static int pci_dio_insn_bits_di_b(struct comedi_device *dev,
 407                                   struct comedi_subdevice *s,
 408                                   struct comedi_insn *insn,
 409                                   unsigned int *data)
 410 {
 411         unsigned long reg = (unsigned long)s->private;
 412         unsigned long iobase = dev->iobase + reg;
 413
 414         data[1] = inb(iobase);
 415         if (s->n_chan > 8)
 416                 data[1] |= (inb(iobase + 1) << 8);
 417         if (s->n_chan > 16)
 418                 data[1] |= (inb(iobase + 2) << 16);
 419         if (s->n_chan > 24)
 420                 data[1] |= (inb(iobase + 3) << 24);
 421
 422         return insn->n;
 423 }
 424
 425 static int pci_dio_insn_bits_di_w(struct comedi_device *dev,
 426                                   struct comedi_subdevice *s,
 427                                   struct comedi_insn *insn,
 428                                   unsigned int *data)
 429 {
 430         unsigned long reg = (unsigned long)s->private;
 431         unsigned long iobase = dev->iobase + reg;
 432
 433         data[1] = inw(iobase);
 434         if (s->n_chan > 16)
 435                 data[1] |= (inw(iobase + 2) << 16);
 436
 437         return insn->n;
 438 }
 439
 440 static int pci_dio_insn_bits_do_b(struct comedi_device *dev,
 441                                   struct comedi_subdevice *s,
 442                                   struct comedi_insn *insn,
 443                                   unsigned int *data)
 444 {
 445         unsigned long reg = (unsigned long)s->private;
 446         unsigned long iobase = dev->iobase + reg;
 447
 448         if (comedi_dio_update_state(s, data)) {
 449                 outb(s->state & 0xff, iobase);
 450                 if (s->n_chan > 8)
 451                         outb((s->state >> 8) & 0xff, iobase + 1);
 452                 if (s->n_chan > 16)
 453                         outb((s->state >> 16) & 0xff, iobase + 2);
 454                 if (s->n_chan > 24)
 455                         outb((s->state >> 24) & 0xff, iobase + 3);
 456         }
 457
 458         data[1] = s->state;
 459
 460         return insn->n;
 461 }
 462
 463 static int pci_dio_insn_bits_do_w(struct comedi_device *dev,
 464                                   struct comedi_subdevice *s,
 465                                   struct comedi_insn *insn,
 466                                   unsigned int *data)
 467 {
 468         unsigned long reg = (unsigned long)s->private;
 469         unsigned long iobase = dev->iobase + reg;
 470
 471         if (comedi_dio_update_state(s, data)) {
 472                 outw(s->state & 0xffff, iobase);
 473                 if (s->n_chan > 16)
 474                         outw((s->state >> 16) & 0xffff, iobase + 2);
 475         }
 476
 477         data[1] = s->state;
 478
 479         return insn->n;
 480 }
 481
 482 static int pci_dio_reset(struct comedi_device *dev, unsigned long cardtype)
 483 {
 484         struct pci_dio_dev_private_data *dev_private = dev->private;
 485         /* disable channel freeze function on the PCI-1752/1756 boards */
 486         if (cardtype == TYPE_PCI1752 || cardtype == TYPE_PCI1756)
 487                 outw(0, dev->iobase + PCI1752_CFC_REG);
 488
 489         /* disable and clear interrupts */
 490         switch (cardtype) {
 491         case TYPE_PCI1730:
 492         case TYPE_PCI1733:
 493         case TYPE_PCI1736:
 494                 dev_private->int_ctrl = 0x00;
 495                 outb(dev_private->int_ctrl, dev->iobase + PCI173X_INT_EN_REG);
 496                 /* Reset all 4 Int Flags */
 497                 outb(0x0f, dev->iobase + PCI173X_INT_CLR_REG);
 498                 /* Rising Edge => IRQ . On all 4 Pins */
 499                 dev_private->int_rf = 0x00;
 500                 outb(dev_private->int_rf, dev->iobase + PCI173X_INT_RF_REG);
 501                 break;
 502         case TYPE_PCI1739:
 503         case TYPE_PCI1750:
 504         case TYPE_PCI1751:
 505                 outb(0x88, dev->iobase + PCI1750_INT_REG);
 506                 break;
 507         case TYPE_PCI1753:
 508         case TYPE_PCI1753E:
 509                 outb(0x88, dev->iobase + PCI1753_INT_REG(0));
 510                 outb(0x80, dev->iobase + PCI1753_INT_REG(1));
 511                 outb(0x80, dev->iobase + PCI1753_INT_REG(2));
 512                 outb(0x80, dev->iobase + PCI1753_INT_REG(3));
 513                 if (cardtype == TYPE_PCI1753E) {
 514                         outb(0x88, dev->iobase + PCI1753E_INT_REG(0));
 515                         outb(0x80, dev->iobase + PCI1753E_INT_REG(1));
 516                         outb(0x80, dev->iobase + PCI1753E_INT_REG(2));
 517                         outb(0x80, dev->iobase + PCI1753E_INT_REG(3));
 518                 }
 519                 break;
 520         case TYPE_PCI1754:
 521         case TYPE_PCI1756:
 522                 outw(0x08, dev->iobase + PCI1754_INT_REG(0));
 523                 outw(0x08, dev->iobase + PCI1754_INT_REG(1));
 524                 if (cardtype == TYPE_PCI1754) {
 525                         outw(0x08, dev->iobase + PCI1754_INT_REG(2));
 526                         outw(0x08, dev->iobase + PCI1754_INT_REG(3));
 527                 }
 528                 break;
 529         case TYPE_PCI1761:
 530                 /* disable interrupts */
 531                 outb(0, dev->iobase + PCI1761_INT_EN_REG);
 532                 /* clear interrupts */
 533                 outb(0xff, dev->iobase + PCI1761_INT_CLR_REG);
 534                 /* set rising edge trigger */
 535                 outb(0, dev->iobase + PCI1761_INT_RF_REG);
 536                 break;
 537         case TYPE_PCI1762:
 538                 outw(0x0101, dev->iobase + PCI1762_INT_REG);
 539                 break;
 540         default:
 541                 break;
 542         }
 543
 544         return 0;
 545 }
 546
 547 static int pci_dio_auto_attach(struct comedi_device *dev,
 548                                unsigned long context)
 549 {
 550         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 551         const struct dio_boardtype *board = NULL;
 552         struct comedi_subdevice *s;
 553         struct pci_dio_dev_private_data *dev_private;
 554         int ret, subdev, i, j;
 555
 556         if (context < ARRAY_SIZE(boardtypes))
 557                 board = &boardtypes[context];
 558         if (!board)
 559                 return -ENODEV;
 560         dev->board_ptr = board;
 561         dev->board_name = board->name;
 562
 563         dev_private = comedi_alloc_devpriv(dev, sizeof(*dev_private));
 564         if (!dev_private)
 565                 return -ENOMEM;
 566
 567         ret = comedi_pci_enable(dev);
 568         if (ret)
 569                 return ret;
 570         if (context == TYPE_PCI1736)
 571                 dev->iobase = pci_resource_start(pcidev, 0);
 572         else
 573                 dev->iobase = pci_resource_start(pcidev, 2);
 574
 575         dev_private->boardtype = context;
 576         pci_dio_reset(dev, context);
 577
 578         /* request IRQ if device has irq subdevices */
 579         if (board->sdirq[0].int_en && pcidev->irq) {
 580                 ret = request_irq(pcidev->irq, pci_dio_interrupt, IRQF_SHARED,
 581                                   dev->board_name, dev);
 582                 if (ret == 0)
 583                         dev->irq = pcidev->irq;
 584         }
 585
 586         ret = comedi_alloc_subdevices(dev, board->nsubdevs);
 587         if (ret)
 588                 return ret;
 589
 590         subdev = 0;
 591         for (i = 0; i < PCI_DIO_MAX_DI_SUBDEVS; i++) {
 592                 const struct diosubd_data *d = &board->sdi[i];
 593
 594                 if (d->chans) {
 595                         s = &dev->subdevices[subdev++];
 596                         s->type         = COMEDI_SUBD_DI;
 597                         s->subdev_flags = SDF_READABLE;
 598                         s->n_chan       = d->chans;
 599                         s->maxdata      = 1;
 600                         s->range_table  = &range_digital;
 601                         s->insn_bits    = board->is_16bit
 602                                                 ? pci_dio_insn_bits_di_w
 603                                                 : pci_dio_insn_bits_di_b;
 604                         s->private      = (void *)d->addr;
 605                 }
 606         }
 607
 608         for (i = 0; i < PCI_DIO_MAX_DO_SUBDEVS; i++) {
 609                 const struct diosubd_data *d = &board->sdo[i];
 610
 611                 if (d->chans) {
 612                         s = &dev->subdevices[subdev++];
 613                         s->type         = COMEDI_SUBD_DO;
 614                         s->subdev_flags = SDF_WRITABLE;
 615                         s->n_chan       = d->chans;
 616                         s->maxdata      = 1;
 617                         s->range_table  = &range_digital;
 618                         s->insn_bits    = board->is_16bit
 619                                                 ? pci_dio_insn_bits_do_w
 620                                                 : pci_dio_insn_bits_do_b;
 621                         s->private      = (void *)d->addr;
 622
 623                         /* reset all outputs to 0 */
 624                         if (board->is_16bit) {
 625                                 outw(0, dev->iobase + d->addr);
 626                                 if (s->n_chan > 16)
 627                                         outw(0, dev->iobase + d->addr + 2);
 628                         } else {
 629                                 outb(0, dev->iobase + d->addr);
 630                                 if (s->n_chan > 8)
 631                                         outb(0, dev->iobase + d->addr + 1);
 632                                 if (s->n_chan > 16)
 633                                         outb(0, dev->iobase + d->addr + 2);
 634                                 if (s->n_chan > 24)
 635                                         outb(0, dev->iobase + d->addr + 3);
 636                         }
 637                 }
 638         }
 639
 640         for (i = 0; i < PCI_DIO_MAX_DIO_SUBDEVG; i++) {
 641                 const struct diosubd_data *d = &board->sdio[i];
 642
 643                 for (j = 0; j < d->chans; j++) {
 644                         s = &dev->subdevices[subdev++];
 645                         ret = subdev_8255_io_init(dev, s,
 646                                                   d->addr + j * I8255_SIZE);
 647                         if (ret)
 648                                 return ret;
 649                 }
 650         }
 651
 652         if (board->id_reg) {
 653                 s = &dev->subdevices[subdev++];
 654                 s->type         = COMEDI_SUBD_DI;
 655                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
 656                 s->n_chan       = 4;
 657                 s->maxdata      = 1;
 658                 s->range_table  = &range_digital;
 659                 s->insn_bits    = board->is_16bit ? pci_dio_insn_bits_di_w
 660                                                   : pci_dio_insn_bits_di_b;
 661                 s->private      = (void *)board->id_reg;
 662         }
 663
 664         if (board->timer_regbase) {
 665                 s = &dev->subdevices[subdev++];
 666
 667                 dev->pacer =
 668                     comedi_8254_io_alloc(dev->iobase + board->timer_regbase,
 669                                          0, I8254_IO8, 0);
 670                 if (IS_ERR(dev->pacer))
 671                         return PTR_ERR(dev->pacer);
 672
 673                 comedi_8254_subdevice_init(s, dev->pacer);
 674         }
 675
 676         dev_private->irq_subd = subdev; /* first interrupt subdevice index */
 677         for (i = 0; i < PCI_DIO_MAX_IRQ_SUBDEVS; ++i) {
 678                 struct pci_dio_sd_private_data *sd_priv = NULL;
 679                 const struct dio_irq_subd_data *d = &board->sdirq[i];
 680
 681                 if (d->int_en) {
 682                         s = &dev->subdevices[subdev++];
 683                         s->type         = COMEDI_SUBD_DI;
 684                         s->subdev_flags = SDF_READABLE;
 685                         s->n_chan       = 1;
 686                         s->maxdata      = 1;
 687                         s->range_table  = &range_digital;
 688                         s->insn_bits    = pci_dio_insn_bits_dirq_b;
 689                         sd_priv = comedi_alloc_spriv(s, sizeof(*sd_priv));
 690                         if (!sd_priv)
 691                                 return -ENOMEM;
 692
 693                         spin_lock_init(&sd_priv->subd_slock);
 694                         sd_priv->port_offset = d->addr;
 695                         sd_priv->cmd_running = 0;
 696
 697                         if (dev->irq) {
 698                                 dev->read_subdev = s;
 699                                 s->type         = COMEDI_SUBD_DI;
 700                                 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
 701                                 s->len_chanlist = 1;
 702                                 s->do_cmdtest   = pci_dio_asy_cmdtest;
 703                                 s->do_cmd       = pci_dio_asy_cmd;
 704                                 s->cancel       = pci_dio_asy_cancel;
 705                         }
 706                 }
 707         }
 708
 709         return 0;
 710 }
 711
 712 static void pci_dio_detach(struct comedi_device *dev)
 713 {
 714         struct pci_dio_dev_private_data *dev_private = dev->private;
 715         int boardtype = dev_private->boardtype;
 716
 717         if (dev->iobase)
 718                 pci_dio_reset(dev, boardtype);
 719         comedi_pci_detach(dev);
 720 }
 721
 722 static struct comedi_driver adv_pci_dio_driver = {
 723         .driver_name    = "adv_pci_dio",
 724         .module         = THIS_MODULE,
 725         .auto_attach    = pci_dio_auto_attach,
 726         .detach         = pci_dio_detach,
 727 };
 728
 729 static unsigned long pci_dio_override_cardtype(struct pci_dev *pcidev,
 730                                                unsigned long cardtype)
 731 {
 732         /*
 733          * Change cardtype from TYPE_PCI1753 to TYPE_PCI1753E if expansion
 734          * board available.  Need to enable PCI device and request the main
 735          * registers PCI BAR temporarily to perform the test.
 736          */
 737         if (cardtype != TYPE_PCI1753)
 738                 return cardtype;
 739         if (pci_enable_device(pcidev) < 0)
 740                 return cardtype;
 741         if (pci_request_region(pcidev, 2, "adv_pci_dio") == 0) {
 742                 /*
 743                  * This test is based on Advantech's "advdaq" driver source
 744                  * (which declares its module licence as "GPL" although the
 745                  * driver source does not include a "COPYING" file).
 746                  */
 747                 unsigned long reg = pci_resource_start(pcidev, 2) + 53;
 748
 749                 outb(0x05, reg);
 750                 if ((inb(reg) & 0x07) == 0x02) {
 751                         outb(0x02, reg);
 752                         if ((inb(reg) & 0x07) == 0x05)
 753                                 cardtype = TYPE_PCI1753E;
 754                 }
 755                 pci_release_region(pcidev, 2);
 756         }
 757         pci_disable_device(pcidev);
 758         return cardtype;
 759 }
 760
 761 static int adv_pci_dio_pci_probe(struct pci_dev *dev,
 762                                  const struct pci_device_id *id)
 763 {
 764         unsigned long cardtype;
 765
 766         cardtype = pci_dio_override_cardtype(dev, id->driver_data);
 767         return comedi_pci_auto_config(dev, &adv_pci_dio_driver, cardtype);
 768 }
 769
 770 static const struct pci_device_id adv_pci_dio_pci_table[] = {
 771         { PCI_VDEVICE(ADVANTECH, 0x1730), TYPE_PCI1730 },
 772         { PCI_VDEVICE(ADVANTECH, 0x1733), TYPE_PCI1733 },
 773         { PCI_VDEVICE(ADVANTECH, 0x1734), TYPE_PCI1734 },
 774         { PCI_VDEVICE(ADVANTECH, 0x1735), TYPE_PCI1735 },
 775         { PCI_VDEVICE(ADVANTECH, 0x1736), TYPE_PCI1736 },
 776         { PCI_VDEVICE(ADVANTECH, 0x1739), TYPE_PCI1739 },
 777         { PCI_VDEVICE(ADVANTECH, 0x1750), TYPE_PCI1750 },
 778         { PCI_VDEVICE(ADVANTECH, 0x1751), TYPE_PCI1751 },
 779         { PCI_VDEVICE(ADVANTECH, 0x1752), TYPE_PCI1752 },
 780         { PCI_VDEVICE(ADVANTECH, 0x1753), TYPE_PCI1753 },
 781         { PCI_VDEVICE(ADVANTECH, 0x1754), TYPE_PCI1754 },
 782         { PCI_VDEVICE(ADVANTECH, 0x1756), TYPE_PCI1756 },
 783         { PCI_VDEVICE(ADVANTECH, 0x1761), TYPE_PCI1761 },
 784         { PCI_VDEVICE(ADVANTECH, 0x1762), TYPE_PCI1762 },
 785         { 0 }
 786 };
 787 MODULE_DEVICE_TABLE(pci, adv_pci_dio_pci_table);
 788
 789 static struct pci_driver adv_pci_dio_pci_driver = {
 790         .name           = "adv_pci_dio",
 791         .id_table       = adv_pci_dio_pci_table,
 792         .probe          = adv_pci_dio_pci_probe,
 793         .remove         = comedi_pci_auto_unconfig,
 794 };
 795 module_comedi_pci_driver(adv_pci_dio_driver, adv_pci_dio_pci_driver);
 796
 797 MODULE_AUTHOR("Comedi https://www.comedi.org");
 798 MODULE_DESCRIPTION("Comedi driver for Advantech Digital I/O Cards");
 799 MODULE_LICENSE("GPL");