2 * Allwinner SoCs hstimer driver.
4 * Copyright (C) 2013 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/clk.h>
14 #include <linux/clockchips.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/irqreturn.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
25 #define TIMER_IRQ_EN_REG 0x00
26 #define TIMER_IRQ_EN(val) BIT(val)
27 #define TIMER_IRQ_ST_REG 0x04
28 #define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
29 #define TIMER_CTL_ENABLE BIT(0)
30 #define TIMER_CTL_RELOAD BIT(1)
31 #define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
32 #define TIMER_CTL_ONESHOT BIT(7)
33 #define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
34 #define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
35 #define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
36 #define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
38 #define TIMER_SYNC_TICKS 3
43 struct notifier_block clk_rate_cb;
47 #define to_sun5i_timer(x) \
48 container_of(x, struct sun5i_timer, clk_rate_cb)
50 struct sun5i_timer_clksrc {
51 struct sun5i_timer timer;
52 struct clocksource clksrc;
55 #define to_sun5i_timer_clksrc(x) \
56 container_of(x, struct sun5i_timer_clksrc, clksrc)
58 struct sun5i_timer_clkevt {
59 struct sun5i_timer timer;
60 struct clock_event_device clkevt;
63 #define to_sun5i_timer_clkevt(x) \
64 container_of(x, struct sun5i_timer_clkevt, clkevt)
67 * When we disable a timer, we need to wait at least for 2 cycles of
68 * the timer source clock. We will use for that the clocksource timer
69 * that is already setup and runs at the same frequency than the other
70 * timers, and we never will be disabled.
72 static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
74 u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));
76 while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
80 static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
82 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
83 writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));
85 sun5i_clkevt_sync(ce);
88 static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)
90 writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));
93 static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic)
95 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
98 val &= ~TIMER_CTL_ONESHOT;
100 val |= TIMER_CTL_ONESHOT;
102 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
103 ce->timer.base + TIMER_CTL_REG(timer));
106 static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
108 struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
110 sun5i_clkevt_time_stop(ce, 0);
114 static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
116 struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
118 sun5i_clkevt_time_stop(ce, 0);
119 sun5i_clkevt_time_start(ce, 0, false);
123 static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
125 struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
127 sun5i_clkevt_time_stop(ce, 0);
128 sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy);
129 sun5i_clkevt_time_start(ce, 0, true);
133 static int sun5i_clkevt_next_event(unsigned long evt,
134 struct clock_event_device *clkevt)
136 struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
138 sun5i_clkevt_time_stop(ce, 0);
139 sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
140 sun5i_clkevt_time_start(ce, 0, false);
145 static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
147 struct sun5i_timer_clkevt *ce = (struct sun5i_timer_clkevt *)dev_id;
149 writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG);
150 ce->clkevt.event_handler(&ce->clkevt);
155 static cycle_t sun5i_clksrc_read(struct clocksource *clksrc)
157 struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
159 return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
162 static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
163 unsigned long event, void *data)
165 struct clk_notifier_data *ndata = data;
166 struct sun5i_timer *timer = to_sun5i_timer(nb);
167 struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer);
170 case PRE_RATE_CHANGE:
171 clocksource_unregister(&cs->clksrc);
174 case POST_RATE_CHANGE:
175 clocksource_register_hz(&cs->clksrc, ndata->new_rate);
185 static int __init sun5i_setup_clocksource(struct device_node *node,
187 struct clk *clk, int irq)
189 struct sun5i_timer_clksrc *cs;
193 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
197 ret = clk_prepare_enable(clk);
199 pr_err("Couldn't enable parent clock\n");
203 rate = clk_get_rate(clk);
205 pr_err("Couldn't get parent clock rate\n");
207 goto err_disable_clk;
210 cs->timer.base = base;
212 cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc;
213 cs->timer.clk_rate_cb.next = NULL;
215 ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb);
217 pr_err("Unable to register clock notifier.\n");
218 goto err_disable_clk;
221 writel(~0, base + TIMER_INTVAL_LO_REG(1));
222 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
223 base + TIMER_CTL_REG(1));
225 cs->clksrc.name = node->name;
226 cs->clksrc.rating = 340;
227 cs->clksrc.read = sun5i_clksrc_read;
228 cs->clksrc.mask = CLOCKSOURCE_MASK(32);
229 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
231 ret = clocksource_register_hz(&cs->clksrc, rate);
233 pr_err("Couldn't register clock source.\n");
234 goto err_remove_notifier;
240 clk_notifier_unregister(clk, &cs->timer.clk_rate_cb);
242 clk_disable_unprepare(clk);
248 static int sun5i_rate_cb_clkevt(struct notifier_block *nb,
249 unsigned long event, void *data)
251 struct clk_notifier_data *ndata = data;
252 struct sun5i_timer *timer = to_sun5i_timer(nb);
253 struct sun5i_timer_clkevt *ce = container_of(timer, struct sun5i_timer_clkevt, timer);
255 if (event == POST_RATE_CHANGE) {
256 clockevents_update_freq(&ce->clkevt, ndata->new_rate);
257 ce->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
263 static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base,
264 struct clk *clk, int irq)
266 struct sun5i_timer_clkevt *ce;
271 ce = kzalloc(sizeof(*ce), GFP_KERNEL);
275 ret = clk_prepare_enable(clk);
277 pr_err("Couldn't enable parent clock\n");
281 rate = clk_get_rate(clk);
283 pr_err("Couldn't get parent clock rate\n");
285 goto err_disable_clk;
288 ce->timer.base = base;
289 ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
291 ce->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clkevt;
292 ce->timer.clk_rate_cb.next = NULL;
294 ret = clk_notifier_register(clk, &ce->timer.clk_rate_cb);
296 pr_err("Unable to register clock notifier.\n");
297 goto err_disable_clk;
300 ce->clkevt.name = node->name;
301 ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
302 ce->clkevt.set_next_event = sun5i_clkevt_next_event;
303 ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;
304 ce->clkevt.set_state_periodic = sun5i_clkevt_set_periodic;
305 ce->clkevt.set_state_oneshot = sun5i_clkevt_set_oneshot;
306 ce->clkevt.tick_resume = sun5i_clkevt_shutdown;
307 ce->clkevt.rating = 340;
308 ce->clkevt.irq = irq;
309 ce->clkevt.cpumask = cpu_possible_mask;
311 /* Enable timer0 interrupt */
312 val = readl(base + TIMER_IRQ_EN_REG);
313 writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG);
315 clockevents_config_and_register(&ce->clkevt, rate,
316 TIMER_SYNC_TICKS, 0xffffffff);
318 ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
321 pr_err("Unable to register interrupt\n");
322 goto err_remove_notifier;
328 clk_notifier_unregister(clk, &ce->timer.clk_rate_cb);
330 clk_disable_unprepare(clk);
336 static int __init sun5i_timer_init(struct device_node *node)
338 struct reset_control *rstc;
339 void __iomem *timer_base;
343 timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
344 if (IS_ERR(timer_base)) {
345 pr_err("Can't map registers");
346 return PTR_ERR(timer_base);;
349 irq = irq_of_parse_and_map(node, 0);
351 pr_err("Can't parse IRQ");
355 clk = of_clk_get(node, 0);
357 pr_err("Can't get timer clock");
361 rstc = of_reset_control_get(node, NULL);
363 reset_control_deassert(rstc);
365 ret = sun5i_setup_clocksource(node, timer_base, clk, irq);
369 return sun5i_setup_clockevent(node, timer_base, clk, irq);
371 CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
373 CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",