drivers/clocksource/timer-imx-tpm.c

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  * Copyright 2017 NXP
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/clockchips.h>
  13 #include <linux/clocksource.h>
  14 #include <linux/delay.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/sched_clock.h>
  19
  20 #define TPM_SC                          0x10
  21 #define TPM_SC_CMOD_INC_PER_CNT         (0x1 << 3)
  22 #define TPM_SC_CMOD_DIV_DEFAULT         0x3
  23 #define TPM_SC_TOF_MASK                 (0x1 << 7)
  24 #define TPM_CNT                         0x14
  25 #define TPM_MOD                         0x18
  26 #define TPM_STATUS                      0x1c
  27 #define TPM_STATUS_CH0F                 BIT(0)
  28 #define TPM_C0SC                        0x20
  29 #define TPM_C0SC_CHIE                   BIT(6)
  30 #define TPM_C0SC_MODE_SHIFT             2
  31 #define TPM_C0SC_MODE_MASK              0x3c
  32 #define TPM_C0SC_MODE_SW_COMPARE        0x4
  33 #define TPM_C0SC_CHF_MASK               (0x1 << 7)
  34 #define TPM_C0V                         0x24
  35
  36 static void __iomem *timer_base;
  37 static struct clock_event_device clockevent_tpm;
  38
  39 static inline void tpm_timer_disable(void)
  40 {
  41         unsigned int val;
  42
  43         /* channel disable */
  44         val = readl(timer_base + TPM_C0SC);
  45         val &= ~(TPM_C0SC_MODE_MASK | TPM_C0SC_CHIE);
  46         writel(val, timer_base + TPM_C0SC);
  47 }
  48
  49 static inline void tpm_timer_enable(void)
  50 {
  51         unsigned int val;
  52
  53         /* channel enabled in sw compare mode */
  54         val = readl(timer_base + TPM_C0SC);
  55         val |= (TPM_C0SC_MODE_SW_COMPARE << TPM_C0SC_MODE_SHIFT) |
  56                TPM_C0SC_CHIE;
  57         writel(val, timer_base + TPM_C0SC);
  58 }
  59
  60 static inline void tpm_irq_acknowledge(void)
  61 {
  62         writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS);
  63 }
  64
  65 static struct delay_timer tpm_delay_timer;
  66
  67 static inline unsigned long tpm_read_counter(void)
  68 {
  69         return readl(timer_base + TPM_CNT);
  70 }
  71
  72 static unsigned long tpm_read_current_timer(void)
  73 {
  74         return tpm_read_counter();
  75 }
  76
  77 static u64 notrace tpm_read_sched_clock(void)
  78 {
  79         return tpm_read_counter();
  80 }
  81
  82 static int __init tpm_clocksource_init(unsigned long rate)
  83 {
  84         tpm_delay_timer.read_current_timer = &tpm_read_current_timer;
  85         tpm_delay_timer.freq = rate;
  86         register_current_timer_delay(&tpm_delay_timer);
  87
  88         sched_clock_register(tpm_read_sched_clock, 32, rate);
  89
  90         return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm",
  91                                      rate, 200, 32, clocksource_mmio_readl_up);
  92 }
  93
  94 static int tpm_set_next_event(unsigned long delta,
  95                                 struct clock_event_device *evt)
  96 {
  97         unsigned long next, now;
  98
  99         next = tpm_read_counter();
 100         next += delta;
 101         writel(next, timer_base + TPM_C0V);
 102         now = tpm_read_counter();
 103
 104         /*
 105          * NOTE: We observed in a very small probability, the bus fabric
 106          * contention between GPU and A7 may results a few cycles delay
 107          * of writing CNT registers which may cause the min_delta event got
 108          * missed, so we need add a ETIME check here in case it happened.
 109          */
 110         return (int)(next - now) <= 0 ? -ETIME : 0;
 111 }
 112
 113 static int tpm_set_state_oneshot(struct clock_event_device *evt)
 114 {
 115         tpm_timer_enable();
 116
 117         return 0;
 118 }
 119
 120 static int tpm_set_state_shutdown(struct clock_event_device *evt)
 121 {
 122         tpm_timer_disable();
 123
 124         return 0;
 125 }
 126
 127 static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id)
 128 {
 129         struct clock_event_device *evt = dev_id;
 130
 131         tpm_irq_acknowledge();
 132
 133         evt->event_handler(evt);
 134
 135         return IRQ_HANDLED;
 136 }
 137
 138 static struct clock_event_device clockevent_tpm = {
 139         .name                   = "i.MX7ULP TPM Timer",
 140         .features               = CLOCK_EVT_FEAT_ONESHOT,
 141         .set_state_oneshot      = tpm_set_state_oneshot,
 142         .set_next_event         = tpm_set_next_event,
 143         .set_state_shutdown     = tpm_set_state_shutdown,
 144         .rating                 = 200,
 145 };
 146
 147 static int __init tpm_clockevent_init(unsigned long rate, int irq)
 148 {
 149         int ret;
 150
 151         ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
 152                           "i.MX7ULP TPM Timer", &clockevent_tpm);
 153
 154         clockevent_tpm.cpumask = cpumask_of(0);
 155         clockevent_tpm.irq = irq;
 156         clockevents_config_and_register(&clockevent_tpm,
 157                                         rate, 300, 0xfffffffe);
 158
 159         return ret;
 160 }
 161
 162 static int __init tpm_timer_init(struct device_node *np)
 163 {
 164         struct clk *ipg, *per;
 165         int irq, ret;
 166         u32 rate;
 167
 168         timer_base = of_iomap(np, 0);
 169         if (!timer_base) {
 170                 pr_err("tpm: failed to get base address\n");
 171                 return -ENXIO;
 172         }
 173
 174         irq = irq_of_parse_and_map(np, 0);
 175         if (!irq) {
 176                 pr_err("tpm: failed to get irq\n");
 177                 ret = -ENOENT;
 178                 goto err_iomap;
 179         }
 180
 181         ipg = of_clk_get_by_name(np, "ipg");
 182         per = of_clk_get_by_name(np, "per");
 183         if (IS_ERR(ipg) || IS_ERR(per)) {
 184                 pr_err("tpm: failed to get igp or per clk\n");
 185                 ret = -ENODEV;
 186                 goto err_clk_get;
 187         }
 188
 189         /* enable clk before accessing registers */
 190         ret = clk_prepare_enable(ipg);
 191         if (ret) {
 192                 pr_err("tpm: ipg clock enable failed (%d)\n", ret);
 193                 goto err_clk_get;
 194         }
 195
 196         ret = clk_prepare_enable(per);
 197         if (ret) {
 198                 pr_err("tpm: per clock enable failed (%d)\n", ret);
 199                 goto err_per_clk_enable;
 200         }
 201
 202         /*
 203          * Initialize tpm module to a known state
 204          * 1) Counter disabled
 205          * 2) TPM counter operates in up counting mode
 206          * 3) Timer Overflow Interrupt disabled
 207          * 4) Channel0 disabled
 208          * 5) DMA transfers disabled
 209          */
 210         /* make sure counter is disabled */
 211         writel(0, timer_base + TPM_SC);
 212         /* TOF is W1C */
 213         writel(TPM_SC_TOF_MASK, timer_base + TPM_SC);
 214         writel(0, timer_base + TPM_CNT);
 215         /* CHF is W1C */
 216         writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);
 217
 218         /* increase per cnt, div 8 by default */
 219         writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,
 220                      timer_base + TPM_SC);
 221
 222         /* set MOD register to maximum for free running mode */
 223         writel(0xffffffff, timer_base + TPM_MOD);
 224
 225         rate = clk_get_rate(per) >> 3;
 226         ret = tpm_clocksource_init(rate);
 227         if (ret)
 228                 goto err_per_clk_enable;
 229
 230         ret = tpm_clockevent_init(rate, irq);
 231         if (ret)
 232                 goto err_per_clk_enable;
 233
 234         return 0;
 235
 236 err_per_clk_enable:
 237         clk_disable_unprepare(ipg);
 238 err_clk_get:
 239         clk_put(per);
 240         clk_put(ipg);
 241 err_iomap:
 242         iounmap(timer_base);
 243         return ret;
 244 }
 245 TIMER_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);