1 // SPDX-License-Identifier: GPL-2.0-only
3 * This file contains driver for the Cadence Triple Timer Counter Rev 06
5 * Copyright (C) 2011-2013 Xilinx
7 * based on arch/mips/kernel/time.c timer driver
10 #include <linux/clk.h>
11 #include <linux/interrupt.h>
12 #include <linux/clockchips.h>
13 #include <linux/clocksource.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/slab.h>
17 #include <linux/sched_clock.h>
20 * This driver configures the 2 16/32-bit count-up timers as follows:
22 * T1: Timer 1, clocksource for generic timekeeping
23 * T2: Timer 2, clockevent source for hrtimers
24 * T3: Timer 3, <unused>
26 * The input frequency to the timer module for emulation is 2.5MHz which is
27 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
28 * the timers are clocked at 78.125KHz (12.8 us resolution).
30 * The input frequency to the timer module in silicon is configurable and
31 * obtained from device tree. The pre-scaler of 32 is used.
35 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
36 * and use same offsets for Timer 2
38 #define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
39 #define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
40 #define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
41 #define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
42 #define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
43 #define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
45 #define TTC_CNT_CNTRL_DISABLE_MASK 0x1
47 #define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
48 #define TTC_CLK_CNTRL_PSV_MASK 0x1e
49 #define TTC_CLK_CNTRL_PSV_SHIFT 1
52 * Setup the timers to use pre-scaling, using a fixed value for now that will
53 * work across most input frequency, but it may need to be more dynamic
55 #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
56 #define PRESCALE 2048 /* The exponent must match this */
57 #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
58 #define CLK_CNTRL_PRESCALE_EN 1
59 #define CNT_CNTRL_RESET (1 << 4)
64 * struct ttc_timer - This definition defines local timer structure
66 * @base_addr: Base address of timer
67 * @freq: Timer input clock frequency
68 * @clk: Associated clock source
69 * @clk_rate_change_nb Notifier block for clock rate changes
72 void __iomem *base_addr;
75 struct notifier_block clk_rate_change_nb;
78 #define to_ttc_timer(x) \
79 container_of(x, struct ttc_timer, clk_rate_change_nb)
81 struct ttc_timer_clocksource {
82 u32 scale_clk_ctrl_reg_old;
83 u32 scale_clk_ctrl_reg_new;
85 struct clocksource cs;
88 #define to_ttc_timer_clksrc(x) \
89 container_of(x, struct ttc_timer_clocksource, cs)
91 struct ttc_timer_clockevent {
93 struct clock_event_device ce;
96 #define to_ttc_timer_clkevent(x) \
97 container_of(x, struct ttc_timer_clockevent, ce)
99 static void __iomem *ttc_sched_clock_val_reg;
102 * ttc_set_interval - Set the timer interval value
104 * @timer: Pointer to the timer instance
105 * @cycles: Timer interval ticks
107 static void ttc_set_interval(struct ttc_timer *timer,
108 unsigned long cycles)
112 /* Disable the counter, set the counter value and re-enable counter */
113 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
114 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
115 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
117 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
120 * Reset the counter (0x10) so that it starts from 0, one-shot
121 * mode makes this needed for timing to be right.
123 ctrl_reg |= CNT_CNTRL_RESET;
124 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
125 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
129 * ttc_clock_event_interrupt - Clock event timer interrupt handler
131 * @irq: IRQ number of the Timer
132 * @dev_id: void pointer to the ttc_timer instance
134 * returns: Always IRQ_HANDLED - success
136 static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
138 struct ttc_timer_clockevent *ttce = dev_id;
139 struct ttc_timer *timer = &ttce->ttc;
141 /* Acknowledge the interrupt and call event handler */
142 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
144 ttce->ce.event_handler(&ttce->ce);
150 * __ttc_clocksource_read - Reads the timer counter register
152 * returns: Current timer counter register value
154 static u64 __ttc_clocksource_read(struct clocksource *cs)
156 struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
158 return (u64)readl_relaxed(timer->base_addr +
159 TTC_COUNT_VAL_OFFSET);
162 static u64 notrace ttc_sched_clock_read(void)
164 return readl_relaxed(ttc_sched_clock_val_reg);
168 * ttc_set_next_event - Sets the time interval for next event
170 * @cycles: Timer interval ticks
171 * @evt: Address of clock event instance
173 * returns: Always 0 - success
175 static int ttc_set_next_event(unsigned long cycles,
176 struct clock_event_device *evt)
178 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
179 struct ttc_timer *timer = &ttce->ttc;
181 ttc_set_interval(timer, cycles);
186 * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
188 * @evt: Address of clock event instance
190 static int ttc_shutdown(struct clock_event_device *evt)
192 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
193 struct ttc_timer *timer = &ttce->ttc;
196 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
197 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
198 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
202 static int ttc_set_periodic(struct clock_event_device *evt)
204 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
205 struct ttc_timer *timer = &ttce->ttc;
207 ttc_set_interval(timer,
208 DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
212 static int ttc_resume(struct clock_event_device *evt)
214 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
215 struct ttc_timer *timer = &ttce->ttc;
218 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
219 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
220 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
224 static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
225 unsigned long event, void *data)
227 struct clk_notifier_data *ndata = data;
228 struct ttc_timer *ttc = to_ttc_timer(nb);
229 struct ttc_timer_clocksource *ttccs = container_of(ttc,
230 struct ttc_timer_clocksource, ttc);
233 case PRE_RATE_CHANGE:
236 unsigned long factor, rate_low, rate_high;
238 if (ndata->new_rate > ndata->old_rate) {
239 factor = DIV_ROUND_CLOSEST(ndata->new_rate,
241 rate_low = ndata->old_rate;
242 rate_high = ndata->new_rate;
244 factor = DIV_ROUND_CLOSEST(ndata->old_rate,
246 rate_low = ndata->new_rate;
247 rate_high = ndata->old_rate;
250 if (!is_power_of_2(factor))
253 if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
256 factor = __ilog2_u32(factor);
259 * store timer clock ctrl register so we can restore it in case
262 ttccs->scale_clk_ctrl_reg_old =
263 readl_relaxed(ttccs->ttc.base_addr +
264 TTC_CLK_CNTRL_OFFSET);
266 psv = (ttccs->scale_clk_ctrl_reg_old &
267 TTC_CLK_CNTRL_PSV_MASK) >>
268 TTC_CLK_CNTRL_PSV_SHIFT;
269 if (ndata->new_rate < ndata->old_rate)
274 /* prescaler within legal range? */
275 if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
278 ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
279 ~TTC_CLK_CNTRL_PSV_MASK;
280 ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
283 /* scale down: adjust divider in post-change notification */
284 if (ndata->new_rate < ndata->old_rate)
287 /* scale up: adjust divider now - before frequency change */
288 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
289 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
292 case POST_RATE_CHANGE:
293 /* scale up: pre-change notification did the adjustment */
294 if (ndata->new_rate > ndata->old_rate)
297 /* scale down: adjust divider now - after frequency change */
298 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
299 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
302 case ABORT_RATE_CHANGE:
303 /* we have to undo the adjustment in case we scale up */
304 if (ndata->new_rate < ndata->old_rate)
307 /* restore original register value */
308 writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
309 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
318 static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
321 struct ttc_timer_clocksource *ttccs;
324 ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
328 ttccs->ttc.clk = clk;
330 err = clk_prepare_enable(ttccs->ttc.clk);
336 ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
338 ttccs->ttc.clk_rate_change_nb.notifier_call =
339 ttc_rate_change_clocksource_cb;
340 ttccs->ttc.clk_rate_change_nb.next = NULL;
342 err = clk_notifier_register(ttccs->ttc.clk,
343 &ttccs->ttc.clk_rate_change_nb);
345 pr_warn("Unable to register clock notifier.\n");
347 ttccs->ttc.base_addr = base;
348 ttccs->cs.name = "ttc_clocksource";
349 ttccs->cs.rating = 200;
350 ttccs->cs.read = __ttc_clocksource_read;
351 ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
352 ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
355 * Setup the clock source counter to be an incrementing counter
356 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
357 * it by 32 also. Let it start running now.
359 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
360 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
361 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
362 writel_relaxed(CNT_CNTRL_RESET,
363 ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
365 err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
371 ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
372 sched_clock_register(ttc_sched_clock_read, timer_width,
373 ttccs->ttc.freq / PRESCALE);
378 static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
379 unsigned long event, void *data)
381 struct clk_notifier_data *ndata = data;
382 struct ttc_timer *ttc = to_ttc_timer(nb);
383 struct ttc_timer_clockevent *ttcce = container_of(ttc,
384 struct ttc_timer_clockevent, ttc);
387 case POST_RATE_CHANGE:
388 /* update cached frequency */
389 ttc->freq = ndata->new_rate;
391 clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
394 case PRE_RATE_CHANGE:
395 case ABORT_RATE_CHANGE:
401 static int __init ttc_setup_clockevent(struct clk *clk,
402 void __iomem *base, u32 irq)
404 struct ttc_timer_clockevent *ttcce;
407 ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
411 ttcce->ttc.clk = clk;
413 err = clk_prepare_enable(ttcce->ttc.clk);
417 ttcce->ttc.clk_rate_change_nb.notifier_call =
418 ttc_rate_change_clockevent_cb;
419 ttcce->ttc.clk_rate_change_nb.next = NULL;
421 err = clk_notifier_register(ttcce->ttc.clk,
422 &ttcce->ttc.clk_rate_change_nb);
424 pr_warn("Unable to register clock notifier.\n");
428 ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
430 ttcce->ttc.base_addr = base;
431 ttcce->ce.name = "ttc_clockevent";
432 ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
433 ttcce->ce.set_next_event = ttc_set_next_event;
434 ttcce->ce.set_state_shutdown = ttc_shutdown;
435 ttcce->ce.set_state_periodic = ttc_set_periodic;
436 ttcce->ce.set_state_oneshot = ttc_shutdown;
437 ttcce->ce.tick_resume = ttc_resume;
438 ttcce->ce.rating = 200;
440 ttcce->ce.cpumask = cpu_possible_mask;
443 * Setup the clock event timer to be an interval timer which
444 * is prescaled by 32 using the interval interrupt. Leave it
447 writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
448 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
449 ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
450 writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
452 err = request_irq(irq, ttc_clock_event_interrupt,
453 IRQF_TIMER, ttcce->ce.name, ttcce);
457 clockevents_config_and_register(&ttcce->ce,
458 ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
468 * ttc_timer_init - Initialize the timer
470 * Initializes the timer hardware and register the clock source and clock event
471 * timers with Linux kernal timer framework
473 static int __init ttc_timer_init(struct device_node *timer)
476 void __iomem *timer_baseaddr;
477 struct clk *clk_cs, *clk_ce;
478 static int initialized;
480 u32 timer_width = 16;
488 * Get the 1st Triple Timer Counter (TTC) block from the device tree
489 * and use it. Note that the event timer uses the interrupt and it's the
490 * 2nd TTC hence the irq_of_parse_and_map(,1)
492 timer_baseaddr = of_iomap(timer, 0);
493 if (!timer_baseaddr) {
494 pr_err("ERROR: invalid timer base address\n");
498 irq = irq_of_parse_and_map(timer, 1);
500 pr_err("ERROR: invalid interrupt number\n");
504 of_property_read_u32(timer, "timer-width", &timer_width);
506 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
507 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
508 clk_cs = of_clk_get(timer, clksel);
509 if (IS_ERR(clk_cs)) {
510 pr_err("ERROR: timer input clock not found\n");
511 return PTR_ERR(clk_cs);
514 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
515 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
516 clk_ce = of_clk_get(timer, clksel);
517 if (IS_ERR(clk_ce)) {
518 pr_err("ERROR: timer input clock not found\n");
519 return PTR_ERR(clk_ce);
522 ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
526 ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
530 pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);
535 TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);