drivers/clocksource/sh_cmt.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SuperH Timer Support - CMT
   4  *
   5  *  Copyright (C) 2008 Magnus Damm
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/clockchips.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/ioport.h>
  17 #include <linux/irq.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_domain.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/sh_timer.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27
  28 struct sh_cmt_device;
  29
  30 /*
  31  * The CMT comes in 5 different identified flavours, depending not only on the
  32  * SoC but also on the particular instance. The following table lists the main
  33  * characteristics of those flavours.
  34  *
  35  *                      16B     32B     32B-F   48B     R-Car Gen2
  36  * -----------------------------------------------------------------------------
  37  * Channels             2       1/4     1       6       2/8
  38  * Control Width        16      16      16      16      32
  39  * Counter Width        16      32      32      32/48   32/48
  40  * Shared Start/Stop    Y       Y       Y       Y       N
  41  *
  42  * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
  43  * located in the channel registers block. All other versions have a shared
  44  * start/stop register located in the global space.
  45  *
  46  * Channels are indexed from 0 to N-1 in the documentation. The channel index
  47  * infers the start/stop bit position in the control register and the channel
  48  * registers block address. Some CMT instances have a subset of channels
  49  * available, in which case the index in the documentation doesn't match the
  50  * "real" index as implemented in hardware. This is for instance the case with
  51  * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
  52  * in the documentation but using start/stop bit 5 and having its registers
  53  * block at 0x60.
  54  *
  55  * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
  56  * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
  57  */
  58
  59 enum sh_cmt_model {
  60         SH_CMT_16BIT,
  61         SH_CMT_32BIT,
  62         SH_CMT_48BIT,
  63         SH_CMT0_RCAR_GEN2,
  64         SH_CMT1_RCAR_GEN2,
  65 };
  66
  67 struct sh_cmt_info {
  68         enum sh_cmt_model model;
  69
  70         unsigned int channels_mask;
  71
  72         unsigned long width; /* 16 or 32 bit version of hardware block */
  73         u32 overflow_bit;
  74         u32 clear_bits;
  75
  76         /* callbacks for CMSTR and CMCSR access */
  77         u32 (*read_control)(void __iomem *base, unsigned long offs);
  78         void (*write_control)(void __iomem *base, unsigned long offs,
  79                               u32 value);
  80
  81         /* callbacks for CMCNT and CMCOR access */
  82         u32 (*read_count)(void __iomem *base, unsigned long offs);
  83         void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
  84 };
  85
  86 struct sh_cmt_channel {
  87         struct sh_cmt_device *cmt;
  88
  89         unsigned int index;     /* Index in the documentation */
  90         unsigned int hwidx;     /* Real hardware index */
  91
  92         void __iomem *iostart;
  93         void __iomem *ioctrl;
  94
  95         unsigned int timer_bit;
  96         unsigned long flags;
  97         u32 match_value;
  98         u32 next_match_value;
  99         u32 max_match_value;
 100         raw_spinlock_t lock;
 101         struct clock_event_device ced;
 102         struct clocksource cs;
 103         u64 total_cycles;
 104         bool cs_enabled;
 105 };
 106
 107 struct sh_cmt_device {
 108         struct platform_device *pdev;
 109
 110         const struct sh_cmt_info *info;
 111
 112         void __iomem *mapbase;
 113         struct clk *clk;
 114         unsigned long rate;
 115
 116         raw_spinlock_t lock; /* Protect the shared start/stop register */
 117
 118         struct sh_cmt_channel *channels;
 119         unsigned int num_channels;
 120         unsigned int hw_channels;
 121
 122         bool has_clockevent;
 123         bool has_clocksource;
 124 };
 125
 126 #define SH_CMT16_CMCSR_CMF              (1 << 7)
 127 #define SH_CMT16_CMCSR_CMIE             (1 << 6)
 128 #define SH_CMT16_CMCSR_CKS8             (0 << 0)
 129 #define SH_CMT16_CMCSR_CKS32            (1 << 0)
 130 #define SH_CMT16_CMCSR_CKS128           (2 << 0)
 131 #define SH_CMT16_CMCSR_CKS512           (3 << 0)
 132 #define SH_CMT16_CMCSR_CKS_MASK         (3 << 0)
 133
 134 #define SH_CMT32_CMCSR_CMF              (1 << 15)
 135 #define SH_CMT32_CMCSR_OVF              (1 << 14)
 136 #define SH_CMT32_CMCSR_WRFLG            (1 << 13)
 137 #define SH_CMT32_CMCSR_STTF             (1 << 12)
 138 #define SH_CMT32_CMCSR_STPF             (1 << 11)
 139 #define SH_CMT32_CMCSR_SSIE             (1 << 10)
 140 #define SH_CMT32_CMCSR_CMS              (1 << 9)
 141 #define SH_CMT32_CMCSR_CMM              (1 << 8)
 142 #define SH_CMT32_CMCSR_CMTOUT_IE        (1 << 7)
 143 #define SH_CMT32_CMCSR_CMR_NONE         (0 << 4)
 144 #define SH_CMT32_CMCSR_CMR_DMA          (1 << 4)
 145 #define SH_CMT32_CMCSR_CMR_IRQ          (2 << 4)
 146 #define SH_CMT32_CMCSR_CMR_MASK         (3 << 4)
 147 #define SH_CMT32_CMCSR_DBGIVD           (1 << 3)
 148 #define SH_CMT32_CMCSR_CKS_RCLK8        (4 << 0)
 149 #define SH_CMT32_CMCSR_CKS_RCLK32       (5 << 0)
 150 #define SH_CMT32_CMCSR_CKS_RCLK128      (6 << 0)
 151 #define SH_CMT32_CMCSR_CKS_RCLK1        (7 << 0)
 152 #define SH_CMT32_CMCSR_CKS_MASK         (7 << 0)
 153
 154 static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
 155 {
 156         return ioread16(base + (offs << 1));
 157 }
 158
 159 static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
 160 {
 161         return ioread32(base + (offs << 2));
 162 }
 163
 164 static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
 165 {
 166         iowrite16(value, base + (offs << 1));
 167 }
 168
 169 static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
 170 {
 171         iowrite32(value, base + (offs << 2));
 172 }
 173
 174 static const struct sh_cmt_info sh_cmt_info[] = {
 175         [SH_CMT_16BIT] = {
 176                 .model = SH_CMT_16BIT,
 177                 .width = 16,
 178                 .overflow_bit = SH_CMT16_CMCSR_CMF,
 179                 .clear_bits = ~SH_CMT16_CMCSR_CMF,
 180                 .read_control = sh_cmt_read16,
 181                 .write_control = sh_cmt_write16,
 182                 .read_count = sh_cmt_read16,
 183                 .write_count = sh_cmt_write16,
 184         },
 185         [SH_CMT_32BIT] = {
 186                 .model = SH_CMT_32BIT,
 187                 .width = 32,
 188                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 189                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 190                 .read_control = sh_cmt_read16,
 191                 .write_control = sh_cmt_write16,
 192                 .read_count = sh_cmt_read32,
 193                 .write_count = sh_cmt_write32,
 194         },
 195         [SH_CMT_48BIT] = {
 196                 .model = SH_CMT_48BIT,
 197                 .channels_mask = 0x3f,
 198                 .width = 32,
 199                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 200                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 201                 .read_control = sh_cmt_read32,
 202                 .write_control = sh_cmt_write32,
 203                 .read_count = sh_cmt_read32,
 204                 .write_count = sh_cmt_write32,
 205         },
 206         [SH_CMT0_RCAR_GEN2] = {
 207                 .model = SH_CMT0_RCAR_GEN2,
 208                 .channels_mask = 0x60,
 209                 .width = 32,
 210                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 211                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 212                 .read_control = sh_cmt_read32,
 213                 .write_control = sh_cmt_write32,
 214                 .read_count = sh_cmt_read32,
 215                 .write_count = sh_cmt_write32,
 216         },
 217         [SH_CMT1_RCAR_GEN2] = {
 218                 .model = SH_CMT1_RCAR_GEN2,
 219                 .channels_mask = 0xff,
 220                 .width = 32,
 221                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 222                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 223                 .read_control = sh_cmt_read32,
 224                 .write_control = sh_cmt_write32,
 225                 .read_count = sh_cmt_read32,
 226                 .write_count = sh_cmt_write32,
 227         },
 228 };
 229
 230 #define CMCSR 0 /* channel register */
 231 #define CMCNT 1 /* channel register */
 232 #define CMCOR 2 /* channel register */
 233
 234 #define CMCLKE  0x1000  /* CLK Enable Register (R-Car Gen2) */
 235
 236 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
 237 {
 238         if (ch->iostart)
 239                 return ch->cmt->info->read_control(ch->iostart, 0);
 240         else
 241                 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
 242 }
 243
 244 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
 245 {
 246         if (ch->iostart)
 247                 ch->cmt->info->write_control(ch->iostart, 0, value);
 248         else
 249                 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
 250 }
 251
 252 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
 253 {
 254         return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
 255 }
 256
 257 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
 258 {
 259         ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
 260 }
 261
 262 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
 263 {
 264         return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
 265 }
 266
 267 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
 268 {
 269         ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
 270 }
 271
 272 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
 273 {
 274         ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
 275 }
 276
 277 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
 278 {
 279         u32 v1, v2, v3;
 280         u32 o1, o2;
 281
 282         o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 283
 284         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
 285         do {
 286                 o2 = o1;
 287                 v1 = sh_cmt_read_cmcnt(ch);
 288                 v2 = sh_cmt_read_cmcnt(ch);
 289                 v3 = sh_cmt_read_cmcnt(ch);
 290                 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 291         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
 292                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 293
 294         *has_wrapped = o1;
 295         return v2;
 296 }
 297
 298 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
 299 {
 300         unsigned long flags;
 301         u32 value;
 302
 303         /* start stop register shared by multiple timer channels */
 304         raw_spin_lock_irqsave(&ch->cmt->lock, flags);
 305         value = sh_cmt_read_cmstr(ch);
 306
 307         if (start)
 308                 value |= 1 << ch->timer_bit;
 309         else
 310                 value &= ~(1 << ch->timer_bit);
 311
 312         sh_cmt_write_cmstr(ch, value);
 313         raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
 314 }
 315
 316 static int sh_cmt_enable(struct sh_cmt_channel *ch)
 317 {
 318         int k, ret;
 319
 320         pm_runtime_get_sync(&ch->cmt->pdev->dev);
 321         dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
 322
 323         /* enable clock */
 324         ret = clk_enable(ch->cmt->clk);
 325         if (ret) {
 326                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
 327                         ch->index);
 328                 goto err0;
 329         }
 330
 331         /* make sure channel is disabled */
 332         sh_cmt_start_stop_ch(ch, 0);
 333
 334         /* configure channel, periodic mode and maximum timeout */
 335         if (ch->cmt->info->width == 16) {
 336                 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
 337                                    SH_CMT16_CMCSR_CKS512);
 338         } else {
 339                 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
 340                                    SH_CMT32_CMCSR_CMTOUT_IE |
 341                                    SH_CMT32_CMCSR_CMR_IRQ |
 342                                    SH_CMT32_CMCSR_CKS_RCLK8);
 343         }
 344
 345         sh_cmt_write_cmcor(ch, 0xffffffff);
 346         sh_cmt_write_cmcnt(ch, 0);
 347
 348         /*
 349          * According to the sh73a0 user's manual, as CMCNT can be operated
 350          * only by the RCLK (Pseudo 32 KHz), there's one restriction on
 351          * modifying CMCNT register; two RCLK cycles are necessary before
 352          * this register is either read or any modification of the value
 353          * it holds is reflected in the LSI's actual operation.
 354          *
 355          * While at it, we're supposed to clear out the CMCNT as of this
 356          * moment, so make sure it's processed properly here.  This will
 357          * take RCLKx2 at maximum.
 358          */
 359         for (k = 0; k < 100; k++) {
 360                 if (!sh_cmt_read_cmcnt(ch))
 361                         break;
 362                 udelay(1);
 363         }
 364
 365         if (sh_cmt_read_cmcnt(ch)) {
 366                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
 367                         ch->index);
 368                 ret = -ETIMEDOUT;
 369                 goto err1;
 370         }
 371
 372         /* enable channel */
 373         sh_cmt_start_stop_ch(ch, 1);
 374         return 0;
 375  err1:
 376         /* stop clock */
 377         clk_disable(ch->cmt->clk);
 378
 379  err0:
 380         return ret;
 381 }
 382
 383 static void sh_cmt_disable(struct sh_cmt_channel *ch)
 384 {
 385         /* disable channel */
 386         sh_cmt_start_stop_ch(ch, 0);
 387
 388         /* disable interrupts in CMT block */
 389         sh_cmt_write_cmcsr(ch, 0);
 390
 391         /* stop clock */
 392         clk_disable(ch->cmt->clk);
 393
 394         dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
 395         pm_runtime_put(&ch->cmt->pdev->dev);
 396 }
 397
 398 /* private flags */
 399 #define FLAG_CLOCKEVENT (1 << 0)
 400 #define FLAG_CLOCKSOURCE (1 << 1)
 401 #define FLAG_REPROGRAM (1 << 2)
 402 #define FLAG_SKIPEVENT (1 << 3)
 403 #define FLAG_IRQCONTEXT (1 << 4)
 404
 405 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
 406                                               int absolute)
 407 {
 408         u32 value = ch->next_match_value;
 409         u32 new_match;
 410         u32 delay = 0;
 411         u32 now = 0;
 412         u32 has_wrapped;
 413
 414         now = sh_cmt_get_counter(ch, &has_wrapped);
 415         ch->flags |= FLAG_REPROGRAM; /* force reprogram */
 416
 417         if (has_wrapped) {
 418                 /* we're competing with the interrupt handler.
 419                  *  -> let the interrupt handler reprogram the timer.
 420                  *  -> interrupt number two handles the event.
 421                  */
 422                 ch->flags |= FLAG_SKIPEVENT;
 423                 return;
 424         }
 425
 426         if (absolute)
 427                 now = 0;
 428
 429         do {
 430                 /* reprogram the timer hardware,
 431                  * but don't save the new match value yet.
 432                  */
 433                 new_match = now + value + delay;
 434                 if (new_match > ch->max_match_value)
 435                         new_match = ch->max_match_value;
 436
 437                 sh_cmt_write_cmcor(ch, new_match);
 438
 439                 now = sh_cmt_get_counter(ch, &has_wrapped);
 440                 if (has_wrapped && (new_match > ch->match_value)) {
 441                         /* we are changing to a greater match value,
 442                          * so this wrap must be caused by the counter
 443                          * matching the old value.
 444                          * -> first interrupt reprograms the timer.
 445                          * -> interrupt number two handles the event.
 446                          */
 447                         ch->flags |= FLAG_SKIPEVENT;
 448                         break;
 449                 }
 450
 451                 if (has_wrapped) {
 452                         /* we are changing to a smaller match value,
 453                          * so the wrap must be caused by the counter
 454                          * matching the new value.
 455                          * -> save programmed match value.
 456                          * -> let isr handle the event.
 457                          */
 458                         ch->match_value = new_match;
 459                         break;
 460                 }
 461
 462                 /* be safe: verify hardware settings */
 463                 if (now < new_match) {
 464                         /* timer value is below match value, all good.
 465                          * this makes sure we won't miss any match events.
 466                          * -> save programmed match value.
 467                          * -> let isr handle the event.
 468                          */
 469                         ch->match_value = new_match;
 470                         break;
 471                 }
 472
 473                 /* the counter has reached a value greater
 474                  * than our new match value. and since the
 475                  * has_wrapped flag isn't set we must have
 476                  * programmed a too close event.
 477                  * -> increase delay and retry.
 478                  */
 479                 if (delay)
 480                         delay <<= 1;
 481                 else
 482                         delay = 1;
 483
 484                 if (!delay)
 485                         dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
 486                                  ch->index);
 487
 488         } while (delay);
 489 }
 490
 491 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 492 {
 493         if (delta > ch->max_match_value)
 494                 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
 495                          ch->index);
 496
 497         ch->next_match_value = delta;
 498         sh_cmt_clock_event_program_verify(ch, 0);
 499 }
 500
 501 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 502 {
 503         unsigned long flags;
 504
 505         raw_spin_lock_irqsave(&ch->lock, flags);
 506         __sh_cmt_set_next(ch, delta);
 507         raw_spin_unlock_irqrestore(&ch->lock, flags);
 508 }
 509
 510 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
 511 {
 512         struct sh_cmt_channel *ch = dev_id;
 513
 514         /* clear flags */
 515         sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
 516                            ch->cmt->info->clear_bits);
 517
 518         /* update clock source counter to begin with if enabled
 519          * the wrap flag should be cleared by the timer specific
 520          * isr before we end up here.
 521          */
 522         if (ch->flags & FLAG_CLOCKSOURCE)
 523                 ch->total_cycles += ch->match_value + 1;
 524
 525         if (!(ch->flags & FLAG_REPROGRAM))
 526                 ch->next_match_value = ch->max_match_value;
 527
 528         ch->flags |= FLAG_IRQCONTEXT;
 529
 530         if (ch->flags & FLAG_CLOCKEVENT) {
 531                 if (!(ch->flags & FLAG_SKIPEVENT)) {
 532                         if (clockevent_state_oneshot(&ch->ced)) {
 533                                 ch->next_match_value = ch->max_match_value;
 534                                 ch->flags |= FLAG_REPROGRAM;
 535                         }
 536
 537                         ch->ced.event_handler(&ch->ced);
 538                 }
 539         }
 540
 541         ch->flags &= ~FLAG_SKIPEVENT;
 542
 543         if (ch->flags & FLAG_REPROGRAM) {
 544                 ch->flags &= ~FLAG_REPROGRAM;
 545                 sh_cmt_clock_event_program_verify(ch, 1);
 546
 547                 if (ch->flags & FLAG_CLOCKEVENT)
 548                         if ((clockevent_state_shutdown(&ch->ced))
 549                             || (ch->match_value == ch->next_match_value))
 550                                 ch->flags &= ~FLAG_REPROGRAM;
 551         }
 552
 553         ch->flags &= ~FLAG_IRQCONTEXT;
 554
 555         return IRQ_HANDLED;
 556 }
 557
 558 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
 559 {
 560         int ret = 0;
 561         unsigned long flags;
 562
 563         raw_spin_lock_irqsave(&ch->lock, flags);
 564
 565         if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 566                 ret = sh_cmt_enable(ch);
 567
 568         if (ret)
 569                 goto out;
 570         ch->flags |= flag;
 571
 572         /* setup timeout if no clockevent */
 573         if (ch->cmt->num_channels == 1 &&
 574             flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT)))
 575                 __sh_cmt_set_next(ch, ch->max_match_value);
 576  out:
 577         raw_spin_unlock_irqrestore(&ch->lock, flags);
 578
 579         return ret;
 580 }
 581
 582 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
 583 {
 584         unsigned long flags;
 585         unsigned long f;
 586
 587         raw_spin_lock_irqsave(&ch->lock, flags);
 588
 589         f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
 590         ch->flags &= ~flag;
 591
 592         if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 593                 sh_cmt_disable(ch);
 594
 595         /* adjust the timeout to maximum if only clocksource left */
 596         if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
 597                 __sh_cmt_set_next(ch, ch->max_match_value);
 598
 599         raw_spin_unlock_irqrestore(&ch->lock, flags);
 600 }
 601
 602 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
 603 {
 604         return container_of(cs, struct sh_cmt_channel, cs);
 605 }
 606
 607 static u64 sh_cmt_clocksource_read(struct clocksource *cs)
 608 {
 609         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 610         u32 has_wrapped;
 611
 612         if (ch->cmt->num_channels == 1) {
 613                 unsigned long flags;
 614                 u64 value;
 615                 u32 raw;
 616
 617                 raw_spin_lock_irqsave(&ch->lock, flags);
 618                 value = ch->total_cycles;
 619                 raw = sh_cmt_get_counter(ch, &has_wrapped);
 620
 621                 if (unlikely(has_wrapped))
 622                         raw += ch->match_value + 1;
 623                 raw_spin_unlock_irqrestore(&ch->lock, flags);
 624
 625                 return value + raw;
 626         }
 627
 628         return sh_cmt_get_counter(ch, &has_wrapped);
 629 }
 630
 631 static int sh_cmt_clocksource_enable(struct clocksource *cs)
 632 {
 633         int ret;
 634         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 635
 636         WARN_ON(ch->cs_enabled);
 637
 638         ch->total_cycles = 0;
 639
 640         ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 641         if (!ret)
 642                 ch->cs_enabled = true;
 643
 644         return ret;
 645 }
 646
 647 static void sh_cmt_clocksource_disable(struct clocksource *cs)
 648 {
 649         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 650
 651         WARN_ON(!ch->cs_enabled);
 652
 653         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 654         ch->cs_enabled = false;
 655 }
 656
 657 static void sh_cmt_clocksource_suspend(struct clocksource *cs)
 658 {
 659         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 660
 661         if (!ch->cs_enabled)
 662                 return;
 663
 664         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 665         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 666 }
 667
 668 static void sh_cmt_clocksource_resume(struct clocksource *cs)
 669 {
 670         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 671
 672         if (!ch->cs_enabled)
 673                 return;
 674
 675         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 676         sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 677 }
 678
 679 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
 680                                        const char *name)
 681 {
 682         struct clocksource *cs = &ch->cs;
 683
 684         cs->name = name;
 685         cs->rating = 125;
 686         cs->read = sh_cmt_clocksource_read;
 687         cs->enable = sh_cmt_clocksource_enable;
 688         cs->disable = sh_cmt_clocksource_disable;
 689         cs->suspend = sh_cmt_clocksource_suspend;
 690         cs->resume = sh_cmt_clocksource_resume;
 691         cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width);
 692         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 693
 694         dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
 695                  ch->index);
 696
 697         clocksource_register_hz(cs, ch->cmt->rate);
 698         return 0;
 699 }
 700
 701 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
 702 {
 703         return container_of(ced, struct sh_cmt_channel, ced);
 704 }
 705
 706 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
 707 {
 708         sh_cmt_start(ch, FLAG_CLOCKEVENT);
 709
 710         if (periodic)
 711                 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
 712         else
 713                 sh_cmt_set_next(ch, ch->max_match_value);
 714 }
 715
 716 static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
 717 {
 718         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 719
 720         sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 721         return 0;
 722 }
 723
 724 static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
 725                                         int periodic)
 726 {
 727         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 728
 729         /* deal with old setting first */
 730         if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
 731                 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 732
 733         dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
 734                  ch->index, periodic ? "periodic" : "oneshot");
 735         sh_cmt_clock_event_start(ch, periodic);
 736         return 0;
 737 }
 738
 739 static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
 740 {
 741         return sh_cmt_clock_event_set_state(ced, 0);
 742 }
 743
 744 static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
 745 {
 746         return sh_cmt_clock_event_set_state(ced, 1);
 747 }
 748
 749 static int sh_cmt_clock_event_next(unsigned long delta,
 750                                    struct clock_event_device *ced)
 751 {
 752         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 753
 754         BUG_ON(!clockevent_state_oneshot(ced));
 755         if (likely(ch->flags & FLAG_IRQCONTEXT))
 756                 ch->next_match_value = delta - 1;
 757         else
 758                 sh_cmt_set_next(ch, delta - 1);
 759
 760         return 0;
 761 }
 762
 763 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
 764 {
 765         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 766
 767         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 768         clk_unprepare(ch->cmt->clk);
 769 }
 770
 771 static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
 772 {
 773         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 774
 775         clk_prepare(ch->cmt->clk);
 776         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 777 }
 778
 779 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
 780                                       const char *name)
 781 {
 782         struct clock_event_device *ced = &ch->ced;
 783         int irq;
 784         int ret;
 785
 786         irq = platform_get_irq(ch->cmt->pdev, ch->index);
 787         if (irq < 0)
 788                 return irq;
 789
 790         ret = request_irq(irq, sh_cmt_interrupt,
 791                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 792                           dev_name(&ch->cmt->pdev->dev), ch);
 793         if (ret) {
 794                 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
 795                         ch->index, irq);
 796                 return ret;
 797         }
 798
 799         ced->name = name;
 800         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 801         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 802         ced->rating = 125;
 803         ced->cpumask = cpu_possible_mask;
 804         ced->set_next_event = sh_cmt_clock_event_next;
 805         ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
 806         ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
 807         ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
 808         ced->suspend = sh_cmt_clock_event_suspend;
 809         ced->resume = sh_cmt_clock_event_resume;
 810
 811         /* TODO: calculate good shift from rate and counter bit width */
 812         ced->shift = 32;
 813         ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
 814         ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
 815         ced->max_delta_ticks = ch->max_match_value;
 816         ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
 817         ced->min_delta_ticks = 0x1f;
 818
 819         dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
 820                  ch->index);
 821         clockevents_register_device(ced);
 822
 823         return 0;
 824 }
 825
 826 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
 827                            bool clockevent, bool clocksource)
 828 {
 829         int ret;
 830
 831         if (clockevent) {
 832                 ch->cmt->has_clockevent = true;
 833                 ret = sh_cmt_register_clockevent(ch, name);
 834                 if (ret < 0)
 835                         return ret;
 836         }
 837
 838         if (clocksource) {
 839                 ch->cmt->has_clocksource = true;
 840                 sh_cmt_register_clocksource(ch, name);
 841         }
 842
 843         return 0;
 844 }
 845
 846 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
 847                                 unsigned int hwidx, bool clockevent,
 848                                 bool clocksource, struct sh_cmt_device *cmt)
 849 {
 850         u32 value;
 851         int ret;
 852
 853         /* Skip unused channels. */
 854         if (!clockevent && !clocksource)
 855                 return 0;
 856
 857         ch->cmt = cmt;
 858         ch->index = index;
 859         ch->hwidx = hwidx;
 860         ch->timer_bit = hwidx;
 861
 862         /*
 863          * Compute the address of the channel control register block. For the
 864          * timers with a per-channel start/stop register, compute its address
 865          * as well.
 866          */
 867         switch (cmt->info->model) {
 868         case SH_CMT_16BIT:
 869                 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
 870                 break;
 871         case SH_CMT_32BIT:
 872         case SH_CMT_48BIT:
 873                 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
 874                 break;
 875         case SH_CMT0_RCAR_GEN2:
 876         case SH_CMT1_RCAR_GEN2:
 877                 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
 878                 ch->ioctrl = ch->iostart + 0x10;
 879                 ch->timer_bit = 0;
 880
 881                 /* Enable the clock supply to the channel */
 882                 value = ioread32(cmt->mapbase + CMCLKE);
 883                 value |= BIT(hwidx);
 884                 iowrite32(value, cmt->mapbase + CMCLKE);
 885                 break;
 886         }
 887
 888         if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
 889                 ch->max_match_value = ~0;
 890         else
 891                 ch->max_match_value = (1 << cmt->info->width) - 1;
 892
 893         ch->match_value = ch->max_match_value;
 894         raw_spin_lock_init(&ch->lock);
 895
 896         ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
 897                               clockevent, clocksource);
 898         if (ret) {
 899                 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
 900                         ch->index);
 901                 return ret;
 902         }
 903         ch->cs_enabled = false;
 904
 905         return 0;
 906 }
 907
 908 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
 909 {
 910         struct resource *mem;
 911
 912         mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
 913         if (!mem) {
 914                 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
 915                 return -ENXIO;
 916         }
 917
 918         cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
 919         if (cmt->mapbase == NULL) {
 920                 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
 921                 return -ENXIO;
 922         }
 923
 924         return 0;
 925 }
 926
 927 static const struct platform_device_id sh_cmt_id_table[] = {
 928         { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
 929         { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
 930         { }
 931 };
 932 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
 933
 934 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
 935         {
 936                 /* deprecated, preserved for backward compatibility */
 937                 .compatible = "renesas,cmt-48",
 938                 .data = &sh_cmt_info[SH_CMT_48BIT]
 939         },
 940         {
 941                 /* deprecated, preserved for backward compatibility */
 942                 .compatible = "renesas,cmt-48-gen2",
 943                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 944         },
 945         {
 946                 .compatible = "renesas,r8a7740-cmt1",
 947                 .data = &sh_cmt_info[SH_CMT_48BIT]
 948         },
 949         {
 950                 .compatible = "renesas,sh73a0-cmt1",
 951                 .data = &sh_cmt_info[SH_CMT_48BIT]
 952         },
 953         {
 954                 .compatible = "renesas,rcar-gen2-cmt0",
 955                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 956         },
 957         {
 958                 .compatible = "renesas,rcar-gen2-cmt1",
 959                 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
 960         },
 961         {
 962                 .compatible = "renesas,rcar-gen3-cmt0",
 963                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 964         },
 965         {
 966                 .compatible = "renesas,rcar-gen3-cmt1",
 967                 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
 968         },
 969         { }
 970 };
 971 MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
 972
 973 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
 974 {
 975         unsigned int mask;
 976         unsigned int i;
 977         int ret;
 978
 979         cmt->pdev = pdev;
 980         raw_spin_lock_init(&cmt->lock);
 981
 982         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
 983                 cmt->info = of_device_get_match_data(&pdev->dev);
 984                 cmt->hw_channels = cmt->info->channels_mask;
 985         } else if (pdev->dev.platform_data) {
 986                 struct sh_timer_config *cfg = pdev->dev.platform_data;
 987                 const struct platform_device_id *id = pdev->id_entry;
 988
 989                 cmt->info = (const struct sh_cmt_info *)id->driver_data;
 990                 cmt->hw_channels = cfg->channels_mask;
 991         } else {
 992                 dev_err(&cmt->pdev->dev, "missing platform data\n");
 993                 return -ENXIO;
 994         }
 995
 996         /* Get hold of clock. */
 997         cmt->clk = clk_get(&cmt->pdev->dev, "fck");
 998         if (IS_ERR(cmt->clk)) {
 999                 dev_err(&cmt->pdev->dev, "cannot get clock\n");
1000                 return PTR_ERR(cmt->clk);
1001         }
1002
1003         ret = clk_prepare(cmt->clk);
1004         if (ret < 0)
1005                 goto err_clk_put;
1006
1007         /* Determine clock rate. */
1008         ret = clk_enable(cmt->clk);
1009         if (ret < 0)
1010                 goto err_clk_unprepare;
1011
1012         if (cmt->info->width == 16)
1013                 cmt->rate = clk_get_rate(cmt->clk) / 512;
1014         else
1015                 cmt->rate = clk_get_rate(cmt->clk) / 8;
1016
1017         /* Map the memory resource(s). */
1018         ret = sh_cmt_map_memory(cmt);
1019         if (ret < 0)
1020                 goto err_clk_disable;
1021
1022         /* Allocate and setup the channels. */
1023         cmt->num_channels = hweight8(cmt->hw_channels);
1024         cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1025                                 GFP_KERNEL);
1026         if (cmt->channels == NULL) {
1027                 ret = -ENOMEM;
1028                 goto err_unmap;
1029         }
1030
1031         /*
1032          * Use the first channel as a clock event device and the second channel
1033          * as a clock source. If only one channel is available use it for both.
1034          */
1035         for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1036                 unsigned int hwidx = ffs(mask) - 1;
1037                 bool clocksource = i == 1 || cmt->num_channels == 1;
1038                 bool clockevent = i == 0;
1039
1040                 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1041                                            clockevent, clocksource, cmt);
1042                 if (ret < 0)
1043                         goto err_unmap;
1044
1045                 mask &= ~(1 << hwidx);
1046         }
1047
1048         clk_disable(cmt->clk);
1049
1050         platform_set_drvdata(pdev, cmt);
1051
1052         return 0;
1053
1054 err_unmap:
1055         kfree(cmt->channels);
1056         iounmap(cmt->mapbase);
1057 err_clk_disable:
1058         clk_disable(cmt->clk);
1059 err_clk_unprepare:
1060         clk_unprepare(cmt->clk);
1061 err_clk_put:
1062         clk_put(cmt->clk);
1063         return ret;
1064 }
1065
1066 static int sh_cmt_probe(struct platform_device *pdev)
1067 {
1068         struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1069         int ret;
1070
1071         if (!is_early_platform_device(pdev)) {
1072                 pm_runtime_set_active(&pdev->dev);
1073                 pm_runtime_enable(&pdev->dev);
1074         }
1075
1076         if (cmt) {
1077                 dev_info(&pdev->dev, "kept as earlytimer\n");
1078                 goto out;
1079         }
1080
1081         cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1082         if (cmt == NULL)
1083                 return -ENOMEM;
1084
1085         ret = sh_cmt_setup(cmt, pdev);
1086         if (ret) {
1087                 kfree(cmt);
1088                 pm_runtime_idle(&pdev->dev);
1089                 return ret;
1090         }
1091         if (is_early_platform_device(pdev))
1092                 return 0;
1093
1094  out:
1095         if (cmt->has_clockevent || cmt->has_clocksource)
1096                 pm_runtime_irq_safe(&pdev->dev);
1097         else
1098                 pm_runtime_idle(&pdev->dev);
1099
1100         return 0;
1101 }
1102
1103 static int sh_cmt_remove(struct platform_device *pdev)
1104 {
1105         return -EBUSY; /* cannot unregister clockevent and clocksource */
1106 }
1107
1108 static struct platform_driver sh_cmt_device_driver = {
1109         .probe          = sh_cmt_probe,
1110         .remove         = sh_cmt_remove,
1111         .driver         = {
1112                 .name   = "sh_cmt",
1113                 .of_match_table = of_match_ptr(sh_cmt_of_table),
1114         },
1115         .id_table       = sh_cmt_id_table,
1116 };
1117
1118 static int __init sh_cmt_init(void)
1119 {
1120         return platform_driver_register(&sh_cmt_device_driver);
1121 }
1122
1123 static void __exit sh_cmt_exit(void)
1124 {
1125         platform_driver_unregister(&sh_cmt_device_driver);
1126 }
1127
1128 early_platform_init("earlytimer", &sh_cmt_device_driver);
1129 subsys_initcall(sh_cmt_init);
1130 module_exit(sh_cmt_exit);
1131
1132 MODULE_AUTHOR("Magnus Damm");
1133 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1134 MODULE_LICENSE("GPL v2");