drivers/clocksource/sh_cmt.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SuperH Timer Support - CMT
   4  *
   5  *  Copyright (C) 2008 Magnus Damm
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/clockchips.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/ioport.h>
  17 #include <linux/irq.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_domain.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/sh_timer.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27
  28 struct sh_cmt_device;
  29
  30 /*
  31  * The CMT comes in 5 different identified flavours, depending not only on the
  32  * SoC but also on the particular instance. The following table lists the main
  33  * characteristics of those flavours.
  34  *
  35  *                      16B     32B     32B-F   48B     R-Car Gen2
  36  * -----------------------------------------------------------------------------
  37  * Channels             2       1/4     1       6       2/8
  38  * Control Width        16      16      16      16      32
  39  * Counter Width        16      32      32      32/48   32/48
  40  * Shared Start/Stop    Y       Y       Y       Y       N
  41  *
  42  * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
  43  * located in the channel registers block. All other versions have a shared
  44  * start/stop register located in the global space.
  45  *
  46  * Channels are indexed from 0 to N-1 in the documentation. The channel index
  47  * infers the start/stop bit position in the control register and the channel
  48  * registers block address. Some CMT instances have a subset of channels
  49  * available, in which case the index in the documentation doesn't match the
  50  * "real" index as implemented in hardware. This is for instance the case with
  51  * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
  52  * in the documentation but using start/stop bit 5 and having its registers
  53  * block at 0x60.
  54  *
  55  * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
  56  * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
  57  */
  58
  59 enum sh_cmt_model {
  60         SH_CMT_16BIT,
  61         SH_CMT_32BIT,
  62         SH_CMT_48BIT,
  63         SH_CMT0_RCAR_GEN2,
  64         SH_CMT1_RCAR_GEN2,
  65 };
  66
  67 struct sh_cmt_info {
  68         enum sh_cmt_model model;
  69
  70         unsigned int channels_mask;
  71
  72         unsigned long width; /* 16 or 32 bit version of hardware block */
  73         u32 overflow_bit;
  74         u32 clear_bits;
  75
  76         /* callbacks for CMSTR and CMCSR access */
  77         u32 (*read_control)(void __iomem *base, unsigned long offs);
  78         void (*write_control)(void __iomem *base, unsigned long offs,
  79                               u32 value);
  80
  81         /* callbacks for CMCNT and CMCOR access */
  82         u32 (*read_count)(void __iomem *base, unsigned long offs);
  83         void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
  84 };
  85
  86 struct sh_cmt_channel {
  87         struct sh_cmt_device *cmt;
  88
  89         unsigned int index;     /* Index in the documentation */
  90         unsigned int hwidx;     /* Real hardware index */
  91
  92         void __iomem *iostart;
  93         void __iomem *ioctrl;
  94
  95         unsigned int timer_bit;
  96         unsigned long flags;
  97         u32 match_value;
  98         u32 next_match_value;
  99         u32 max_match_value;
 100         raw_spinlock_t lock;
 101         struct clock_event_device ced;
 102         struct clocksource cs;
 103         u64 total_cycles;
 104         bool cs_enabled;
 105 };
 106
 107 struct sh_cmt_device {
 108         struct platform_device *pdev;
 109
 110         const struct sh_cmt_info *info;
 111
 112         void __iomem *mapbase;
 113         struct clk *clk;
 114         unsigned long rate;
 115
 116         raw_spinlock_t lock; /* Protect the shared start/stop register */
 117
 118         struct sh_cmt_channel *channels;
 119         unsigned int num_channels;
 120         unsigned int hw_channels;
 121
 122         bool has_clockevent;
 123         bool has_clocksource;
 124 };
 125
 126 #define SH_CMT16_CMCSR_CMF              (1 << 7)
 127 #define SH_CMT16_CMCSR_CMIE             (1 << 6)
 128 #define SH_CMT16_CMCSR_CKS8             (0 << 0)
 129 #define SH_CMT16_CMCSR_CKS32            (1 << 0)
 130 #define SH_CMT16_CMCSR_CKS128           (2 << 0)
 131 #define SH_CMT16_CMCSR_CKS512           (3 << 0)
 132 #define SH_CMT16_CMCSR_CKS_MASK         (3 << 0)
 133
 134 #define SH_CMT32_CMCSR_CMF              (1 << 15)
 135 #define SH_CMT32_CMCSR_OVF              (1 << 14)
 136 #define SH_CMT32_CMCSR_WRFLG            (1 << 13)
 137 #define SH_CMT32_CMCSR_STTF             (1 << 12)
 138 #define SH_CMT32_CMCSR_STPF             (1 << 11)
 139 #define SH_CMT32_CMCSR_SSIE             (1 << 10)
 140 #define SH_CMT32_CMCSR_CMS              (1 << 9)
 141 #define SH_CMT32_CMCSR_CMM              (1 << 8)
 142 #define SH_CMT32_CMCSR_CMTOUT_IE        (1 << 7)
 143 #define SH_CMT32_CMCSR_CMR_NONE         (0 << 4)
 144 #define SH_CMT32_CMCSR_CMR_DMA          (1 << 4)
 145 #define SH_CMT32_CMCSR_CMR_IRQ          (2 << 4)
 146 #define SH_CMT32_CMCSR_CMR_MASK         (3 << 4)
 147 #define SH_CMT32_CMCSR_DBGIVD           (1 << 3)
 148 #define SH_CMT32_CMCSR_CKS_RCLK8        (4 << 0)
 149 #define SH_CMT32_CMCSR_CKS_RCLK32       (5 << 0)
 150 #define SH_CMT32_CMCSR_CKS_RCLK128      (6 << 0)
 151 #define SH_CMT32_CMCSR_CKS_RCLK1        (7 << 0)
 152 #define SH_CMT32_CMCSR_CKS_MASK         (7 << 0)
 153
 154 static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
 155 {
 156         return ioread16(base + (offs << 1));
 157 }
 158
 159 static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
 160 {
 161         return ioread32(base + (offs << 2));
 162 }
 163
 164 static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
 165 {
 166         iowrite16(value, base + (offs << 1));
 167 }
 168
 169 static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
 170 {
 171         iowrite32(value, base + (offs << 2));
 172 }
 173
 174 static const struct sh_cmt_info sh_cmt_info[] = {
 175         [SH_CMT_16BIT] = {
 176                 .model = SH_CMT_16BIT,
 177                 .width = 16,
 178                 .overflow_bit = SH_CMT16_CMCSR_CMF,
 179                 .clear_bits = ~SH_CMT16_CMCSR_CMF,
 180                 .read_control = sh_cmt_read16,
 181                 .write_control = sh_cmt_write16,
 182                 .read_count = sh_cmt_read16,
 183                 .write_count = sh_cmt_write16,
 184         },
 185         [SH_CMT_32BIT] = {
 186                 .model = SH_CMT_32BIT,
 187                 .width = 32,
 188                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 189                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 190                 .read_control = sh_cmt_read16,
 191                 .write_control = sh_cmt_write16,
 192                 .read_count = sh_cmt_read32,
 193                 .write_count = sh_cmt_write32,
 194         },
 195         [SH_CMT_48BIT] = {
 196                 .model = SH_CMT_48BIT,
 197                 .channels_mask = 0x3f,
 198                 .width = 32,
 199                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 200                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 201                 .read_control = sh_cmt_read32,
 202                 .write_control = sh_cmt_write32,
 203                 .read_count = sh_cmt_read32,
 204                 .write_count = sh_cmt_write32,
 205         },
 206         [SH_CMT0_RCAR_GEN2] = {
 207                 .model = SH_CMT0_RCAR_GEN2,
 208                 .channels_mask = 0x60,
 209                 .width = 32,
 210                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 211                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 212                 .read_control = sh_cmt_read32,
 213                 .write_control = sh_cmt_write32,
 214                 .read_count = sh_cmt_read32,
 215                 .write_count = sh_cmt_write32,
 216         },
 217         [SH_CMT1_RCAR_GEN2] = {
 218                 .model = SH_CMT1_RCAR_GEN2,
 219                 .channels_mask = 0xff,
 220                 .width = 32,
 221                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 222                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 223                 .read_control = sh_cmt_read32,
 224                 .write_control = sh_cmt_write32,
 225                 .read_count = sh_cmt_read32,
 226                 .write_count = sh_cmt_write32,
 227         },
 228 };
 229
 230 #define CMCSR 0 /* channel register */
 231 #define CMCNT 1 /* channel register */
 232 #define CMCOR 2 /* channel register */
 233
 234 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
 235 {
 236         if (ch->iostart)
 237                 return ch->cmt->info->read_control(ch->iostart, 0);
 238         else
 239                 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
 240 }
 241
 242 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
 243 {
 244         if (ch->iostart)
 245                 ch->cmt->info->write_control(ch->iostart, 0, value);
 246         else
 247                 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
 248 }
 249
 250 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
 251 {
 252         return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
 253 }
 254
 255 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
 256 {
 257         ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
 258 }
 259
 260 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
 261 {
 262         return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
 263 }
 264
 265 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
 266 {
 267         ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
 268 }
 269
 270 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
 271 {
 272         ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
 273 }
 274
 275 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
 276 {
 277         u32 v1, v2, v3;
 278         u32 o1, o2;
 279
 280         o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 281
 282         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
 283         do {
 284                 o2 = o1;
 285                 v1 = sh_cmt_read_cmcnt(ch);
 286                 v2 = sh_cmt_read_cmcnt(ch);
 287                 v3 = sh_cmt_read_cmcnt(ch);
 288                 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 289         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
 290                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 291
 292         *has_wrapped = o1;
 293         return v2;
 294 }
 295
 296 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
 297 {
 298         unsigned long flags;
 299         u32 value;
 300
 301         /* start stop register shared by multiple timer channels */
 302         raw_spin_lock_irqsave(&ch->cmt->lock, flags);
 303         value = sh_cmt_read_cmstr(ch);
 304
 305         if (start)
 306                 value |= 1 << ch->timer_bit;
 307         else
 308                 value &= ~(1 << ch->timer_bit);
 309
 310         sh_cmt_write_cmstr(ch, value);
 311         raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
 312 }
 313
 314 static int sh_cmt_enable(struct sh_cmt_channel *ch)
 315 {
 316         int k, ret;
 317
 318         pm_runtime_get_sync(&ch->cmt->pdev->dev);
 319         dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
 320
 321         /* enable clock */
 322         ret = clk_enable(ch->cmt->clk);
 323         if (ret) {
 324                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
 325                         ch->index);
 326                 goto err0;
 327         }
 328
 329         /* make sure channel is disabled */
 330         sh_cmt_start_stop_ch(ch, 0);
 331
 332         /* configure channel, periodic mode and maximum timeout */
 333         if (ch->cmt->info->width == 16) {
 334                 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
 335                                    SH_CMT16_CMCSR_CKS512);
 336         } else {
 337                 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
 338                                    SH_CMT32_CMCSR_CMTOUT_IE |
 339                                    SH_CMT32_CMCSR_CMR_IRQ |
 340                                    SH_CMT32_CMCSR_CKS_RCLK8);
 341         }
 342
 343         sh_cmt_write_cmcor(ch, 0xffffffff);
 344         sh_cmt_write_cmcnt(ch, 0);
 345
 346         /*
 347          * According to the sh73a0 user's manual, as CMCNT can be operated
 348          * only by the RCLK (Pseudo 32 KHz), there's one restriction on
 349          * modifying CMCNT register; two RCLK cycles are necessary before
 350          * this register is either read or any modification of the value
 351          * it holds is reflected in the LSI's actual operation.
 352          *
 353          * While at it, we're supposed to clear out the CMCNT as of this
 354          * moment, so make sure it's processed properly here.  This will
 355          * take RCLKx2 at maximum.
 356          */
 357         for (k = 0; k < 100; k++) {
 358                 if (!sh_cmt_read_cmcnt(ch))
 359                         break;
 360                 udelay(1);
 361         }
 362
 363         if (sh_cmt_read_cmcnt(ch)) {
 364                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
 365                         ch->index);
 366                 ret = -ETIMEDOUT;
 367                 goto err1;
 368         }
 369
 370         /* enable channel */
 371         sh_cmt_start_stop_ch(ch, 1);
 372         return 0;
 373  err1:
 374         /* stop clock */
 375         clk_disable(ch->cmt->clk);
 376
 377  err0:
 378         return ret;
 379 }
 380
 381 static void sh_cmt_disable(struct sh_cmt_channel *ch)
 382 {
 383         /* disable channel */
 384         sh_cmt_start_stop_ch(ch, 0);
 385
 386         /* disable interrupts in CMT block */
 387         sh_cmt_write_cmcsr(ch, 0);
 388
 389         /* stop clock */
 390         clk_disable(ch->cmt->clk);
 391
 392         dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
 393         pm_runtime_put(&ch->cmt->pdev->dev);
 394 }
 395
 396 /* private flags */
 397 #define FLAG_CLOCKEVENT (1 << 0)
 398 #define FLAG_CLOCKSOURCE (1 << 1)
 399 #define FLAG_REPROGRAM (1 << 2)
 400 #define FLAG_SKIPEVENT (1 << 3)
 401 #define FLAG_IRQCONTEXT (1 << 4)
 402
 403 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
 404                                               int absolute)
 405 {
 406         u32 value = ch->next_match_value;
 407         u32 new_match;
 408         u32 delay = 0;
 409         u32 now = 0;
 410         u32 has_wrapped;
 411
 412         now = sh_cmt_get_counter(ch, &has_wrapped);
 413         ch->flags |= FLAG_REPROGRAM; /* force reprogram */
 414
 415         if (has_wrapped) {
 416                 /* we're competing with the interrupt handler.
 417                  *  -> let the interrupt handler reprogram the timer.
 418                  *  -> interrupt number two handles the event.
 419                  */
 420                 ch->flags |= FLAG_SKIPEVENT;
 421                 return;
 422         }
 423
 424         if (absolute)
 425                 now = 0;
 426
 427         do {
 428                 /* reprogram the timer hardware,
 429                  * but don't save the new match value yet.
 430                  */
 431                 new_match = now + value + delay;
 432                 if (new_match > ch->max_match_value)
 433                         new_match = ch->max_match_value;
 434
 435                 sh_cmt_write_cmcor(ch, new_match);
 436
 437                 now = sh_cmt_get_counter(ch, &has_wrapped);
 438                 if (has_wrapped && (new_match > ch->match_value)) {
 439                         /* we are changing to a greater match value,
 440                          * so this wrap must be caused by the counter
 441                          * matching the old value.
 442                          * -> first interrupt reprograms the timer.
 443                          * -> interrupt number two handles the event.
 444                          */
 445                         ch->flags |= FLAG_SKIPEVENT;
 446                         break;
 447                 }
 448
 449                 if (has_wrapped) {
 450                         /* we are changing to a smaller match value,
 451                          * so the wrap must be caused by the counter
 452                          * matching the new value.
 453                          * -> save programmed match value.
 454                          * -> let isr handle the event.
 455                          */
 456                         ch->match_value = new_match;
 457                         break;
 458                 }
 459
 460                 /* be safe: verify hardware settings */
 461                 if (now < new_match) {
 462                         /* timer value is below match value, all good.
 463                          * this makes sure we won't miss any match events.
 464                          * -> save programmed match value.
 465                          * -> let isr handle the event.
 466                          */
 467                         ch->match_value = new_match;
 468                         break;
 469                 }
 470
 471                 /* the counter has reached a value greater
 472                  * than our new match value. and since the
 473                  * has_wrapped flag isn't set we must have
 474                  * programmed a too close event.
 475                  * -> increase delay and retry.
 476                  */
 477                 if (delay)
 478                         delay <<= 1;
 479                 else
 480                         delay = 1;
 481
 482                 if (!delay)
 483                         dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
 484                                  ch->index);
 485
 486         } while (delay);
 487 }
 488
 489 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 490 {
 491         if (delta > ch->max_match_value)
 492                 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
 493                          ch->index);
 494
 495         ch->next_match_value = delta;
 496         sh_cmt_clock_event_program_verify(ch, 0);
 497 }
 498
 499 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 500 {
 501         unsigned long flags;
 502
 503         raw_spin_lock_irqsave(&ch->lock, flags);
 504         __sh_cmt_set_next(ch, delta);
 505         raw_spin_unlock_irqrestore(&ch->lock, flags);
 506 }
 507
 508 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
 509 {
 510         struct sh_cmt_channel *ch = dev_id;
 511
 512         /* clear flags */
 513         sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
 514                            ch->cmt->info->clear_bits);
 515
 516         /* update clock source counter to begin with if enabled
 517          * the wrap flag should be cleared by the timer specific
 518          * isr before we end up here.
 519          */
 520         if (ch->flags & FLAG_CLOCKSOURCE)
 521                 ch->total_cycles += ch->match_value + 1;
 522
 523         if (!(ch->flags & FLAG_REPROGRAM))
 524                 ch->next_match_value = ch->max_match_value;
 525
 526         ch->flags |= FLAG_IRQCONTEXT;
 527
 528         if (ch->flags & FLAG_CLOCKEVENT) {
 529                 if (!(ch->flags & FLAG_SKIPEVENT)) {
 530                         if (clockevent_state_oneshot(&ch->ced)) {
 531                                 ch->next_match_value = ch->max_match_value;
 532                                 ch->flags |= FLAG_REPROGRAM;
 533                         }
 534
 535                         ch->ced.event_handler(&ch->ced);
 536                 }
 537         }
 538
 539         ch->flags &= ~FLAG_SKIPEVENT;
 540
 541         if (ch->flags & FLAG_REPROGRAM) {
 542                 ch->flags &= ~FLAG_REPROGRAM;
 543                 sh_cmt_clock_event_program_verify(ch, 1);
 544
 545                 if (ch->flags & FLAG_CLOCKEVENT)
 546                         if ((clockevent_state_shutdown(&ch->ced))
 547                             || (ch->match_value == ch->next_match_value))
 548                                 ch->flags &= ~FLAG_REPROGRAM;
 549         }
 550
 551         ch->flags &= ~FLAG_IRQCONTEXT;
 552
 553         return IRQ_HANDLED;
 554 }
 555
 556 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
 557 {
 558         int ret = 0;
 559         unsigned long flags;
 560
 561         raw_spin_lock_irqsave(&ch->lock, flags);
 562
 563         if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 564                 ret = sh_cmt_enable(ch);
 565
 566         if (ret)
 567                 goto out;
 568         ch->flags |= flag;
 569
 570         /* setup timeout if no clockevent */
 571         if (ch->cmt->num_channels == 1 &&
 572             flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT)))
 573                 __sh_cmt_set_next(ch, ch->max_match_value);
 574  out:
 575         raw_spin_unlock_irqrestore(&ch->lock, flags);
 576
 577         return ret;
 578 }
 579
 580 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
 581 {
 582         unsigned long flags;
 583         unsigned long f;
 584
 585         raw_spin_lock_irqsave(&ch->lock, flags);
 586
 587         f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
 588         ch->flags &= ~flag;
 589
 590         if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 591                 sh_cmt_disable(ch);
 592
 593         /* adjust the timeout to maximum if only clocksource left */
 594         if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
 595                 __sh_cmt_set_next(ch, ch->max_match_value);
 596
 597         raw_spin_unlock_irqrestore(&ch->lock, flags);
 598 }
 599
 600 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
 601 {
 602         return container_of(cs, struct sh_cmt_channel, cs);
 603 }
 604
 605 static u64 sh_cmt_clocksource_read(struct clocksource *cs)
 606 {
 607         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 608         u32 has_wrapped;
 609
 610         if (ch->cmt->num_channels == 1) {
 611                 unsigned long flags;
 612                 u64 value;
 613                 u32 raw;
 614
 615                 raw_spin_lock_irqsave(&ch->lock, flags);
 616                 value = ch->total_cycles;
 617                 raw = sh_cmt_get_counter(ch, &has_wrapped);
 618
 619                 if (unlikely(has_wrapped))
 620                         raw += ch->match_value + 1;
 621                 raw_spin_unlock_irqrestore(&ch->lock, flags);
 622
 623                 return value + raw;
 624         }
 625
 626         return sh_cmt_get_counter(ch, &has_wrapped);
 627 }
 628
 629 static int sh_cmt_clocksource_enable(struct clocksource *cs)
 630 {
 631         int ret;
 632         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 633
 634         WARN_ON(ch->cs_enabled);
 635
 636         ch->total_cycles = 0;
 637
 638         ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 639         if (!ret)
 640                 ch->cs_enabled = true;
 641
 642         return ret;
 643 }
 644
 645 static void sh_cmt_clocksource_disable(struct clocksource *cs)
 646 {
 647         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 648
 649         WARN_ON(!ch->cs_enabled);
 650
 651         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 652         ch->cs_enabled = false;
 653 }
 654
 655 static void sh_cmt_clocksource_suspend(struct clocksource *cs)
 656 {
 657         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 658
 659         if (!ch->cs_enabled)
 660                 return;
 661
 662         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 663         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 664 }
 665
 666 static void sh_cmt_clocksource_resume(struct clocksource *cs)
 667 {
 668         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 669
 670         if (!ch->cs_enabled)
 671                 return;
 672
 673         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 674         sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 675 }
 676
 677 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
 678                                        const char *name)
 679 {
 680         struct clocksource *cs = &ch->cs;
 681
 682         cs->name = name;
 683         cs->rating = 125;
 684         cs->read = sh_cmt_clocksource_read;
 685         cs->enable = sh_cmt_clocksource_enable;
 686         cs->disable = sh_cmt_clocksource_disable;
 687         cs->suspend = sh_cmt_clocksource_suspend;
 688         cs->resume = sh_cmt_clocksource_resume;
 689         cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width);
 690         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 691
 692         dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
 693                  ch->index);
 694
 695         clocksource_register_hz(cs, ch->cmt->rate);
 696         return 0;
 697 }
 698
 699 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
 700 {
 701         return container_of(ced, struct sh_cmt_channel, ced);
 702 }
 703
 704 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
 705 {
 706         sh_cmt_start(ch, FLAG_CLOCKEVENT);
 707
 708         if (periodic)
 709                 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
 710         else
 711                 sh_cmt_set_next(ch, ch->max_match_value);
 712 }
 713
 714 static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
 715 {
 716         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 717
 718         sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 719         return 0;
 720 }
 721
 722 static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
 723                                         int periodic)
 724 {
 725         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 726
 727         /* deal with old setting first */
 728         if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
 729                 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 730
 731         dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
 732                  ch->index, periodic ? "periodic" : "oneshot");
 733         sh_cmt_clock_event_start(ch, periodic);
 734         return 0;
 735 }
 736
 737 static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
 738 {
 739         return sh_cmt_clock_event_set_state(ced, 0);
 740 }
 741
 742 static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
 743 {
 744         return sh_cmt_clock_event_set_state(ced, 1);
 745 }
 746
 747 static int sh_cmt_clock_event_next(unsigned long delta,
 748                                    struct clock_event_device *ced)
 749 {
 750         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 751
 752         BUG_ON(!clockevent_state_oneshot(ced));
 753         if (likely(ch->flags & FLAG_IRQCONTEXT))
 754                 ch->next_match_value = delta - 1;
 755         else
 756                 sh_cmt_set_next(ch, delta - 1);
 757
 758         return 0;
 759 }
 760
 761 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
 762 {
 763         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 764
 765         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 766         clk_unprepare(ch->cmt->clk);
 767 }
 768
 769 static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
 770 {
 771         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 772
 773         clk_prepare(ch->cmt->clk);
 774         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 775 }
 776
 777 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
 778                                       const char *name)
 779 {
 780         struct clock_event_device *ced = &ch->ced;
 781         int irq;
 782         int ret;
 783
 784         irq = platform_get_irq(ch->cmt->pdev, ch->index);
 785         if (irq < 0)
 786                 return irq;
 787
 788         ret = request_irq(irq, sh_cmt_interrupt,
 789                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 790                           dev_name(&ch->cmt->pdev->dev), ch);
 791         if (ret) {
 792                 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
 793                         ch->index, irq);
 794                 return ret;
 795         }
 796
 797         ced->name = name;
 798         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 799         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 800         ced->rating = 125;
 801         ced->cpumask = cpu_possible_mask;
 802         ced->set_next_event = sh_cmt_clock_event_next;
 803         ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
 804         ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
 805         ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
 806         ced->suspend = sh_cmt_clock_event_suspend;
 807         ced->resume = sh_cmt_clock_event_resume;
 808
 809         /* TODO: calculate good shift from rate and counter bit width */
 810         ced->shift = 32;
 811         ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
 812         ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
 813         ced->max_delta_ticks = ch->max_match_value;
 814         ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
 815         ced->min_delta_ticks = 0x1f;
 816
 817         dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
 818                  ch->index);
 819         clockevents_register_device(ced);
 820
 821         return 0;
 822 }
 823
 824 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
 825                            bool clockevent, bool clocksource)
 826 {
 827         int ret;
 828
 829         if (clockevent) {
 830                 ch->cmt->has_clockevent = true;
 831                 ret = sh_cmt_register_clockevent(ch, name);
 832                 if (ret < 0)
 833                         return ret;
 834         }
 835
 836         if (clocksource) {
 837                 ch->cmt->has_clocksource = true;
 838                 sh_cmt_register_clocksource(ch, name);
 839         }
 840
 841         return 0;
 842 }
 843
 844 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
 845                                 unsigned int hwidx, bool clockevent,
 846                                 bool clocksource, struct sh_cmt_device *cmt)
 847 {
 848         int ret;
 849
 850         /* Skip unused channels. */
 851         if (!clockevent && !clocksource)
 852                 return 0;
 853
 854         ch->cmt = cmt;
 855         ch->index = index;
 856         ch->hwidx = hwidx;
 857         ch->timer_bit = hwidx;
 858
 859         /*
 860          * Compute the address of the channel control register block. For the
 861          * timers with a per-channel start/stop register, compute its address
 862          * as well.
 863          */
 864         switch (cmt->info->model) {
 865         case SH_CMT_16BIT:
 866                 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
 867                 break;
 868         case SH_CMT_32BIT:
 869         case SH_CMT_48BIT:
 870                 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
 871                 break;
 872         case SH_CMT0_RCAR_GEN2:
 873         case SH_CMT1_RCAR_GEN2:
 874                 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
 875                 ch->ioctrl = ch->iostart + 0x10;
 876                 ch->timer_bit = 0;
 877                 break;
 878         }
 879
 880         if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
 881                 ch->max_match_value = ~0;
 882         else
 883                 ch->max_match_value = (1 << cmt->info->width) - 1;
 884
 885         ch->match_value = ch->max_match_value;
 886         raw_spin_lock_init(&ch->lock);
 887
 888         ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
 889                               clockevent, clocksource);
 890         if (ret) {
 891                 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
 892                         ch->index);
 893                 return ret;
 894         }
 895         ch->cs_enabled = false;
 896
 897         return 0;
 898 }
 899
 900 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
 901 {
 902         struct resource *mem;
 903
 904         mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
 905         if (!mem) {
 906                 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
 907                 return -ENXIO;
 908         }
 909
 910         cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
 911         if (cmt->mapbase == NULL) {
 912                 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
 913                 return -ENXIO;
 914         }
 915
 916         return 0;
 917 }
 918
 919 static const struct platform_device_id sh_cmt_id_table[] = {
 920         { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
 921         { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
 922         { }
 923 };
 924 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
 925
 926 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
 927         {
 928                 /* deprecated, preserved for backward compatibility */
 929                 .compatible = "renesas,cmt-48",
 930                 .data = &sh_cmt_info[SH_CMT_48BIT]
 931         },
 932         {
 933                 /* deprecated, preserved for backward compatibility */
 934                 .compatible = "renesas,cmt-48-gen2",
 935                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 936         },
 937         {
 938                 .compatible = "renesas,r8a7740-cmt1",
 939                 .data = &sh_cmt_info[SH_CMT_48BIT]
 940         },
 941         {
 942                 .compatible = "renesas,sh73a0-cmt1",
 943                 .data = &sh_cmt_info[SH_CMT_48BIT]
 944         },
 945         {
 946                 .compatible = "renesas,rcar-gen2-cmt0",
 947                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 948         },
 949         {
 950                 .compatible = "renesas,rcar-gen2-cmt1",
 951                 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
 952         },
 953         {
 954                 .compatible = "renesas,rcar-gen3-cmt0",
 955                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 956         },
 957         {
 958                 .compatible = "renesas,rcar-gen3-cmt1",
 959                 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
 960         },
 961         { }
 962 };
 963 MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
 964
 965 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
 966 {
 967         unsigned int mask;
 968         unsigned int i;
 969         int ret;
 970
 971         cmt->pdev = pdev;
 972         raw_spin_lock_init(&cmt->lock);
 973
 974         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
 975                 cmt->info = of_device_get_match_data(&pdev->dev);
 976                 cmt->hw_channels = cmt->info->channels_mask;
 977         } else if (pdev->dev.platform_data) {
 978                 struct sh_timer_config *cfg = pdev->dev.platform_data;
 979                 const struct platform_device_id *id = pdev->id_entry;
 980
 981                 cmt->info = (const struct sh_cmt_info *)id->driver_data;
 982                 cmt->hw_channels = cfg->channels_mask;
 983         } else {
 984                 dev_err(&cmt->pdev->dev, "missing platform data\n");
 985                 return -ENXIO;
 986         }
 987
 988         /* Get hold of clock. */
 989         cmt->clk = clk_get(&cmt->pdev->dev, "fck");
 990         if (IS_ERR(cmt->clk)) {
 991                 dev_err(&cmt->pdev->dev, "cannot get clock\n");
 992                 return PTR_ERR(cmt->clk);
 993         }
 994
 995         ret = clk_prepare(cmt->clk);
 996         if (ret < 0)
 997                 goto err_clk_put;
 998
 999         /* Determine clock rate. */
1000         ret = clk_enable(cmt->clk);
1001         if (ret < 0)
1002                 goto err_clk_unprepare;
1003
1004         if (cmt->info->width == 16)
1005                 cmt->rate = clk_get_rate(cmt->clk) / 512;
1006         else
1007                 cmt->rate = clk_get_rate(cmt->clk) / 8;
1008
1009         clk_disable(cmt->clk);
1010
1011         /* Map the memory resource(s). */
1012         ret = sh_cmt_map_memory(cmt);
1013         if (ret < 0)
1014                 goto err_clk_unprepare;
1015
1016         /* Allocate and setup the channels. */
1017         cmt->num_channels = hweight8(cmt->hw_channels);
1018         cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1019                                 GFP_KERNEL);
1020         if (cmt->channels == NULL) {
1021                 ret = -ENOMEM;
1022                 goto err_unmap;
1023         }
1024
1025         /*
1026          * Use the first channel as a clock event device and the second channel
1027          * as a clock source. If only one channel is available use it for both.
1028          */
1029         for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1030                 unsigned int hwidx = ffs(mask) - 1;
1031                 bool clocksource = i == 1 || cmt->num_channels == 1;
1032                 bool clockevent = i == 0;
1033
1034                 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1035                                            clockevent, clocksource, cmt);
1036                 if (ret < 0)
1037                         goto err_unmap;
1038
1039                 mask &= ~(1 << hwidx);
1040         }
1041
1042         platform_set_drvdata(pdev, cmt);
1043
1044         return 0;
1045
1046 err_unmap:
1047         kfree(cmt->channels);
1048         iounmap(cmt->mapbase);
1049 err_clk_unprepare:
1050         clk_unprepare(cmt->clk);
1051 err_clk_put:
1052         clk_put(cmt->clk);
1053         return ret;
1054 }
1055
1056 static int sh_cmt_probe(struct platform_device *pdev)
1057 {
1058         struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1059         int ret;
1060
1061         if (!is_early_platform_device(pdev)) {
1062                 pm_runtime_set_active(&pdev->dev);
1063                 pm_runtime_enable(&pdev->dev);
1064         }
1065
1066         if (cmt) {
1067                 dev_info(&pdev->dev, "kept as earlytimer\n");
1068                 goto out;
1069         }
1070
1071         cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1072         if (cmt == NULL)
1073                 return -ENOMEM;
1074
1075         ret = sh_cmt_setup(cmt, pdev);
1076         if (ret) {
1077                 kfree(cmt);
1078                 pm_runtime_idle(&pdev->dev);
1079                 return ret;
1080         }
1081         if (is_early_platform_device(pdev))
1082                 return 0;
1083
1084  out:
1085         if (cmt->has_clockevent || cmt->has_clocksource)
1086                 pm_runtime_irq_safe(&pdev->dev);
1087         else
1088                 pm_runtime_idle(&pdev->dev);
1089
1090         return 0;
1091 }
1092
1093 static int sh_cmt_remove(struct platform_device *pdev)
1094 {
1095         return -EBUSY; /* cannot unregister clockevent and clocksource */
1096 }
1097
1098 static struct platform_driver sh_cmt_device_driver = {
1099         .probe          = sh_cmt_probe,
1100         .remove         = sh_cmt_remove,
1101         .driver         = {
1102                 .name   = "sh_cmt",
1103                 .of_match_table = of_match_ptr(sh_cmt_of_table),
1104         },
1105         .id_table       = sh_cmt_id_table,
1106 };
1107
1108 static int __init sh_cmt_init(void)
1109 {
1110         return platform_driver_register(&sh_cmt_device_driver);
1111 }
1112
1113 static void __exit sh_cmt_exit(void)
1114 {
1115         platform_driver_unregister(&sh_cmt_device_driver);
1116 }
1117
1118 early_platform_init("earlytimer", &sh_cmt_device_driver);
1119 subsys_initcall(sh_cmt_init);
1120 module_exit(sh_cmt_exit);
1121
1122 MODULE_AUTHOR("Magnus Damm");
1123 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1124 MODULE_LICENSE("GPL v2");