drivers/clocksource/sh_cmt.c

   1 /*
   2  * SuperH Timer Support - CMT
   3  *
   4  *  Copyright (C) 2008 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clockchips.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/ioport.h>
  25 #include <linux/irq.h>
  26 #include <linux/module.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_domain.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/slab.h>
  34 #include <linux/spinlock.h>
  35
  36 struct sh_cmt_device;
  37
  38 /*
  39  * The CMT comes in 5 different identified flavours, depending not only on the
  40  * SoC but also on the particular instance. The following table lists the main
  41  * characteristics of those flavours.
  42  *
  43  *                      16B     32B     32B-F   48B     R-Car Gen2
  44  * -----------------------------------------------------------------------------
  45  * Channels             2       1/4     1       6       2/8
  46  * Control Width        16      16      16      16      32
  47  * Counter Width        16      32      32      32/48   32/48
  48  * Shared Start/Stop    Y       Y       Y       Y       N
  49  *
  50  * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
  51  * located in the channel registers block. All other versions have a shared
  52  * start/stop register located in the global space.
  53  *
  54  * Channels are indexed from 0 to N-1 in the documentation. The channel index
  55  * infers the start/stop bit position in the control register and the channel
  56  * registers block address. Some CMT instances have a subset of channels
  57  * available, in which case the index in the documentation doesn't match the
  58  * "real" index as implemented in hardware. This is for instance the case with
  59  * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
  60  * in the documentation but using start/stop bit 5 and having its registers
  61  * block at 0x60.
  62  *
  63  * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
  64  * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
  65  */
  66
  67 enum sh_cmt_model {
  68         SH_CMT_16BIT,
  69         SH_CMT_32BIT,
  70         SH_CMT_48BIT,
  71         SH_CMT0_RCAR_GEN2,
  72         SH_CMT1_RCAR_GEN2,
  73 };
  74
  75 struct sh_cmt_info {
  76         enum sh_cmt_model model;
  77
  78         unsigned int channels_mask;
  79
  80         unsigned long width; /* 16 or 32 bit version of hardware block */
  81         u32 overflow_bit;
  82         u32 clear_bits;
  83
  84         /* callbacks for CMSTR and CMCSR access */
  85         u32 (*read_control)(void __iomem *base, unsigned long offs);
  86         void (*write_control)(void __iomem *base, unsigned long offs,
  87                               u32 value);
  88
  89         /* callbacks for CMCNT and CMCOR access */
  90         u32 (*read_count)(void __iomem *base, unsigned long offs);
  91         void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
  92 };
  93
  94 struct sh_cmt_channel {
  95         struct sh_cmt_device *cmt;
  96
  97         unsigned int index;     /* Index in the documentation */
  98         unsigned int hwidx;     /* Real hardware index */
  99
 100         void __iomem *iostart;
 101         void __iomem *ioctrl;
 102
 103         unsigned int timer_bit;
 104         unsigned long flags;
 105         u32 match_value;
 106         u32 next_match_value;
 107         u32 max_match_value;
 108         raw_spinlock_t lock;
 109         struct clock_event_device ced;
 110         struct clocksource cs;
 111         u64 total_cycles;
 112         bool cs_enabled;
 113 };
 114
 115 struct sh_cmt_device {
 116         struct platform_device *pdev;
 117
 118         const struct sh_cmt_info *info;
 119
 120         void __iomem *mapbase;
 121         struct clk *clk;
 122         unsigned long rate;
 123
 124         raw_spinlock_t lock; /* Protect the shared start/stop register */
 125
 126         struct sh_cmt_channel *channels;
 127         unsigned int num_channels;
 128         unsigned int hw_channels;
 129
 130         bool has_clockevent;
 131         bool has_clocksource;
 132 };
 133
 134 #define SH_CMT16_CMCSR_CMF              (1 << 7)
 135 #define SH_CMT16_CMCSR_CMIE             (1 << 6)
 136 #define SH_CMT16_CMCSR_CKS8             (0 << 0)
 137 #define SH_CMT16_CMCSR_CKS32            (1 << 0)
 138 #define SH_CMT16_CMCSR_CKS128           (2 << 0)
 139 #define SH_CMT16_CMCSR_CKS512           (3 << 0)
 140 #define SH_CMT16_CMCSR_CKS_MASK         (3 << 0)
 141
 142 #define SH_CMT32_CMCSR_CMF              (1 << 15)
 143 #define SH_CMT32_CMCSR_OVF              (1 << 14)
 144 #define SH_CMT32_CMCSR_WRFLG            (1 << 13)
 145 #define SH_CMT32_CMCSR_STTF             (1 << 12)
 146 #define SH_CMT32_CMCSR_STPF             (1 << 11)
 147 #define SH_CMT32_CMCSR_SSIE             (1 << 10)
 148 #define SH_CMT32_CMCSR_CMS              (1 << 9)
 149 #define SH_CMT32_CMCSR_CMM              (1 << 8)
 150 #define SH_CMT32_CMCSR_CMTOUT_IE        (1 << 7)
 151 #define SH_CMT32_CMCSR_CMR_NONE         (0 << 4)
 152 #define SH_CMT32_CMCSR_CMR_DMA          (1 << 4)
 153 #define SH_CMT32_CMCSR_CMR_IRQ          (2 << 4)
 154 #define SH_CMT32_CMCSR_CMR_MASK         (3 << 4)
 155 #define SH_CMT32_CMCSR_DBGIVD           (1 << 3)
 156 #define SH_CMT32_CMCSR_CKS_RCLK8        (4 << 0)
 157 #define SH_CMT32_CMCSR_CKS_RCLK32       (5 << 0)
 158 #define SH_CMT32_CMCSR_CKS_RCLK128      (6 << 0)
 159 #define SH_CMT32_CMCSR_CKS_RCLK1        (7 << 0)
 160 #define SH_CMT32_CMCSR_CKS_MASK         (7 << 0)
 161
 162 static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
 163 {
 164         return ioread16(base + (offs << 1));
 165 }
 166
 167 static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
 168 {
 169         return ioread32(base + (offs << 2));
 170 }
 171
 172 static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
 173 {
 174         iowrite16(value, base + (offs << 1));
 175 }
 176
 177 static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
 178 {
 179         iowrite32(value, base + (offs << 2));
 180 }
 181
 182 static const struct sh_cmt_info sh_cmt_info[] = {
 183         [SH_CMT_16BIT] = {
 184                 .model = SH_CMT_16BIT,
 185                 .width = 16,
 186                 .overflow_bit = SH_CMT16_CMCSR_CMF,
 187                 .clear_bits = ~SH_CMT16_CMCSR_CMF,
 188                 .read_control = sh_cmt_read16,
 189                 .write_control = sh_cmt_write16,
 190                 .read_count = sh_cmt_read16,
 191                 .write_count = sh_cmt_write16,
 192         },
 193         [SH_CMT_32BIT] = {
 194                 .model = SH_CMT_32BIT,
 195                 .width = 32,
 196                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 197                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 198                 .read_control = sh_cmt_read16,
 199                 .write_control = sh_cmt_write16,
 200                 .read_count = sh_cmt_read32,
 201                 .write_count = sh_cmt_write32,
 202         },
 203         [SH_CMT_48BIT] = {
 204                 .model = SH_CMT_48BIT,
 205                 .channels_mask = 0x3f,
 206                 .width = 32,
 207                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 208                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 209                 .read_control = sh_cmt_read32,
 210                 .write_control = sh_cmt_write32,
 211                 .read_count = sh_cmt_read32,
 212                 .write_count = sh_cmt_write32,
 213         },
 214         [SH_CMT0_RCAR_GEN2] = {
 215                 .model = SH_CMT0_RCAR_GEN2,
 216                 .channels_mask = 0x60,
 217                 .width = 32,
 218                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 219                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 220                 .read_control = sh_cmt_read32,
 221                 .write_control = sh_cmt_write32,
 222                 .read_count = sh_cmt_read32,
 223                 .write_count = sh_cmt_write32,
 224         },
 225         [SH_CMT1_RCAR_GEN2] = {
 226                 .model = SH_CMT1_RCAR_GEN2,
 227                 .channels_mask = 0xff,
 228                 .width = 32,
 229                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 230                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 231                 .read_control = sh_cmt_read32,
 232                 .write_control = sh_cmt_write32,
 233                 .read_count = sh_cmt_read32,
 234                 .write_count = sh_cmt_write32,
 235         },
 236 };
 237
 238 #define CMCSR 0 /* channel register */
 239 #define CMCNT 1 /* channel register */
 240 #define CMCOR 2 /* channel register */
 241
 242 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
 243 {
 244         if (ch->iostart)
 245                 return ch->cmt->info->read_control(ch->iostart, 0);
 246         else
 247                 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
 248 }
 249
 250 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
 251 {
 252         if (ch->iostart)
 253                 ch->cmt->info->write_control(ch->iostart, 0, value);
 254         else
 255                 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
 256 }
 257
 258 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
 259 {
 260         return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
 261 }
 262
 263 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
 264 {
 265         ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
 266 }
 267
 268 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
 269 {
 270         return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
 271 }
 272
 273 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
 274 {
 275         ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
 276 }
 277
 278 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
 279 {
 280         ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
 281 }
 282
 283 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
 284 {
 285         u32 v1, v2, v3;
 286         u32 o1, o2;
 287
 288         o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 289
 290         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
 291         do {
 292                 o2 = o1;
 293                 v1 = sh_cmt_read_cmcnt(ch);
 294                 v2 = sh_cmt_read_cmcnt(ch);
 295                 v3 = sh_cmt_read_cmcnt(ch);
 296                 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 297         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
 298                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 299
 300         *has_wrapped = o1;
 301         return v2;
 302 }
 303
 304 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
 305 {
 306         unsigned long flags;
 307         u32 value;
 308
 309         /* start stop register shared by multiple timer channels */
 310         raw_spin_lock_irqsave(&ch->cmt->lock, flags);
 311         value = sh_cmt_read_cmstr(ch);
 312
 313         if (start)
 314                 value |= 1 << ch->timer_bit;
 315         else
 316                 value &= ~(1 << ch->timer_bit);
 317
 318         sh_cmt_write_cmstr(ch, value);
 319         raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
 320 }
 321
 322 static int sh_cmt_enable(struct sh_cmt_channel *ch)
 323 {
 324         int k, ret;
 325
 326         pm_runtime_get_sync(&ch->cmt->pdev->dev);
 327         dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
 328
 329         /* enable clock */
 330         ret = clk_enable(ch->cmt->clk);
 331         if (ret) {
 332                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
 333                         ch->index);
 334                 goto err0;
 335         }
 336
 337         /* make sure channel is disabled */
 338         sh_cmt_start_stop_ch(ch, 0);
 339
 340         /* configure channel, periodic mode and maximum timeout */
 341         if (ch->cmt->info->width == 16) {
 342                 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
 343                                    SH_CMT16_CMCSR_CKS512);
 344         } else {
 345                 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
 346                                    SH_CMT32_CMCSR_CMTOUT_IE |
 347                                    SH_CMT32_CMCSR_CMR_IRQ |
 348                                    SH_CMT32_CMCSR_CKS_RCLK8);
 349         }
 350
 351         sh_cmt_write_cmcor(ch, 0xffffffff);
 352         sh_cmt_write_cmcnt(ch, 0);
 353
 354         /*
 355          * According to the sh73a0 user's manual, as CMCNT can be operated
 356          * only by the RCLK (Pseudo 32 KHz), there's one restriction on
 357          * modifying CMCNT register; two RCLK cycles are necessary before
 358          * this register is either read or any modification of the value
 359          * it holds is reflected in the LSI's actual operation.
 360          *
 361          * While at it, we're supposed to clear out the CMCNT as of this
 362          * moment, so make sure it's processed properly here.  This will
 363          * take RCLKx2 at maximum.
 364          */
 365         for (k = 0; k < 100; k++) {
 366                 if (!sh_cmt_read_cmcnt(ch))
 367                         break;
 368                 udelay(1);
 369         }
 370
 371         if (sh_cmt_read_cmcnt(ch)) {
 372                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
 373                         ch->index);
 374                 ret = -ETIMEDOUT;
 375                 goto err1;
 376         }
 377
 378         /* enable channel */
 379         sh_cmt_start_stop_ch(ch, 1);
 380         return 0;
 381  err1:
 382         /* stop clock */
 383         clk_disable(ch->cmt->clk);
 384
 385  err0:
 386         return ret;
 387 }
 388
 389 static void sh_cmt_disable(struct sh_cmt_channel *ch)
 390 {
 391         /* disable channel */
 392         sh_cmt_start_stop_ch(ch, 0);
 393
 394         /* disable interrupts in CMT block */
 395         sh_cmt_write_cmcsr(ch, 0);
 396
 397         /* stop clock */
 398         clk_disable(ch->cmt->clk);
 399
 400         dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
 401         pm_runtime_put(&ch->cmt->pdev->dev);
 402 }
 403
 404 /* private flags */
 405 #define FLAG_CLOCKEVENT (1 << 0)
 406 #define FLAG_CLOCKSOURCE (1 << 1)
 407 #define FLAG_REPROGRAM (1 << 2)
 408 #define FLAG_SKIPEVENT (1 << 3)
 409 #define FLAG_IRQCONTEXT (1 << 4)
 410
 411 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
 412                                               int absolute)
 413 {
 414         u32 value = ch->next_match_value;
 415         u32 new_match;
 416         u32 delay = 0;
 417         u32 now = 0;
 418         u32 has_wrapped;
 419
 420         now = sh_cmt_get_counter(ch, &has_wrapped);
 421         ch->flags |= FLAG_REPROGRAM; /* force reprogram */
 422
 423         if (has_wrapped) {
 424                 /* we're competing with the interrupt handler.
 425                  *  -> let the interrupt handler reprogram the timer.
 426                  *  -> interrupt number two handles the event.
 427                  */
 428                 ch->flags |= FLAG_SKIPEVENT;
 429                 return;
 430         }
 431
 432         if (absolute)
 433                 now = 0;
 434
 435         do {
 436                 /* reprogram the timer hardware,
 437                  * but don't save the new match value yet.
 438                  */
 439                 new_match = now + value + delay;
 440                 if (new_match > ch->max_match_value)
 441                         new_match = ch->max_match_value;
 442
 443                 sh_cmt_write_cmcor(ch, new_match);
 444
 445                 now = sh_cmt_get_counter(ch, &has_wrapped);
 446                 if (has_wrapped && (new_match > ch->match_value)) {
 447                         /* we are changing to a greater match value,
 448                          * so this wrap must be caused by the counter
 449                          * matching the old value.
 450                          * -> first interrupt reprograms the timer.
 451                          * -> interrupt number two handles the event.
 452                          */
 453                         ch->flags |= FLAG_SKIPEVENT;
 454                         break;
 455                 }
 456
 457                 if (has_wrapped) {
 458                         /* we are changing to a smaller match value,
 459                          * so the wrap must be caused by the counter
 460                          * matching the new value.
 461                          * -> save programmed match value.
 462                          * -> let isr handle the event.
 463                          */
 464                         ch->match_value = new_match;
 465                         break;
 466                 }
 467
 468                 /* be safe: verify hardware settings */
 469                 if (now < new_match) {
 470                         /* timer value is below match value, all good.
 471                          * this makes sure we won't miss any match events.
 472                          * -> save programmed match value.
 473                          * -> let isr handle the event.
 474                          */
 475                         ch->match_value = new_match;
 476                         break;
 477                 }
 478
 479                 /* the counter has reached a value greater
 480                  * than our new match value. and since the
 481                  * has_wrapped flag isn't set we must have
 482                  * programmed a too close event.
 483                  * -> increase delay and retry.
 484                  */
 485                 if (delay)
 486                         delay <<= 1;
 487                 else
 488                         delay = 1;
 489
 490                 if (!delay)
 491                         dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
 492                                  ch->index);
 493
 494         } while (delay);
 495 }
 496
 497 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 498 {
 499         if (delta > ch->max_match_value)
 500                 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
 501                          ch->index);
 502
 503         ch->next_match_value = delta;
 504         sh_cmt_clock_event_program_verify(ch, 0);
 505 }
 506
 507 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 508 {
 509         unsigned long flags;
 510
 511         raw_spin_lock_irqsave(&ch->lock, flags);
 512         __sh_cmt_set_next(ch, delta);
 513         raw_spin_unlock_irqrestore(&ch->lock, flags);
 514 }
 515
 516 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
 517 {
 518         struct sh_cmt_channel *ch = dev_id;
 519
 520         /* clear flags */
 521         sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
 522                            ch->cmt->info->clear_bits);
 523
 524         /* update clock source counter to begin with if enabled
 525          * the wrap flag should be cleared by the timer specific
 526          * isr before we end up here.
 527          */
 528         if (ch->flags & FLAG_CLOCKSOURCE)
 529                 ch->total_cycles += ch->match_value + 1;
 530
 531         if (!(ch->flags & FLAG_REPROGRAM))
 532                 ch->next_match_value = ch->max_match_value;
 533
 534         ch->flags |= FLAG_IRQCONTEXT;
 535
 536         if (ch->flags & FLAG_CLOCKEVENT) {
 537                 if (!(ch->flags & FLAG_SKIPEVENT)) {
 538                         if (clockevent_state_oneshot(&ch->ced)) {
 539                                 ch->next_match_value = ch->max_match_value;
 540                                 ch->flags |= FLAG_REPROGRAM;
 541                         }
 542
 543                         ch->ced.event_handler(&ch->ced);
 544                 }
 545         }
 546
 547         ch->flags &= ~FLAG_SKIPEVENT;
 548
 549         if (ch->flags & FLAG_REPROGRAM) {
 550                 ch->flags &= ~FLAG_REPROGRAM;
 551                 sh_cmt_clock_event_program_verify(ch, 1);
 552
 553                 if (ch->flags & FLAG_CLOCKEVENT)
 554                         if ((clockevent_state_shutdown(&ch->ced))
 555                             || (ch->match_value == ch->next_match_value))
 556                                 ch->flags &= ~FLAG_REPROGRAM;
 557         }
 558
 559         ch->flags &= ~FLAG_IRQCONTEXT;
 560
 561         return IRQ_HANDLED;
 562 }
 563
 564 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
 565 {
 566         int ret = 0;
 567         unsigned long flags;
 568
 569         raw_spin_lock_irqsave(&ch->lock, flags);
 570
 571         if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 572                 ret = sh_cmt_enable(ch);
 573
 574         if (ret)
 575                 goto out;
 576         ch->flags |= flag;
 577
 578         /* setup timeout if no clockevent */
 579         if (ch->cmt->num_channels == 1 &&
 580             flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT)))
 581                 __sh_cmt_set_next(ch, ch->max_match_value);
 582  out:
 583         raw_spin_unlock_irqrestore(&ch->lock, flags);
 584
 585         return ret;
 586 }
 587
 588 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
 589 {
 590         unsigned long flags;
 591         unsigned long f;
 592
 593         raw_spin_lock_irqsave(&ch->lock, flags);
 594
 595         f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
 596         ch->flags &= ~flag;
 597
 598         if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 599                 sh_cmt_disable(ch);
 600
 601         /* adjust the timeout to maximum if only clocksource left */
 602         if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
 603                 __sh_cmt_set_next(ch, ch->max_match_value);
 604
 605         raw_spin_unlock_irqrestore(&ch->lock, flags);
 606 }
 607
 608 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
 609 {
 610         return container_of(cs, struct sh_cmt_channel, cs);
 611 }
 612
 613 static u64 sh_cmt_clocksource_read(struct clocksource *cs)
 614 {
 615         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 616         u32 has_wrapped;
 617
 618         if (ch->cmt->num_channels == 1) {
 619                 unsigned long flags;
 620                 u64 value;
 621                 u32 raw;
 622
 623                 raw_spin_lock_irqsave(&ch->lock, flags);
 624                 value = ch->total_cycles;
 625                 raw = sh_cmt_get_counter(ch, &has_wrapped);
 626
 627                 if (unlikely(has_wrapped))
 628                         raw += ch->match_value + 1;
 629                 raw_spin_unlock_irqrestore(&ch->lock, flags);
 630
 631                 return value + raw;
 632         }
 633
 634         return sh_cmt_get_counter(ch, &has_wrapped);
 635 }
 636
 637 static int sh_cmt_clocksource_enable(struct clocksource *cs)
 638 {
 639         int ret;
 640         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 641
 642         WARN_ON(ch->cs_enabled);
 643
 644         ch->total_cycles = 0;
 645
 646         ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 647         if (!ret)
 648                 ch->cs_enabled = true;
 649
 650         return ret;
 651 }
 652
 653 static void sh_cmt_clocksource_disable(struct clocksource *cs)
 654 {
 655         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 656
 657         WARN_ON(!ch->cs_enabled);
 658
 659         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 660         ch->cs_enabled = false;
 661 }
 662
 663 static void sh_cmt_clocksource_suspend(struct clocksource *cs)
 664 {
 665         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 666
 667         if (!ch->cs_enabled)
 668                 return;
 669
 670         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 671         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 672 }
 673
 674 static void sh_cmt_clocksource_resume(struct clocksource *cs)
 675 {
 676         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 677
 678         if (!ch->cs_enabled)
 679                 return;
 680
 681         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 682         sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 683 }
 684
 685 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
 686                                        const char *name)
 687 {
 688         struct clocksource *cs = &ch->cs;
 689
 690         cs->name = name;
 691         cs->rating = 125;
 692         cs->read = sh_cmt_clocksource_read;
 693         cs->enable = sh_cmt_clocksource_enable;
 694         cs->disable = sh_cmt_clocksource_disable;
 695         cs->suspend = sh_cmt_clocksource_suspend;
 696         cs->resume = sh_cmt_clocksource_resume;
 697         cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width);
 698         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 699
 700         dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
 701                  ch->index);
 702
 703         clocksource_register_hz(cs, ch->cmt->rate);
 704         return 0;
 705 }
 706
 707 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
 708 {
 709         return container_of(ced, struct sh_cmt_channel, ced);
 710 }
 711
 712 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
 713 {
 714         sh_cmt_start(ch, FLAG_CLOCKEVENT);
 715
 716         if (periodic)
 717                 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
 718         else
 719                 sh_cmt_set_next(ch, ch->max_match_value);
 720 }
 721
 722 static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
 723 {
 724         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 725
 726         sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 727         return 0;
 728 }
 729
 730 static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
 731                                         int periodic)
 732 {
 733         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 734
 735         /* deal with old setting first */
 736         if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
 737                 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 738
 739         dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
 740                  ch->index, periodic ? "periodic" : "oneshot");
 741         sh_cmt_clock_event_start(ch, periodic);
 742         return 0;
 743 }
 744
 745 static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
 746 {
 747         return sh_cmt_clock_event_set_state(ced, 0);
 748 }
 749
 750 static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
 751 {
 752         return sh_cmt_clock_event_set_state(ced, 1);
 753 }
 754
 755 static int sh_cmt_clock_event_next(unsigned long delta,
 756                                    struct clock_event_device *ced)
 757 {
 758         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 759
 760         BUG_ON(!clockevent_state_oneshot(ced));
 761         if (likely(ch->flags & FLAG_IRQCONTEXT))
 762                 ch->next_match_value = delta - 1;
 763         else
 764                 sh_cmt_set_next(ch, delta - 1);
 765
 766         return 0;
 767 }
 768
 769 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
 770 {
 771         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 772
 773         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 774         clk_unprepare(ch->cmt->clk);
 775 }
 776
 777 static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
 778 {
 779         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 780
 781         clk_prepare(ch->cmt->clk);
 782         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 783 }
 784
 785 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
 786                                       const char *name)
 787 {
 788         struct clock_event_device *ced = &ch->ced;
 789         int irq;
 790         int ret;
 791
 792         irq = platform_get_irq(ch->cmt->pdev, ch->index);
 793         if (irq < 0) {
 794                 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
 795                         ch->index);
 796                 return irq;
 797         }
 798
 799         ret = request_irq(irq, sh_cmt_interrupt,
 800                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 801                           dev_name(&ch->cmt->pdev->dev), ch);
 802         if (ret) {
 803                 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
 804                         ch->index, irq);
 805                 return ret;
 806         }
 807
 808         ced->name = name;
 809         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 810         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 811         ced->rating = 125;
 812         ced->cpumask = cpu_possible_mask;
 813         ced->set_next_event = sh_cmt_clock_event_next;
 814         ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
 815         ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
 816         ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
 817         ced->suspend = sh_cmt_clock_event_suspend;
 818         ced->resume = sh_cmt_clock_event_resume;
 819
 820         /* TODO: calculate good shift from rate and counter bit width */
 821         ced->shift = 32;
 822         ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
 823         ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
 824         ced->max_delta_ticks = ch->max_match_value;
 825         ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
 826         ced->min_delta_ticks = 0x1f;
 827
 828         dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
 829                  ch->index);
 830         clockevents_register_device(ced);
 831
 832         return 0;
 833 }
 834
 835 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
 836                            bool clockevent, bool clocksource)
 837 {
 838         int ret;
 839
 840         if (clockevent) {
 841                 ch->cmt->has_clockevent = true;
 842                 ret = sh_cmt_register_clockevent(ch, name);
 843                 if (ret < 0)
 844                         return ret;
 845         }
 846
 847         if (clocksource) {
 848                 ch->cmt->has_clocksource = true;
 849                 sh_cmt_register_clocksource(ch, name);
 850         }
 851
 852         return 0;
 853 }
 854
 855 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
 856                                 unsigned int hwidx, bool clockevent,
 857                                 bool clocksource, struct sh_cmt_device *cmt)
 858 {
 859         int ret;
 860
 861         /* Skip unused channels. */
 862         if (!clockevent && !clocksource)
 863                 return 0;
 864
 865         ch->cmt = cmt;
 866         ch->index = index;
 867         ch->hwidx = hwidx;
 868         ch->timer_bit = hwidx;
 869
 870         /*
 871          * Compute the address of the channel control register block. For the
 872          * timers with a per-channel start/stop register, compute its address
 873          * as well.
 874          */
 875         switch (cmt->info->model) {
 876         case SH_CMT_16BIT:
 877                 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
 878                 break;
 879         case SH_CMT_32BIT:
 880         case SH_CMT_48BIT:
 881                 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
 882                 break;
 883         case SH_CMT0_RCAR_GEN2:
 884         case SH_CMT1_RCAR_GEN2:
 885                 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
 886                 ch->ioctrl = ch->iostart + 0x10;
 887                 ch->timer_bit = 0;
 888                 break;
 889         }
 890
 891         if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
 892                 ch->max_match_value = ~0;
 893         else
 894                 ch->max_match_value = (1 << cmt->info->width) - 1;
 895
 896         ch->match_value = ch->max_match_value;
 897         raw_spin_lock_init(&ch->lock);
 898
 899         ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
 900                               clockevent, clocksource);
 901         if (ret) {
 902                 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
 903                         ch->index);
 904                 return ret;
 905         }
 906         ch->cs_enabled = false;
 907
 908         return 0;
 909 }
 910
 911 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
 912 {
 913         struct resource *mem;
 914
 915         mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
 916         if (!mem) {
 917                 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
 918                 return -ENXIO;
 919         }
 920
 921         cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
 922         if (cmt->mapbase == NULL) {
 923                 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
 924                 return -ENXIO;
 925         }
 926
 927         return 0;
 928 }
 929
 930 static const struct platform_device_id sh_cmt_id_table[] = {
 931         { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
 932         { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
 933         { }
 934 };
 935 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
 936
 937 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
 938         { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
 939         {
 940                 /* deprecated, preserved for backward compatibility */
 941                 .compatible = "renesas,cmt-48-gen2",
 942                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 943         },
 944         { .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
 945         { .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] },
 946         { }
 947 };
 948 MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
 949
 950 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
 951 {
 952         unsigned int mask;
 953         unsigned int i;
 954         int ret;
 955
 956         cmt->pdev = pdev;
 957         raw_spin_lock_init(&cmt->lock);
 958
 959         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
 960                 cmt->info = of_device_get_match_data(&pdev->dev);
 961                 cmt->hw_channels = cmt->info->channels_mask;
 962         } else if (pdev->dev.platform_data) {
 963                 struct sh_timer_config *cfg = pdev->dev.platform_data;
 964                 const struct platform_device_id *id = pdev->id_entry;
 965
 966                 cmt->info = (const struct sh_cmt_info *)id->driver_data;
 967                 cmt->hw_channels = cfg->channels_mask;
 968         } else {
 969                 dev_err(&cmt->pdev->dev, "missing platform data\n");
 970                 return -ENXIO;
 971         }
 972
 973         /* Get hold of clock. */
 974         cmt->clk = clk_get(&cmt->pdev->dev, "fck");
 975         if (IS_ERR(cmt->clk)) {
 976                 dev_err(&cmt->pdev->dev, "cannot get clock\n");
 977                 return PTR_ERR(cmt->clk);
 978         }
 979
 980         ret = clk_prepare(cmt->clk);
 981         if (ret < 0)
 982                 goto err_clk_put;
 983
 984         /* Determine clock rate. */
 985         ret = clk_enable(cmt->clk);
 986         if (ret < 0)
 987                 goto err_clk_unprepare;
 988
 989         if (cmt->info->width == 16)
 990                 cmt->rate = clk_get_rate(cmt->clk) / 512;
 991         else
 992                 cmt->rate = clk_get_rate(cmt->clk) / 8;
 993
 994         clk_disable(cmt->clk);
 995
 996         /* Map the memory resource(s). */
 997         ret = sh_cmt_map_memory(cmt);
 998         if (ret < 0)
 999                 goto err_clk_unprepare;
1000
1001         /* Allocate and setup the channels. */
1002         cmt->num_channels = hweight8(cmt->hw_channels);
1003         cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1004                                 GFP_KERNEL);
1005         if (cmt->channels == NULL) {
1006                 ret = -ENOMEM;
1007                 goto err_unmap;
1008         }
1009
1010         /*
1011          * Use the first channel as a clock event device and the second channel
1012          * as a clock source. If only one channel is available use it for both.
1013          */
1014         for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1015                 unsigned int hwidx = ffs(mask) - 1;
1016                 bool clocksource = i == 1 || cmt->num_channels == 1;
1017                 bool clockevent = i == 0;
1018
1019                 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1020                                            clockevent, clocksource, cmt);
1021                 if (ret < 0)
1022                         goto err_unmap;
1023
1024                 mask &= ~(1 << hwidx);
1025         }
1026
1027         platform_set_drvdata(pdev, cmt);
1028
1029         return 0;
1030
1031 err_unmap:
1032         kfree(cmt->channels);
1033         iounmap(cmt->mapbase);
1034 err_clk_unprepare:
1035         clk_unprepare(cmt->clk);
1036 err_clk_put:
1037         clk_put(cmt->clk);
1038         return ret;
1039 }
1040
1041 static int sh_cmt_probe(struct platform_device *pdev)
1042 {
1043         struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1044         int ret;
1045
1046         if (!is_early_platform_device(pdev)) {
1047                 pm_runtime_set_active(&pdev->dev);
1048                 pm_runtime_enable(&pdev->dev);
1049         }
1050
1051         if (cmt) {
1052                 dev_info(&pdev->dev, "kept as earlytimer\n");
1053                 goto out;
1054         }
1055
1056         cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1057         if (cmt == NULL)
1058                 return -ENOMEM;
1059
1060         ret = sh_cmt_setup(cmt, pdev);
1061         if (ret) {
1062                 kfree(cmt);
1063                 pm_runtime_idle(&pdev->dev);
1064                 return ret;
1065         }
1066         if (is_early_platform_device(pdev))
1067                 return 0;
1068
1069  out:
1070         if (cmt->has_clockevent || cmt->has_clocksource)
1071                 pm_runtime_irq_safe(&pdev->dev);
1072         else
1073                 pm_runtime_idle(&pdev->dev);
1074
1075         return 0;
1076 }
1077
1078 static int sh_cmt_remove(struct platform_device *pdev)
1079 {
1080         return -EBUSY; /* cannot unregister clockevent and clocksource */
1081 }
1082
1083 static struct platform_driver sh_cmt_device_driver = {
1084         .probe          = sh_cmt_probe,
1085         .remove         = sh_cmt_remove,
1086         .driver         = {
1087                 .name   = "sh_cmt",
1088                 .of_match_table = of_match_ptr(sh_cmt_of_table),
1089         },
1090         .id_table       = sh_cmt_id_table,
1091 };
1092
1093 static int __init sh_cmt_init(void)
1094 {
1095         return platform_driver_register(&sh_cmt_device_driver);
1096 }
1097
1098 static void __exit sh_cmt_exit(void)
1099 {
1100         platform_driver_unregister(&sh_cmt_device_driver);
1101 }
1102
1103 early_platform_init("earlytimer", &sh_cmt_device_driver);
1104 subsys_initcall(sh_cmt_init);
1105 module_exit(sh_cmt_exit);
1106
1107 MODULE_AUTHOR("Magnus Damm");
1108 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1109 MODULE_LICENSE("GPL v2");