drivers/clocksource/sh_cmt.c

   1 /*
   2  * SuperH Timer Support - CMT
   3  *
   4  *  Copyright (C) 2008 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clockchips.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/ioport.h>
  25 #include <linux/irq.h>
  26 #include <linux/module.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_domain.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/slab.h>
  34 #include <linux/spinlock.h>
  35
  36 struct sh_cmt_device;
  37
  38 /*
  39  * The CMT comes in 5 different identified flavours, depending not only on the
  40  * SoC but also on the particular instance. The following table lists the main
  41  * characteristics of those flavours.
  42  *
  43  *                      16B     32B     32B-F   48B     R-Car Gen2
  44  * -----------------------------------------------------------------------------
  45  * Channels             2       1/4     1       6       2/8
  46  * Control Width        16      16      16      16      32
  47  * Counter Width        16      32      32      32/48   32/48
  48  * Shared Start/Stop    Y       Y       Y       Y       N
  49  *
  50  * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
  51  * located in the channel registers block. All other versions have a shared
  52  * start/stop register located in the global space.
  53  *
  54  * Channels are indexed from 0 to N-1 in the documentation. The channel index
  55  * infers the start/stop bit position in the control register and the channel
  56  * registers block address. Some CMT instances have a subset of channels
  57  * available, in which case the index in the documentation doesn't match the
  58  * "real" index as implemented in hardware. This is for instance the case with
  59  * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
  60  * in the documentation but using start/stop bit 5 and having its registers
  61  * block at 0x60.
  62  *
  63  * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
  64  * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
  65  */
  66
  67 enum sh_cmt_model {
  68         SH_CMT_16BIT,
  69         SH_CMT_32BIT,
  70         SH_CMT_48BIT,
  71         SH_CMT0_RCAR_GEN2,
  72         SH_CMT1_RCAR_GEN2,
  73 };
  74
  75 struct sh_cmt_info {
  76         enum sh_cmt_model model;
  77
  78         unsigned int channels_mask;
  79
  80         unsigned long width; /* 16 or 32 bit version of hardware block */
  81         u32 overflow_bit;
  82         u32 clear_bits;
  83
  84         /* callbacks for CMSTR and CMCSR access */
  85         u32 (*read_control)(void __iomem *base, unsigned long offs);
  86         void (*write_control)(void __iomem *base, unsigned long offs,
  87                               u32 value);
  88
  89         /* callbacks for CMCNT and CMCOR access */
  90         u32 (*read_count)(void __iomem *base, unsigned long offs);
  91         void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
  92 };
  93
  94 struct sh_cmt_channel {
  95         struct sh_cmt_device *cmt;
  96
  97         unsigned int index;     /* Index in the documentation */
  98         unsigned int hwidx;     /* Real hardware index */
  99
 100         void __iomem *iostart;
 101         void __iomem *ioctrl;
 102
 103         unsigned int timer_bit;
 104         unsigned long flags;
 105         u32 match_value;
 106         u32 next_match_value;
 107         u32 max_match_value;
 108         raw_spinlock_t lock;
 109         struct clock_event_device ced;
 110         struct clocksource cs;
 111         u64 total_cycles;
 112         bool cs_enabled;
 113 };
 114
 115 struct sh_cmt_device {
 116         struct platform_device *pdev;
 117
 118         const struct sh_cmt_info *info;
 119
 120         void __iomem *mapbase;
 121         struct clk *clk;
 122         unsigned long rate;
 123
 124         raw_spinlock_t lock; /* Protect the shared start/stop register */
 125
 126         struct sh_cmt_channel *channels;
 127         unsigned int num_channels;
 128         unsigned int hw_channels;
 129
 130         bool has_clockevent;
 131         bool has_clocksource;
 132 };
 133
 134 #define SH_CMT16_CMCSR_CMF              (1 << 7)
 135 #define SH_CMT16_CMCSR_CMIE             (1 << 6)
 136 #define SH_CMT16_CMCSR_CKS8             (0 << 0)
 137 #define SH_CMT16_CMCSR_CKS32            (1 << 0)
 138 #define SH_CMT16_CMCSR_CKS128           (2 << 0)
 139 #define SH_CMT16_CMCSR_CKS512           (3 << 0)
 140 #define SH_CMT16_CMCSR_CKS_MASK         (3 << 0)
 141
 142 #define SH_CMT32_CMCSR_CMF              (1 << 15)
 143 #define SH_CMT32_CMCSR_OVF              (1 << 14)
 144 #define SH_CMT32_CMCSR_WRFLG            (1 << 13)
 145 #define SH_CMT32_CMCSR_STTF             (1 << 12)
 146 #define SH_CMT32_CMCSR_STPF             (1 << 11)
 147 #define SH_CMT32_CMCSR_SSIE             (1 << 10)
 148 #define SH_CMT32_CMCSR_CMS              (1 << 9)
 149 #define SH_CMT32_CMCSR_CMM              (1 << 8)
 150 #define SH_CMT32_CMCSR_CMTOUT_IE        (1 << 7)
 151 #define SH_CMT32_CMCSR_CMR_NONE         (0 << 4)
 152 #define SH_CMT32_CMCSR_CMR_DMA          (1 << 4)
 153 #define SH_CMT32_CMCSR_CMR_IRQ          (2 << 4)
 154 #define SH_CMT32_CMCSR_CMR_MASK         (3 << 4)
 155 #define SH_CMT32_CMCSR_DBGIVD           (1 << 3)
 156 #define SH_CMT32_CMCSR_CKS_RCLK8        (4 << 0)
 157 #define SH_CMT32_CMCSR_CKS_RCLK32       (5 << 0)
 158 #define SH_CMT32_CMCSR_CKS_RCLK128      (6 << 0)
 159 #define SH_CMT32_CMCSR_CKS_RCLK1        (7 << 0)
 160 #define SH_CMT32_CMCSR_CKS_MASK         (7 << 0)
 161
 162 static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
 163 {
 164         return ioread16(base + (offs << 1));
 165 }
 166
 167 static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
 168 {
 169         return ioread32(base + (offs << 2));
 170 }
 171
 172 static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
 173 {
 174         iowrite16(value, base + (offs << 1));
 175 }
 176
 177 static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
 178 {
 179         iowrite32(value, base + (offs << 2));
 180 }
 181
 182 static const struct sh_cmt_info sh_cmt_info[] = {
 183         [SH_CMT_16BIT] = {
 184                 .model = SH_CMT_16BIT,
 185                 .width = 16,
 186                 .overflow_bit = SH_CMT16_CMCSR_CMF,
 187                 .clear_bits = ~SH_CMT16_CMCSR_CMF,
 188                 .read_control = sh_cmt_read16,
 189                 .write_control = sh_cmt_write16,
 190                 .read_count = sh_cmt_read16,
 191                 .write_count = sh_cmt_write16,
 192         },
 193         [SH_CMT_32BIT] = {
 194                 .model = SH_CMT_32BIT,
 195                 .width = 32,
 196                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 197                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 198                 .read_control = sh_cmt_read16,
 199                 .write_control = sh_cmt_write16,
 200                 .read_count = sh_cmt_read32,
 201                 .write_count = sh_cmt_write32,
 202         },
 203         [SH_CMT_48BIT] = {
 204                 .model = SH_CMT_48BIT,
 205                 .channels_mask = 0x3f,
 206                 .width = 32,
 207                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 208                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 209                 .read_control = sh_cmt_read32,
 210                 .write_control = sh_cmt_write32,
 211                 .read_count = sh_cmt_read32,
 212                 .write_count = sh_cmt_write32,
 213         },
 214         [SH_CMT0_RCAR_GEN2] = {
 215                 .model = SH_CMT0_RCAR_GEN2,
 216                 .channels_mask = 0x60,
 217                 .width = 32,
 218                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 219                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 220                 .read_control = sh_cmt_read32,
 221                 .write_control = sh_cmt_write32,
 222                 .read_count = sh_cmt_read32,
 223                 .write_count = sh_cmt_write32,
 224         },
 225         [SH_CMT1_RCAR_GEN2] = {
 226                 .model = SH_CMT1_RCAR_GEN2,
 227                 .channels_mask = 0xff,
 228                 .width = 32,
 229                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 230                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 231                 .read_control = sh_cmt_read32,
 232                 .write_control = sh_cmt_write32,
 233                 .read_count = sh_cmt_read32,
 234                 .write_count = sh_cmt_write32,
 235         },
 236 };
 237
 238 #define CMCSR 0 /* channel register */
 239 #define CMCNT 1 /* channel register */
 240 #define CMCOR 2 /* channel register */
 241
 242 #define CMCLKE  0x1000  /* CLK Enable Register (R-Car Gen2) */
 243
 244 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
 245 {
 246         if (ch->iostart)
 247                 return ch->cmt->info->read_control(ch->iostart, 0);
 248         else
 249                 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
 250 }
 251
 252 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
 253 {
 254         if (ch->iostart)
 255                 ch->cmt->info->write_control(ch->iostart, 0, value);
 256         else
 257                 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
 258 }
 259
 260 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
 261 {
 262         return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
 263 }
 264
 265 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
 266 {
 267         ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
 268 }
 269
 270 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
 271 {
 272         return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
 273 }
 274
 275 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
 276 {
 277         ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
 278 }
 279
 280 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
 281 {
 282         ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
 283 }
 284
 285 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
 286 {
 287         u32 v1, v2, v3;
 288         u32 o1, o2;
 289
 290         o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 291
 292         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
 293         do {
 294                 o2 = o1;
 295                 v1 = sh_cmt_read_cmcnt(ch);
 296                 v2 = sh_cmt_read_cmcnt(ch);
 297                 v3 = sh_cmt_read_cmcnt(ch);
 298                 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 299         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
 300                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 301
 302         *has_wrapped = o1;
 303         return v2;
 304 }
 305
 306 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
 307 {
 308         unsigned long flags;
 309         u32 value;
 310
 311         /* start stop register shared by multiple timer channels */
 312         raw_spin_lock_irqsave(&ch->cmt->lock, flags);
 313         value = sh_cmt_read_cmstr(ch);
 314
 315         if (start)
 316                 value |= 1 << ch->timer_bit;
 317         else
 318                 value &= ~(1 << ch->timer_bit);
 319
 320         sh_cmt_write_cmstr(ch, value);
 321         raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
 322 }
 323
 324 static int sh_cmt_enable(struct sh_cmt_channel *ch)
 325 {
 326         int k, ret;
 327
 328         pm_runtime_get_sync(&ch->cmt->pdev->dev);
 329         dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
 330
 331         /* enable clock */
 332         ret = clk_enable(ch->cmt->clk);
 333         if (ret) {
 334                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
 335                         ch->index);
 336                 goto err0;
 337         }
 338
 339         /* make sure channel is disabled */
 340         sh_cmt_start_stop_ch(ch, 0);
 341
 342         /* configure channel, periodic mode and maximum timeout */
 343         if (ch->cmt->info->width == 16) {
 344                 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
 345                                    SH_CMT16_CMCSR_CKS512);
 346         } else {
 347                 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
 348                                    SH_CMT32_CMCSR_CMTOUT_IE |
 349                                    SH_CMT32_CMCSR_CMR_IRQ |
 350                                    SH_CMT32_CMCSR_CKS_RCLK8);
 351         }
 352
 353         sh_cmt_write_cmcor(ch, 0xffffffff);
 354         sh_cmt_write_cmcnt(ch, 0);
 355
 356         /*
 357          * According to the sh73a0 user's manual, as CMCNT can be operated
 358          * only by the RCLK (Pseudo 32 KHz), there's one restriction on
 359          * modifying CMCNT register; two RCLK cycles are necessary before
 360          * this register is either read or any modification of the value
 361          * it holds is reflected in the LSI's actual operation.
 362          *
 363          * While at it, we're supposed to clear out the CMCNT as of this
 364          * moment, so make sure it's processed properly here.  This will
 365          * take RCLKx2 at maximum.
 366          */
 367         for (k = 0; k < 100; k++) {
 368                 if (!sh_cmt_read_cmcnt(ch))
 369                         break;
 370                 udelay(1);
 371         }
 372
 373         if (sh_cmt_read_cmcnt(ch)) {
 374                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
 375                         ch->index);
 376                 ret = -ETIMEDOUT;
 377                 goto err1;
 378         }
 379
 380         /* enable channel */
 381         sh_cmt_start_stop_ch(ch, 1);
 382         return 0;
 383  err1:
 384         /* stop clock */
 385         clk_disable(ch->cmt->clk);
 386
 387  err0:
 388         return ret;
 389 }
 390
 391 static void sh_cmt_disable(struct sh_cmt_channel *ch)
 392 {
 393         /* disable channel */
 394         sh_cmt_start_stop_ch(ch, 0);
 395
 396         /* disable interrupts in CMT block */
 397         sh_cmt_write_cmcsr(ch, 0);
 398
 399         /* stop clock */
 400         clk_disable(ch->cmt->clk);
 401
 402         dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
 403         pm_runtime_put(&ch->cmt->pdev->dev);
 404 }
 405
 406 /* private flags */
 407 #define FLAG_CLOCKEVENT (1 << 0)
 408 #define FLAG_CLOCKSOURCE (1 << 1)
 409 #define FLAG_REPROGRAM (1 << 2)
 410 #define FLAG_SKIPEVENT (1 << 3)
 411 #define FLAG_IRQCONTEXT (1 << 4)
 412
 413 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
 414                                               int absolute)
 415 {
 416         u32 value = ch->next_match_value;
 417         u32 new_match;
 418         u32 delay = 0;
 419         u32 now = 0;
 420         u32 has_wrapped;
 421
 422         now = sh_cmt_get_counter(ch, &has_wrapped);
 423         ch->flags |= FLAG_REPROGRAM; /* force reprogram */
 424
 425         if (has_wrapped) {
 426                 /* we're competing with the interrupt handler.
 427                  *  -> let the interrupt handler reprogram the timer.
 428                  *  -> interrupt number two handles the event.
 429                  */
 430                 ch->flags |= FLAG_SKIPEVENT;
 431                 return;
 432         }
 433
 434         if (absolute)
 435                 now = 0;
 436
 437         do {
 438                 /* reprogram the timer hardware,
 439                  * but don't save the new match value yet.
 440                  */
 441                 new_match = now + value + delay;
 442                 if (new_match > ch->max_match_value)
 443                         new_match = ch->max_match_value;
 444
 445                 sh_cmt_write_cmcor(ch, new_match);
 446
 447                 now = sh_cmt_get_counter(ch, &has_wrapped);
 448                 if (has_wrapped && (new_match > ch->match_value)) {
 449                         /* we are changing to a greater match value,
 450                          * so this wrap must be caused by the counter
 451                          * matching the old value.
 452                          * -> first interrupt reprograms the timer.
 453                          * -> interrupt number two handles the event.
 454                          */
 455                         ch->flags |= FLAG_SKIPEVENT;
 456                         break;
 457                 }
 458
 459                 if (has_wrapped) {
 460                         /* we are changing to a smaller match value,
 461                          * so the wrap must be caused by the counter
 462                          * matching the new value.
 463                          * -> save programmed match value.
 464                          * -> let isr handle the event.
 465                          */
 466                         ch->match_value = new_match;
 467                         break;
 468                 }
 469
 470                 /* be safe: verify hardware settings */
 471                 if (now < new_match) {
 472                         /* timer value is below match value, all good.
 473                          * this makes sure we won't miss any match events.
 474                          * -> save programmed match value.
 475                          * -> let isr handle the event.
 476                          */
 477                         ch->match_value = new_match;
 478                         break;
 479                 }
 480
 481                 /* the counter has reached a value greater
 482                  * than our new match value. and since the
 483                  * has_wrapped flag isn't set we must have
 484                  * programmed a too close event.
 485                  * -> increase delay and retry.
 486                  */
 487                 if (delay)
 488                         delay <<= 1;
 489                 else
 490                         delay = 1;
 491
 492                 if (!delay)
 493                         dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
 494                                  ch->index);
 495
 496         } while (delay);
 497 }
 498
 499 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 500 {
 501         if (delta > ch->max_match_value)
 502                 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
 503                          ch->index);
 504
 505         ch->next_match_value = delta;
 506         sh_cmt_clock_event_program_verify(ch, 0);
 507 }
 508
 509 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 510 {
 511         unsigned long flags;
 512
 513         raw_spin_lock_irqsave(&ch->lock, flags);
 514         __sh_cmt_set_next(ch, delta);
 515         raw_spin_unlock_irqrestore(&ch->lock, flags);
 516 }
 517
 518 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
 519 {
 520         struct sh_cmt_channel *ch = dev_id;
 521
 522         /* clear flags */
 523         sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
 524                            ch->cmt->info->clear_bits);
 525
 526         /* update clock source counter to begin with if enabled
 527          * the wrap flag should be cleared by the timer specific
 528          * isr before we end up here.
 529          */
 530         if (ch->flags & FLAG_CLOCKSOURCE)
 531                 ch->total_cycles += ch->match_value + 1;
 532
 533         if (!(ch->flags & FLAG_REPROGRAM))
 534                 ch->next_match_value = ch->max_match_value;
 535
 536         ch->flags |= FLAG_IRQCONTEXT;
 537
 538         if (ch->flags & FLAG_CLOCKEVENT) {
 539                 if (!(ch->flags & FLAG_SKIPEVENT)) {
 540                         if (clockevent_state_oneshot(&ch->ced)) {
 541                                 ch->next_match_value = ch->max_match_value;
 542                                 ch->flags |= FLAG_REPROGRAM;
 543                         }
 544
 545                         ch->ced.event_handler(&ch->ced);
 546                 }
 547         }
 548
 549         ch->flags &= ~FLAG_SKIPEVENT;
 550
 551         if (ch->flags & FLAG_REPROGRAM) {
 552                 ch->flags &= ~FLAG_REPROGRAM;
 553                 sh_cmt_clock_event_program_verify(ch, 1);
 554
 555                 if (ch->flags & FLAG_CLOCKEVENT)
 556                         if ((clockevent_state_shutdown(&ch->ced))
 557                             || (ch->match_value == ch->next_match_value))
 558                                 ch->flags &= ~FLAG_REPROGRAM;
 559         }
 560
 561         ch->flags &= ~FLAG_IRQCONTEXT;
 562
 563         return IRQ_HANDLED;
 564 }
 565
 566 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
 567 {
 568         int ret = 0;
 569         unsigned long flags;
 570
 571         raw_spin_lock_irqsave(&ch->lock, flags);
 572
 573         if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 574                 ret = sh_cmt_enable(ch);
 575
 576         if (ret)
 577                 goto out;
 578         ch->flags |= flag;
 579
 580         /* setup timeout if no clockevent */
 581         if (ch->cmt->num_channels == 1 &&
 582             flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT)))
 583                 __sh_cmt_set_next(ch, ch->max_match_value);
 584  out:
 585         raw_spin_unlock_irqrestore(&ch->lock, flags);
 586
 587         return ret;
 588 }
 589
 590 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
 591 {
 592         unsigned long flags;
 593         unsigned long f;
 594
 595         raw_spin_lock_irqsave(&ch->lock, flags);
 596
 597         f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
 598         ch->flags &= ~flag;
 599
 600         if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 601                 sh_cmt_disable(ch);
 602
 603         /* adjust the timeout to maximum if only clocksource left */
 604         if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
 605                 __sh_cmt_set_next(ch, ch->max_match_value);
 606
 607         raw_spin_unlock_irqrestore(&ch->lock, flags);
 608 }
 609
 610 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
 611 {
 612         return container_of(cs, struct sh_cmt_channel, cs);
 613 }
 614
 615 static u64 sh_cmt_clocksource_read(struct clocksource *cs)
 616 {
 617         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 618         u32 has_wrapped;
 619
 620         if (ch->cmt->num_channels == 1) {
 621                 unsigned long flags;
 622                 u64 value;
 623                 u32 raw;
 624
 625                 raw_spin_lock_irqsave(&ch->lock, flags);
 626                 value = ch->total_cycles;
 627                 raw = sh_cmt_get_counter(ch, &has_wrapped);
 628
 629                 if (unlikely(has_wrapped))
 630                         raw += ch->match_value + 1;
 631                 raw_spin_unlock_irqrestore(&ch->lock, flags);
 632
 633                 return value + raw;
 634         }
 635
 636         return sh_cmt_get_counter(ch, &has_wrapped);
 637 }
 638
 639 static int sh_cmt_clocksource_enable(struct clocksource *cs)
 640 {
 641         int ret;
 642         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 643
 644         WARN_ON(ch->cs_enabled);
 645
 646         ch->total_cycles = 0;
 647
 648         ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 649         if (!ret)
 650                 ch->cs_enabled = true;
 651
 652         return ret;
 653 }
 654
 655 static void sh_cmt_clocksource_disable(struct clocksource *cs)
 656 {
 657         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 658
 659         WARN_ON(!ch->cs_enabled);
 660
 661         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 662         ch->cs_enabled = false;
 663 }
 664
 665 static void sh_cmt_clocksource_suspend(struct clocksource *cs)
 666 {
 667         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 668
 669         if (!ch->cs_enabled)
 670                 return;
 671
 672         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 673         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 674 }
 675
 676 static void sh_cmt_clocksource_resume(struct clocksource *cs)
 677 {
 678         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 679
 680         if (!ch->cs_enabled)
 681                 return;
 682
 683         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 684         sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 685 }
 686
 687 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
 688                                        const char *name)
 689 {
 690         struct clocksource *cs = &ch->cs;
 691
 692         cs->name = name;
 693         cs->rating = 125;
 694         cs->read = sh_cmt_clocksource_read;
 695         cs->enable = sh_cmt_clocksource_enable;
 696         cs->disable = sh_cmt_clocksource_disable;
 697         cs->suspend = sh_cmt_clocksource_suspend;
 698         cs->resume = sh_cmt_clocksource_resume;
 699         cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width);
 700         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 701
 702         dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
 703                  ch->index);
 704
 705         clocksource_register_hz(cs, ch->cmt->rate);
 706         return 0;
 707 }
 708
 709 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
 710 {
 711         return container_of(ced, struct sh_cmt_channel, ced);
 712 }
 713
 714 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
 715 {
 716         sh_cmt_start(ch, FLAG_CLOCKEVENT);
 717
 718         if (periodic)
 719                 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
 720         else
 721                 sh_cmt_set_next(ch, ch->max_match_value);
 722 }
 723
 724 static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
 725 {
 726         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 727
 728         sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 729         return 0;
 730 }
 731
 732 static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
 733                                         int periodic)
 734 {
 735         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 736
 737         /* deal with old setting first */
 738         if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
 739                 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 740
 741         dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
 742                  ch->index, periodic ? "periodic" : "oneshot");
 743         sh_cmt_clock_event_start(ch, periodic);
 744         return 0;
 745 }
 746
 747 static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
 748 {
 749         return sh_cmt_clock_event_set_state(ced, 0);
 750 }
 751
 752 static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
 753 {
 754         return sh_cmt_clock_event_set_state(ced, 1);
 755 }
 756
 757 static int sh_cmt_clock_event_next(unsigned long delta,
 758                                    struct clock_event_device *ced)
 759 {
 760         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 761
 762         BUG_ON(!clockevent_state_oneshot(ced));
 763         if (likely(ch->flags & FLAG_IRQCONTEXT))
 764                 ch->next_match_value = delta - 1;
 765         else
 766                 sh_cmt_set_next(ch, delta - 1);
 767
 768         return 0;
 769 }
 770
 771 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
 772 {
 773         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 774
 775         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 776         clk_unprepare(ch->cmt->clk);
 777 }
 778
 779 static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
 780 {
 781         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 782
 783         clk_prepare(ch->cmt->clk);
 784         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 785 }
 786
 787 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
 788                                       const char *name)
 789 {
 790         struct clock_event_device *ced = &ch->ced;
 791         int irq;
 792         int ret;
 793
 794         irq = platform_get_irq(ch->cmt->pdev, ch->index);
 795         if (irq < 0) {
 796                 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
 797                         ch->index);
 798                 return irq;
 799         }
 800
 801         ret = request_irq(irq, sh_cmt_interrupt,
 802                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 803                           dev_name(&ch->cmt->pdev->dev), ch);
 804         if (ret) {
 805                 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
 806                         ch->index, irq);
 807                 return ret;
 808         }
 809
 810         ced->name = name;
 811         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 812         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 813         ced->rating = 125;
 814         ced->cpumask = cpu_possible_mask;
 815         ced->set_next_event = sh_cmt_clock_event_next;
 816         ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
 817         ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
 818         ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
 819         ced->suspend = sh_cmt_clock_event_suspend;
 820         ced->resume = sh_cmt_clock_event_resume;
 821
 822         /* TODO: calculate good shift from rate and counter bit width */
 823         ced->shift = 32;
 824         ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
 825         ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
 826         ced->max_delta_ticks = ch->max_match_value;
 827         ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
 828         ced->min_delta_ticks = 0x1f;
 829
 830         dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
 831                  ch->index);
 832         clockevents_register_device(ced);
 833
 834         return 0;
 835 }
 836
 837 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
 838                            bool clockevent, bool clocksource)
 839 {
 840         int ret;
 841
 842         if (clockevent) {
 843                 ch->cmt->has_clockevent = true;
 844                 ret = sh_cmt_register_clockevent(ch, name);
 845                 if (ret < 0)
 846                         return ret;
 847         }
 848
 849         if (clocksource) {
 850                 ch->cmt->has_clocksource = true;
 851                 sh_cmt_register_clocksource(ch, name);
 852         }
 853
 854         return 0;
 855 }
 856
 857 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
 858                                 unsigned int hwidx, bool clockevent,
 859                                 bool clocksource, struct sh_cmt_device *cmt)
 860 {
 861         u32 value;
 862         int ret;
 863
 864         /* Skip unused channels. */
 865         if (!clockevent && !clocksource)
 866                 return 0;
 867
 868         ch->cmt = cmt;
 869         ch->index = index;
 870         ch->hwidx = hwidx;
 871         ch->timer_bit = hwidx;
 872
 873         /*
 874          * Compute the address of the channel control register block. For the
 875          * timers with a per-channel start/stop register, compute its address
 876          * as well.
 877          */
 878         switch (cmt->info->model) {
 879         case SH_CMT_16BIT:
 880                 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
 881                 break;
 882         case SH_CMT_32BIT:
 883         case SH_CMT_48BIT:
 884                 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
 885                 break;
 886         case SH_CMT0_RCAR_GEN2:
 887         case SH_CMT1_RCAR_GEN2:
 888                 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
 889                 ch->ioctrl = ch->iostart + 0x10;
 890                 ch->timer_bit = 0;
 891
 892                 /* Enable the clock supply to the channel */
 893                 value = ioread32(cmt->mapbase + CMCLKE);
 894                 value |= BIT(hwidx);
 895                 iowrite32(value, cmt->mapbase + CMCLKE);
 896                 break;
 897         }
 898
 899         if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
 900                 ch->max_match_value = ~0;
 901         else
 902                 ch->max_match_value = (1 << cmt->info->width) - 1;
 903
 904         ch->match_value = ch->max_match_value;
 905         raw_spin_lock_init(&ch->lock);
 906
 907         ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
 908                               clockevent, clocksource);
 909         if (ret) {
 910                 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
 911                         ch->index);
 912                 return ret;
 913         }
 914         ch->cs_enabled = false;
 915
 916         return 0;
 917 }
 918
 919 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
 920 {
 921         struct resource *mem;
 922
 923         mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
 924         if (!mem) {
 925                 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
 926                 return -ENXIO;
 927         }
 928
 929         cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
 930         if (cmt->mapbase == NULL) {
 931                 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
 932                 return -ENXIO;
 933         }
 934
 935         return 0;
 936 }
 937
 938 static const struct platform_device_id sh_cmt_id_table[] = {
 939         { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
 940         { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
 941         { }
 942 };
 943 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
 944
 945 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
 946         { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
 947         {
 948                 /* deprecated, preserved for backward compatibility */
 949                 .compatible = "renesas,cmt-48-gen2",
 950                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 951         },
 952         { .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
 953         { .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] },
 954         { }
 955 };
 956 MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
 957
 958 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
 959 {
 960         unsigned int mask;
 961         unsigned int i;
 962         int ret;
 963
 964         cmt->pdev = pdev;
 965         raw_spin_lock_init(&cmt->lock);
 966
 967         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
 968                 cmt->info = of_device_get_match_data(&pdev->dev);
 969                 cmt->hw_channels = cmt->info->channels_mask;
 970         } else if (pdev->dev.platform_data) {
 971                 struct sh_timer_config *cfg = pdev->dev.platform_data;
 972                 const struct platform_device_id *id = pdev->id_entry;
 973
 974                 cmt->info = (const struct sh_cmt_info *)id->driver_data;
 975                 cmt->hw_channels = cfg->channels_mask;
 976         } else {
 977                 dev_err(&cmt->pdev->dev, "missing platform data\n");
 978                 return -ENXIO;
 979         }
 980
 981         /* Get hold of clock. */
 982         cmt->clk = clk_get(&cmt->pdev->dev, "fck");
 983         if (IS_ERR(cmt->clk)) {
 984                 dev_err(&cmt->pdev->dev, "cannot get clock\n");
 985                 return PTR_ERR(cmt->clk);
 986         }
 987
 988         ret = clk_prepare(cmt->clk);
 989         if (ret < 0)
 990                 goto err_clk_put;
 991
 992         /* Determine clock rate. */
 993         ret = clk_enable(cmt->clk);
 994         if (ret < 0)
 995                 goto err_clk_unprepare;
 996
 997         if (cmt->info->width == 16)
 998                 cmt->rate = clk_get_rate(cmt->clk) / 512;
 999         else
1000                 cmt->rate = clk_get_rate(cmt->clk) / 8;
1001
1002         /* Map the memory resource(s). */
1003         ret = sh_cmt_map_memory(cmt);
1004         if (ret < 0)
1005                 goto err_clk_disable;
1006
1007         /* Allocate and setup the channels. */
1008         cmt->num_channels = hweight8(cmt->hw_channels);
1009         cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1010                                 GFP_KERNEL);
1011         if (cmt->channels == NULL) {
1012                 ret = -ENOMEM;
1013                 goto err_unmap;
1014         }
1015
1016         /*
1017          * Use the first channel as a clock event device and the second channel
1018          * as a clock source. If only one channel is available use it for both.
1019          */
1020         for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1021                 unsigned int hwidx = ffs(mask) - 1;
1022                 bool clocksource = i == 1 || cmt->num_channels == 1;
1023                 bool clockevent = i == 0;
1024
1025                 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1026                                            clockevent, clocksource, cmt);
1027                 if (ret < 0)
1028                         goto err_unmap;
1029
1030                 mask &= ~(1 << hwidx);
1031         }
1032
1033         clk_disable(cmt->clk);
1034
1035         platform_set_drvdata(pdev, cmt);
1036
1037         return 0;
1038
1039 err_unmap:
1040         kfree(cmt->channels);
1041         iounmap(cmt->mapbase);
1042 err_clk_disable:
1043         clk_disable(cmt->clk);
1044 err_clk_unprepare:
1045         clk_unprepare(cmt->clk);
1046 err_clk_put:
1047         clk_put(cmt->clk);
1048         return ret;
1049 }
1050
1051 static int sh_cmt_probe(struct platform_device *pdev)
1052 {
1053         struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1054         int ret;
1055
1056         if (!is_early_platform_device(pdev)) {
1057                 pm_runtime_set_active(&pdev->dev);
1058                 pm_runtime_enable(&pdev->dev);
1059         }
1060
1061         if (cmt) {
1062                 dev_info(&pdev->dev, "kept as earlytimer\n");
1063                 goto out;
1064         }
1065
1066         cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1067         if (cmt == NULL)
1068                 return -ENOMEM;
1069
1070         ret = sh_cmt_setup(cmt, pdev);
1071         if (ret) {
1072                 kfree(cmt);
1073                 pm_runtime_idle(&pdev->dev);
1074                 return ret;
1075         }
1076         if (is_early_platform_device(pdev))
1077                 return 0;
1078
1079  out:
1080         if (cmt->has_clockevent || cmt->has_clocksource)
1081                 pm_runtime_irq_safe(&pdev->dev);
1082         else
1083                 pm_runtime_idle(&pdev->dev);
1084
1085         return 0;
1086 }
1087
1088 static int sh_cmt_remove(struct platform_device *pdev)
1089 {
1090         return -EBUSY; /* cannot unregister clockevent and clocksource */
1091 }
1092
1093 static struct platform_driver sh_cmt_device_driver = {
1094         .probe          = sh_cmt_probe,
1095         .remove         = sh_cmt_remove,
1096         .driver         = {
1097                 .name   = "sh_cmt",
1098                 .of_match_table = of_match_ptr(sh_cmt_of_table),
1099         },
1100         .id_table       = sh_cmt_id_table,
1101 };
1102
1103 static int __init sh_cmt_init(void)
1104 {
1105         return platform_driver_register(&sh_cmt_device_driver);
1106 }
1107
1108 static void __exit sh_cmt_exit(void)
1109 {
1110         platform_driver_unregister(&sh_cmt_device_driver);
1111 }
1112
1113 early_platform_init("earlytimer", &sh_cmt_device_driver);
1114 subsys_initcall(sh_cmt_init);
1115 module_exit(sh_cmt_exit);
1116
1117 MODULE_AUTHOR("Magnus Damm");
1118 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1119 MODULE_LICENSE("GPL v2");