drivers/clocksource/exynos_mct.c

   1 /* linux/arch/arm/mach-exynos4/mct.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 MCT(Multi-Core Timer) support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/sched.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/cpu.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/delay.h>
  22 #include <linux/percpu.h>
  23 #include <linux/of.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_address.h>
  26 #include <linux/clocksource.h>
  27 #include <linux/sched_clock.h>
  28
  29 #define EXYNOS4_MCTREG(x)               (x)
  30 #define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
  31 #define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
  32 #define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
  33 #define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
  34 #define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
  35 #define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
  36 #define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
  37 #define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
  38 #define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
  39 #define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
  40 #define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
  41 #define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
  42 #define EXYNOS4_MCT_L_MASK              (0xffffff00)
  43
  44 #define MCT_L_TCNTB_OFFSET              (0x00)
  45 #define MCT_L_ICNTB_OFFSET              (0x08)
  46 #define MCT_L_TCON_OFFSET               (0x20)
  47 #define MCT_L_INT_CSTAT_OFFSET          (0x30)
  48 #define MCT_L_INT_ENB_OFFSET            (0x34)
  49 #define MCT_L_WSTAT_OFFSET              (0x40)
  50 #define MCT_G_TCON_START                (1 << 8)
  51 #define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
  52 #define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
  53 #define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
  54 #define MCT_L_TCON_INT_START            (1 << 1)
  55 #define MCT_L_TCON_TIMER_START          (1 << 0)
  56
  57 #define TICK_BASE_CNT   1
  58
  59 enum {
  60         MCT_INT_SPI,
  61         MCT_INT_PPI
  62 };
  63
  64 enum {
  65         MCT_G0_IRQ,
  66         MCT_G1_IRQ,
  67         MCT_G2_IRQ,
  68         MCT_G3_IRQ,
  69         MCT_L0_IRQ,
  70         MCT_L1_IRQ,
  71         MCT_L2_IRQ,
  72         MCT_L3_IRQ,
  73         MCT_L4_IRQ,
  74         MCT_L5_IRQ,
  75         MCT_L6_IRQ,
  76         MCT_L7_IRQ,
  77         MCT_NR_IRQS,
  78 };
  79
  80 static void __iomem *reg_base;
  81 static unsigned long clk_rate;
  82 static unsigned int mct_int_type;
  83 static int mct_irqs[MCT_NR_IRQS];
  84
  85 struct mct_clock_event_device {
  86         struct clock_event_device evt;
  87         unsigned long base;
  88         char name[10];
  89 };
  90
  91 static void exynos4_mct_write(unsigned int value, unsigned long offset)
  92 {
  93         unsigned long stat_addr;
  94         u32 mask;
  95         u32 i;
  96
  97         writel_relaxed(value, reg_base + offset);
  98
  99         if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
 100                 stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
 101                 switch (offset & ~EXYNOS4_MCT_L_MASK) {
 102                 case MCT_L_TCON_OFFSET:
 103                         mask = 1 << 3;          /* L_TCON write status */
 104                         break;
 105                 case MCT_L_ICNTB_OFFSET:
 106                         mask = 1 << 1;          /* L_ICNTB write status */
 107                         break;
 108                 case MCT_L_TCNTB_OFFSET:
 109                         mask = 1 << 0;          /* L_TCNTB write status */
 110                         break;
 111                 default:
 112                         return;
 113                 }
 114         } else {
 115                 switch (offset) {
 116                 case EXYNOS4_MCT_G_TCON:
 117                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 118                         mask = 1 << 16;         /* G_TCON write status */
 119                         break;
 120                 case EXYNOS4_MCT_G_COMP0_L:
 121                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 122                         mask = 1 << 0;          /* G_COMP0_L write status */
 123                         break;
 124                 case EXYNOS4_MCT_G_COMP0_U:
 125                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 126                         mask = 1 << 1;          /* G_COMP0_U write status */
 127                         break;
 128                 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
 129                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 130                         mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
 131                         break;
 132                 case EXYNOS4_MCT_G_CNT_L:
 133                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
 134                         mask = 1 << 0;          /* G_CNT_L write status */
 135                         break;
 136                 case EXYNOS4_MCT_G_CNT_U:
 137                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
 138                         mask = 1 << 1;          /* G_CNT_U write status */
 139                         break;
 140                 default:
 141                         return;
 142                 }
 143         }
 144
 145         /* Wait maximum 1 ms until written values are applied */
 146         for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
 147                 if (readl_relaxed(reg_base + stat_addr) & mask) {
 148                         writel_relaxed(mask, reg_base + stat_addr);
 149                         return;
 150                 }
 151
 152         panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
 153 }
 154
 155 /* Clocksource handling */
 156 static void exynos4_mct_frc_start(void)
 157 {
 158         u32 reg;
 159
 160         reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
 161         reg |= MCT_G_TCON_START;
 162         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 163 }
 164
 165 /**
 166  * exynos4_read_count_64 - Read all 64-bits of the global counter
 167  *
 168  * This will read all 64-bits of the global counter taking care to make sure
 169  * that the upper and lower half match.  Note that reading the MCT can be quite
 170  * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
 171  * only) version when possible.
 172  *
 173  * Returns the number of cycles in the global counter.
 174  */
 175 static u64 exynos4_read_count_64(void)
 176 {
 177         unsigned int lo, hi;
 178         u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
 179
 180         do {
 181                 hi = hi2;
 182                 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
 183                 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
 184         } while (hi != hi2);
 185
 186         return ((u64)hi << 32) | lo;
 187 }
 188
 189 /**
 190  * exynos4_read_count_32 - Read the lower 32-bits of the global counter
 191  *
 192  * This will read just the lower 32-bits of the global counter.  This is marked
 193  * as notrace so it can be used by the scheduler clock.
 194  *
 195  * Returns the number of cycles in the global counter (lower 32 bits).
 196  */
 197 static u32 notrace exynos4_read_count_32(void)
 198 {
 199         return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
 200 }
 201
 202 static u64 exynos4_frc_read(struct clocksource *cs)
 203 {
 204         return exynos4_read_count_32();
 205 }
 206
 207 static void exynos4_frc_resume(struct clocksource *cs)
 208 {
 209         exynos4_mct_frc_start();
 210 }
 211
 212 static struct clocksource mct_frc = {
 213         .name           = "mct-frc",
 214         .rating         = 450,  /* use value higher than ARM arch timer */
 215         .read           = exynos4_frc_read,
 216         .mask           = CLOCKSOURCE_MASK(32),
 217         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 218         .resume         = exynos4_frc_resume,
 219 };
 220
 221 static u64 notrace exynos4_read_sched_clock(void)
 222 {
 223         return exynos4_read_count_32();
 224 }
 225
 226 #if defined(CONFIG_ARM)
 227 static struct delay_timer exynos4_delay_timer;
 228
 229 static cycles_t exynos4_read_current_timer(void)
 230 {
 231         BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32),
 232                          "cycles_t needs to move to 32-bit for ARM64 usage");
 233         return exynos4_read_count_32();
 234 }
 235 #endif
 236
 237 static int __init exynos4_clocksource_init(void)
 238 {
 239         exynos4_mct_frc_start();
 240
 241 #if defined(CONFIG_ARM)
 242         exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
 243         exynos4_delay_timer.freq = clk_rate;
 244         register_current_timer_delay(&exynos4_delay_timer);
 245 #endif
 246
 247         if (clocksource_register_hz(&mct_frc, clk_rate))
 248                 panic("%s: can't register clocksource\n", mct_frc.name);
 249
 250         sched_clock_register(exynos4_read_sched_clock, 32, clk_rate);
 251
 252         return 0;
 253 }
 254
 255 static void exynos4_mct_comp0_stop(void)
 256 {
 257         unsigned int tcon;
 258
 259         tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
 260         tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
 261
 262         exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
 263         exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
 264 }
 265
 266 static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles)
 267 {
 268         unsigned int tcon;
 269         u64 comp_cycle;
 270
 271         tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
 272
 273         if (periodic) {
 274                 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
 275                 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
 276         }
 277
 278         comp_cycle = exynos4_read_count_64() + cycles;
 279         exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
 280         exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
 281
 282         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
 283
 284         tcon |= MCT_G_TCON_COMP0_ENABLE;
 285         exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
 286 }
 287
 288 static int exynos4_comp_set_next_event(unsigned long cycles,
 289                                        struct clock_event_device *evt)
 290 {
 291         exynos4_mct_comp0_start(false, cycles);
 292
 293         return 0;
 294 }
 295
 296 static int mct_set_state_shutdown(struct clock_event_device *evt)
 297 {
 298         exynos4_mct_comp0_stop();
 299         return 0;
 300 }
 301
 302 static int mct_set_state_periodic(struct clock_event_device *evt)
 303 {
 304         unsigned long cycles_per_jiffy;
 305
 306         cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
 307                             >> evt->shift);
 308         exynos4_mct_comp0_stop();
 309         exynos4_mct_comp0_start(true, cycles_per_jiffy);
 310         return 0;
 311 }
 312
 313 static struct clock_event_device mct_comp_device = {
 314         .name                   = "mct-comp",
 315         .features               = CLOCK_EVT_FEAT_PERIODIC |
 316                                   CLOCK_EVT_FEAT_ONESHOT,
 317         .rating                 = 250,
 318         .set_next_event         = exynos4_comp_set_next_event,
 319         .set_state_periodic     = mct_set_state_periodic,
 320         .set_state_shutdown     = mct_set_state_shutdown,
 321         .set_state_oneshot      = mct_set_state_shutdown,
 322         .set_state_oneshot_stopped = mct_set_state_shutdown,
 323         .tick_resume            = mct_set_state_shutdown,
 324 };
 325
 326 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
 327 {
 328         struct clock_event_device *evt = dev_id;
 329
 330         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
 331
 332         evt->event_handler(evt);
 333
 334         return IRQ_HANDLED;
 335 }
 336
 337 static struct irqaction mct_comp_event_irq = {
 338         .name           = "mct_comp_irq",
 339         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 340         .handler        = exynos4_mct_comp_isr,
 341         .dev_id         = &mct_comp_device,
 342 };
 343
 344 static int exynos4_clockevent_init(void)
 345 {
 346         mct_comp_device.cpumask = cpumask_of(0);
 347         clockevents_config_and_register(&mct_comp_device, clk_rate,
 348                                         0xf, 0xffffffff);
 349         setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
 350
 351         return 0;
 352 }
 353
 354 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
 355
 356 /* Clock event handling */
 357 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
 358 {
 359         unsigned long tmp;
 360         unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
 361         unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
 362
 363         tmp = readl_relaxed(reg_base + offset);
 364         if (tmp & mask) {
 365                 tmp &= ~mask;
 366                 exynos4_mct_write(tmp, offset);
 367         }
 368 }
 369
 370 static void exynos4_mct_tick_start(unsigned long cycles,
 371                                    struct mct_clock_event_device *mevt)
 372 {
 373         unsigned long tmp;
 374
 375         exynos4_mct_tick_stop(mevt);
 376
 377         tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
 378
 379         /* update interrupt count buffer */
 380         exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
 381
 382         /* enable MCT tick interrupt */
 383         exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
 384
 385         tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
 386         tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
 387                MCT_L_TCON_INTERVAL_MODE;
 388         exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
 389 }
 390
 391 static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 392 {
 393         /* Clear the MCT tick interrupt */
 394         if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)
 395                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
 396 }
 397
 398 static int exynos4_tick_set_next_event(unsigned long cycles,
 399                                        struct clock_event_device *evt)
 400 {
 401         struct mct_clock_event_device *mevt;
 402
 403         mevt = container_of(evt, struct mct_clock_event_device, evt);
 404         exynos4_mct_tick_start(cycles, mevt);
 405         return 0;
 406 }
 407
 408 static int set_state_shutdown(struct clock_event_device *evt)
 409 {
 410         struct mct_clock_event_device *mevt;
 411
 412         mevt = container_of(evt, struct mct_clock_event_device, evt);
 413         exynos4_mct_tick_stop(mevt);
 414         exynos4_mct_tick_clear(mevt);
 415         return 0;
 416 }
 417
 418 static int set_state_periodic(struct clock_event_device *evt)
 419 {
 420         struct mct_clock_event_device *mevt;
 421         unsigned long cycles_per_jiffy;
 422
 423         mevt = container_of(evt, struct mct_clock_event_device, evt);
 424         cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
 425                             >> evt->shift);
 426         exynos4_mct_tick_stop(mevt);
 427         exynos4_mct_tick_start(cycles_per_jiffy, mevt);
 428         return 0;
 429 }
 430
 431 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
 432 {
 433         struct mct_clock_event_device *mevt = dev_id;
 434         struct clock_event_device *evt = &mevt->evt;
 435
 436         /*
 437          * This is for supporting oneshot mode.
 438          * Mct would generate interrupt periodically
 439          * without explicit stopping.
 440          */
 441         if (!clockevent_state_periodic(&mevt->evt))
 442                 exynos4_mct_tick_stop(mevt);
 443
 444         exynos4_mct_tick_clear(mevt);
 445
 446         evt->event_handler(evt);
 447
 448         return IRQ_HANDLED;
 449 }
 450
 451 static int exynos4_mct_starting_cpu(unsigned int cpu)
 452 {
 453         struct mct_clock_event_device *mevt =
 454                 per_cpu_ptr(&percpu_mct_tick, cpu);
 455         struct clock_event_device *evt = &mevt->evt;
 456
 457         mevt->base = EXYNOS4_MCT_L_BASE(cpu);
 458         snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
 459
 460         evt->name = mevt->name;
 461         evt->cpumask = cpumask_of(cpu);
 462         evt->set_next_event = exynos4_tick_set_next_event;
 463         evt->set_state_periodic = set_state_periodic;
 464         evt->set_state_shutdown = set_state_shutdown;
 465         evt->set_state_oneshot = set_state_shutdown;
 466         evt->set_state_oneshot_stopped = set_state_shutdown;
 467         evt->tick_resume = set_state_shutdown;
 468         evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 469         evt->rating = 500;      /* use value higher than ARM arch timer */
 470
 471         exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
 472
 473         if (mct_int_type == MCT_INT_SPI) {
 474
 475                 if (evt->irq == -1)
 476                         return -EIO;
 477
 478                 irq_force_affinity(evt->irq, cpumask_of(cpu));
 479                 enable_irq(evt->irq);
 480         } else {
 481                 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
 482         }
 483         clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
 484                                         0xf, 0x7fffffff);
 485
 486         return 0;
 487 }
 488
 489 static int exynos4_mct_dying_cpu(unsigned int cpu)
 490 {
 491         struct mct_clock_event_device *mevt =
 492                 per_cpu_ptr(&percpu_mct_tick, cpu);
 493         struct clock_event_device *evt = &mevt->evt;
 494
 495         evt->set_state_shutdown(evt);
 496         if (mct_int_type == MCT_INT_SPI) {
 497                 if (evt->irq != -1)
 498                         disable_irq_nosync(evt->irq);
 499                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
 500         } else {
 501                 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
 502         }
 503         return 0;
 504 }
 505
 506 static int __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
 507 {
 508         int err, cpu;
 509         struct clk *mct_clk, *tick_clk;
 510
 511         tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
 512                                 clk_get(NULL, "fin_pll");
 513         if (IS_ERR(tick_clk))
 514                 panic("%s: unable to determine tick clock rate\n", __func__);
 515         clk_rate = clk_get_rate(tick_clk);
 516
 517         mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
 518         if (IS_ERR(mct_clk))
 519                 panic("%s: unable to retrieve mct clock instance\n", __func__);
 520         clk_prepare_enable(mct_clk);
 521
 522         reg_base = base;
 523         if (!reg_base)
 524                 panic("%s: unable to ioremap mct address space\n", __func__);
 525
 526         if (mct_int_type == MCT_INT_PPI) {
 527
 528                 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
 529                                          exynos4_mct_tick_isr, "MCT",
 530                                          &percpu_mct_tick);
 531                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
 532                      mct_irqs[MCT_L0_IRQ], err);
 533         } else {
 534                 for_each_possible_cpu(cpu) {
 535                         int mct_irq = mct_irqs[MCT_L0_IRQ + cpu];
 536                         struct mct_clock_event_device *pcpu_mevt =
 537                                 per_cpu_ptr(&percpu_mct_tick, cpu);
 538
 539                         pcpu_mevt->evt.irq = -1;
 540
 541                         irq_set_status_flags(mct_irq, IRQ_NOAUTOEN);
 542                         if (request_irq(mct_irq,
 543                                         exynos4_mct_tick_isr,
 544                                         IRQF_TIMER | IRQF_NOBALANCING,
 545                                         pcpu_mevt->name, pcpu_mevt)) {
 546                                 pr_err("exynos-mct: cannot register IRQ (cpu%d)\n",
 547                                                                         cpu);
 548
 549                                 continue;
 550                         }
 551                         pcpu_mevt->evt.irq = mct_irq;
 552                 }
 553         }
 554
 555         /* Install hotplug callbacks which configure the timer on this CPU */
 556         err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
 557                                 "clockevents/exynos4/mct_timer:starting",
 558                                 exynos4_mct_starting_cpu,
 559                                 exynos4_mct_dying_cpu);
 560         if (err)
 561                 goto out_irq;
 562
 563         return 0;
 564
 565 out_irq:
 566         if (mct_int_type == MCT_INT_PPI) {
 567                 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
 568         } else {
 569                 for_each_possible_cpu(cpu) {
 570                         struct mct_clock_event_device *pcpu_mevt =
 571                                 per_cpu_ptr(&percpu_mct_tick, cpu);
 572
 573                         if (pcpu_mevt->evt.irq != -1) {
 574                                 free_irq(pcpu_mevt->evt.irq, pcpu_mevt);
 575                                 pcpu_mevt->evt.irq = -1;
 576                         }
 577                 }
 578         }
 579         return err;
 580 }
 581
 582 static int __init mct_init_dt(struct device_node *np, unsigned int int_type)
 583 {
 584         u32 nr_irqs, i;
 585         int ret;
 586
 587         mct_int_type = int_type;
 588
 589         /* This driver uses only one global timer interrupt */
 590         mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
 591
 592         /*
 593          * Find out the number of local irqs specified. The local
 594          * timer irqs are specified after the four global timer
 595          * irqs are specified.
 596          */
 597 #ifdef CONFIG_OF
 598         nr_irqs = of_irq_count(np);
 599 #else
 600         nr_irqs = 0;
 601 #endif
 602         for (i = MCT_L0_IRQ; i < nr_irqs; i++)
 603                 mct_irqs[i] = irq_of_parse_and_map(np, i);
 604
 605         ret = exynos4_timer_resources(np, of_iomap(np, 0));
 606         if (ret)
 607                 return ret;
 608
 609         ret = exynos4_clocksource_init();
 610         if (ret)
 611                 return ret;
 612
 613         return exynos4_clockevent_init();
 614 }
 615
 616
 617 static int __init mct_init_spi(struct device_node *np)
 618 {
 619         return mct_init_dt(np, MCT_INT_SPI);
 620 }
 621
 622 static int __init mct_init_ppi(struct device_node *np)
 623 {
 624         return mct_init_dt(np, MCT_INT_PPI);
 625 }
 626 TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
 627 TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);