1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/clocksource/arm_arch_timer.c
5 * Copyright (C) 2011 ARM Ltd.
9 #define pr_fmt(fmt) "arch_timer: " fmt
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/device.h>
14 #include <linux/smp.h>
15 #include <linux/cpu.h>
16 #include <linux/cpu_pm.h>
17 #include <linux/clockchips.h>
18 #include <linux/clocksource.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_address.h>
23 #include <linux/slab.h>
24 #include <linux/sched/clock.h>
25 #include <linux/sched_clock.h>
26 #include <linux/acpi.h>
28 #include <asm/arch_timer.h>
31 #include <clocksource/arm_arch_timer.h>
34 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
36 #define CNTACR(n) (0x40 + ((n) * 4))
37 #define CNTACR_RPCT BIT(0)
38 #define CNTACR_RVCT BIT(1)
39 #define CNTACR_RFRQ BIT(2)
40 #define CNTACR_RVOFF BIT(3)
41 #define CNTACR_RWVT BIT(4)
42 #define CNTACR_RWPT BIT(5)
44 #define CNTVCT_LO 0x08
45 #define CNTVCT_HI 0x0c
47 #define CNTP_TVAL 0x28
49 #define CNTV_TVAL 0x38
52 static unsigned arch_timers_present __initdata;
54 static void __iomem *arch_counter_base;
58 struct clock_event_device evt;
61 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
63 static u32 arch_timer_rate;
64 static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI];
66 static struct clock_event_device __percpu *arch_timer_evt;
68 static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI;
69 static bool arch_timer_c3stop;
70 static bool arch_timer_mem_use_virtual;
71 static bool arch_counter_suspend_stop;
72 static enum vdso_arch_clockmode vdso_default = VDSO_CLOCKMODE_ARCHTIMER;
74 static cpumask_t evtstrm_available = CPU_MASK_NONE;
75 static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
77 static int __init early_evtstrm_cfg(char *buf)
79 return strtobool(buf, &evtstrm_enable);
81 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
84 * Architected system timer support.
87 static __always_inline
88 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
89 struct clock_event_device *clk)
91 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
92 struct arch_timer *timer = to_arch_timer(clk);
94 case ARCH_TIMER_REG_CTRL:
95 writel_relaxed(val, timer->base + CNTP_CTL);
97 case ARCH_TIMER_REG_TVAL:
98 writel_relaxed(val, timer->base + CNTP_TVAL);
101 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
102 struct arch_timer *timer = to_arch_timer(clk);
104 case ARCH_TIMER_REG_CTRL:
105 writel_relaxed(val, timer->base + CNTV_CTL);
107 case ARCH_TIMER_REG_TVAL:
108 writel_relaxed(val, timer->base + CNTV_TVAL);
112 arch_timer_reg_write_cp15(access, reg, val);
116 static __always_inline
117 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
118 struct clock_event_device *clk)
122 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
123 struct arch_timer *timer = to_arch_timer(clk);
125 case ARCH_TIMER_REG_CTRL:
126 val = readl_relaxed(timer->base + CNTP_CTL);
128 case ARCH_TIMER_REG_TVAL:
129 val = readl_relaxed(timer->base + CNTP_TVAL);
132 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
133 struct arch_timer *timer = to_arch_timer(clk);
135 case ARCH_TIMER_REG_CTRL:
136 val = readl_relaxed(timer->base + CNTV_CTL);
138 case ARCH_TIMER_REG_TVAL:
139 val = readl_relaxed(timer->base + CNTV_TVAL);
143 val = arch_timer_reg_read_cp15(access, reg);
149 static notrace u64 arch_counter_get_cntpct_stable(void)
151 return __arch_counter_get_cntpct_stable();
154 static notrace u64 arch_counter_get_cntpct(void)
156 return __arch_counter_get_cntpct();
159 static notrace u64 arch_counter_get_cntvct_stable(void)
161 return __arch_counter_get_cntvct_stable();
164 static notrace u64 arch_counter_get_cntvct(void)
166 return __arch_counter_get_cntvct();
170 * Default to cp15 based access because arm64 uses this function for
171 * sched_clock() before DT is probed and the cp15 method is guaranteed
172 * to exist on arm64. arm doesn't use this before DT is probed so even
173 * if we don't have the cp15 accessors we won't have a problem.
175 u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
176 EXPORT_SYMBOL_GPL(arch_timer_read_counter);
178 static u64 arch_counter_read(struct clocksource *cs)
180 return arch_timer_read_counter();
183 static u64 arch_counter_read_cc(const struct cyclecounter *cc)
185 return arch_timer_read_counter();
188 static struct clocksource clocksource_counter = {
189 .name = "arch_sys_counter",
191 .read = arch_counter_read,
192 .mask = CLOCKSOURCE_MASK(56),
193 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
196 static struct cyclecounter cyclecounter __ro_after_init = {
197 .read = arch_counter_read_cc,
198 .mask = CLOCKSOURCE_MASK(56),
201 struct ate_acpi_oem_info {
202 char oem_id[ACPI_OEM_ID_SIZE + 1];
203 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
207 #ifdef CONFIG_FSL_ERRATUM_A008585
209 * The number of retries is an arbitrary value well beyond the highest number
210 * of iterations the loop has been observed to take.
212 #define __fsl_a008585_read_reg(reg) ({ \
214 int _retries = 200; \
217 _old = read_sysreg(reg); \
218 _new = read_sysreg(reg); \
220 } while (unlikely(_old != _new) && _retries); \
222 WARN_ON_ONCE(!_retries); \
226 static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
228 return __fsl_a008585_read_reg(cntp_tval_el0);
231 static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
233 return __fsl_a008585_read_reg(cntv_tval_el0);
236 static u64 notrace fsl_a008585_read_cntpct_el0(void)
238 return __fsl_a008585_read_reg(cntpct_el0);
241 static u64 notrace fsl_a008585_read_cntvct_el0(void)
243 return __fsl_a008585_read_reg(cntvct_el0);
247 #ifdef CONFIG_HISILICON_ERRATUM_161010101
249 * Verify whether the value of the second read is larger than the first by
250 * less than 32 is the only way to confirm the value is correct, so clear the
251 * lower 5 bits to check whether the difference is greater than 32 or not.
252 * Theoretically the erratum should not occur more than twice in succession
253 * when reading the system counter, but it is possible that some interrupts
254 * may lead to more than twice read errors, triggering the warning, so setting
255 * the number of retries far beyond the number of iterations the loop has been
258 #define __hisi_161010101_read_reg(reg) ({ \
263 _old = read_sysreg(reg); \
264 _new = read_sysreg(reg); \
266 } while (unlikely((_new - _old) >> 5) && _retries); \
268 WARN_ON_ONCE(!_retries); \
272 static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
274 return __hisi_161010101_read_reg(cntp_tval_el0);
277 static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
279 return __hisi_161010101_read_reg(cntv_tval_el0);
282 static u64 notrace hisi_161010101_read_cntpct_el0(void)
284 return __hisi_161010101_read_reg(cntpct_el0);
287 static u64 notrace hisi_161010101_read_cntvct_el0(void)
289 return __hisi_161010101_read_reg(cntvct_el0);
292 static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
294 * Note that trailing spaces are required to properly match
295 * the OEM table information.
299 .oem_table_id = "HIP05 ",
304 .oem_table_id = "HIP06 ",
309 .oem_table_id = "HIP07 ",
312 { /* Sentinel indicating the end of the OEM array */ },
316 #ifdef CONFIG_ARM64_ERRATUM_858921
317 static u64 notrace arm64_858921_read_cntpct_el0(void)
321 old = read_sysreg(cntpct_el0);
322 new = read_sysreg(cntpct_el0);
323 return (((old ^ new) >> 32) & 1) ? old : new;
326 static u64 notrace arm64_858921_read_cntvct_el0(void)
330 old = read_sysreg(cntvct_el0);
331 new = read_sysreg(cntvct_el0);
332 return (((old ^ new) >> 32) & 1) ? old : new;
336 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
338 * The low bits of the counter registers are indeterminate while bit 10 or
339 * greater is rolling over. Since the counter value can jump both backward
340 * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
341 * with all ones or all zeros in the low bits. Bound the loop by the maximum
342 * number of CPU cycles in 3 consecutive 24 MHz counter periods.
344 #define __sun50i_a64_read_reg(reg) ({ \
346 int _retries = 150; \
349 _val = read_sysreg(reg); \
351 } while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries); \
353 WARN_ON_ONCE(!_retries); \
357 static u64 notrace sun50i_a64_read_cntpct_el0(void)
359 return __sun50i_a64_read_reg(cntpct_el0);
362 static u64 notrace sun50i_a64_read_cntvct_el0(void)
364 return __sun50i_a64_read_reg(cntvct_el0);
367 static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
369 return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
372 static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
374 return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
378 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
379 DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
380 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
382 static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0);
384 static void erratum_set_next_event_tval_generic(const int access, unsigned long evt,
385 struct clock_event_device *clk)
390 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
391 ctrl |= ARCH_TIMER_CTRL_ENABLE;
392 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
394 if (access == ARCH_TIMER_PHYS_ACCESS) {
395 cval = evt + arch_counter_get_cntpct_stable();
396 write_sysreg(cval, cntp_cval_el0);
398 cval = evt + arch_counter_get_cntvct_stable();
399 write_sysreg(cval, cntv_cval_el0);
402 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
405 static __maybe_unused int erratum_set_next_event_tval_virt(unsigned long evt,
406 struct clock_event_device *clk)
408 erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
412 static __maybe_unused int erratum_set_next_event_tval_phys(unsigned long evt,
413 struct clock_event_device *clk)
415 erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
419 static const struct arch_timer_erratum_workaround ool_workarounds[] = {
420 #ifdef CONFIG_FSL_ERRATUM_A008585
422 .match_type = ate_match_dt,
423 .id = "fsl,erratum-a008585",
424 .desc = "Freescale erratum a005858",
425 .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
426 .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
427 .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
428 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
429 .set_next_event_phys = erratum_set_next_event_tval_phys,
430 .set_next_event_virt = erratum_set_next_event_tval_virt,
433 #ifdef CONFIG_HISILICON_ERRATUM_161010101
435 .match_type = ate_match_dt,
436 .id = "hisilicon,erratum-161010101",
437 .desc = "HiSilicon erratum 161010101",
438 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
439 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
440 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
441 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
442 .set_next_event_phys = erratum_set_next_event_tval_phys,
443 .set_next_event_virt = erratum_set_next_event_tval_virt,
446 .match_type = ate_match_acpi_oem_info,
447 .id = hisi_161010101_oem_info,
448 .desc = "HiSilicon erratum 161010101",
449 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
450 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
451 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
452 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
453 .set_next_event_phys = erratum_set_next_event_tval_phys,
454 .set_next_event_virt = erratum_set_next_event_tval_virt,
457 #ifdef CONFIG_ARM64_ERRATUM_858921
459 .match_type = ate_match_local_cap_id,
460 .id = (void *)ARM64_WORKAROUND_858921,
461 .desc = "ARM erratum 858921",
462 .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
463 .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
466 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
468 .match_type = ate_match_dt,
469 .id = "allwinner,erratum-unknown1",
470 .desc = "Allwinner erratum UNKNOWN1",
471 .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
472 .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
473 .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
474 .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
475 .set_next_event_phys = erratum_set_next_event_tval_phys,
476 .set_next_event_virt = erratum_set_next_event_tval_virt,
479 #ifdef CONFIG_ARM64_ERRATUM_1418040
481 .match_type = ate_match_local_cap_id,
482 .id = (void *)ARM64_WORKAROUND_1418040,
483 .desc = "ARM erratum 1418040",
484 .disable_compat_vdso = true,
489 typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
493 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
496 const struct device_node *np = arg;
498 return of_property_read_bool(np, wa->id);
502 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
505 return this_cpu_has_cap((uintptr_t)wa->id);
510 bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
513 static const struct ate_acpi_oem_info empty_oem_info = {};
514 const struct ate_acpi_oem_info *info = wa->id;
515 const struct acpi_table_header *table = arg;
517 /* Iterate over the ACPI OEM info array, looking for a match */
518 while (memcmp(info, &empty_oem_info, sizeof(*info))) {
519 if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
520 !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
521 info->oem_revision == table->oem_revision)
530 static const struct arch_timer_erratum_workaround *
531 arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
532 ate_match_fn_t match_fn,
537 for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
538 if (ool_workarounds[i].match_type != type)
541 if (match_fn(&ool_workarounds[i], arg))
542 return &ool_workarounds[i];
549 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
555 __this_cpu_write(timer_unstable_counter_workaround, wa);
557 for_each_possible_cpu(i)
558 per_cpu(timer_unstable_counter_workaround, i) = wa;
561 if (wa->read_cntvct_el0 || wa->read_cntpct_el0)
562 atomic_set(&timer_unstable_counter_workaround_in_use, 1);
565 * Don't use the vdso fastpath if errata require using the
566 * out-of-line counter accessor. We may change our mind pretty
567 * late in the game (with a per-CPU erratum, for example), so
568 * change both the default value and the vdso itself.
570 if (wa->read_cntvct_el0) {
571 clocksource_counter.archdata.clock_mode = VDSO_CLOCKMODE_NONE;
572 vdso_default = VDSO_CLOCKMODE_NONE;
573 } else if (wa->disable_compat_vdso && vdso_default != VDSO_CLOCKMODE_NONE) {
574 vdso_default = VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT;
575 clocksource_counter.archdata.clock_mode = vdso_default;
579 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
582 const struct arch_timer_erratum_workaround *wa, *__wa;
583 ate_match_fn_t match_fn = NULL;
588 match_fn = arch_timer_check_dt_erratum;
590 case ate_match_local_cap_id:
591 match_fn = arch_timer_check_local_cap_erratum;
594 case ate_match_acpi_oem_info:
595 match_fn = arch_timer_check_acpi_oem_erratum;
602 wa = arch_timer_iterate_errata(type, match_fn, arg);
606 __wa = __this_cpu_read(timer_unstable_counter_workaround);
607 if (__wa && wa != __wa)
608 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
609 wa->desc, __wa->desc);
614 arch_timer_enable_workaround(wa, local);
615 pr_info("Enabling %s workaround for %s\n",
616 local ? "local" : "global", wa->desc);
619 static bool arch_timer_this_cpu_has_cntvct_wa(void)
621 return has_erratum_handler(read_cntvct_el0);
624 static bool arch_timer_counter_has_wa(void)
626 return atomic_read(&timer_unstable_counter_workaround_in_use);
629 #define arch_timer_check_ool_workaround(t,a) do { } while(0)
630 #define arch_timer_this_cpu_has_cntvct_wa() ({false;})
631 #define arch_timer_counter_has_wa() ({false;})
632 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
634 static __always_inline irqreturn_t timer_handler(const int access,
635 struct clock_event_device *evt)
639 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
640 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
641 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
642 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
643 evt->event_handler(evt);
650 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
652 struct clock_event_device *evt = dev_id;
654 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
657 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
659 struct clock_event_device *evt = dev_id;
661 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
664 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
666 struct clock_event_device *evt = dev_id;
668 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
671 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
673 struct clock_event_device *evt = dev_id;
675 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
678 static __always_inline int timer_shutdown(const int access,
679 struct clock_event_device *clk)
683 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
684 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
685 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
690 static int arch_timer_shutdown_virt(struct clock_event_device *clk)
692 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
695 static int arch_timer_shutdown_phys(struct clock_event_device *clk)
697 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
700 static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
702 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
705 static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
707 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
710 static __always_inline void set_next_event(const int access, unsigned long evt,
711 struct clock_event_device *clk)
714 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
715 ctrl |= ARCH_TIMER_CTRL_ENABLE;
716 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
717 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
718 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
721 static int arch_timer_set_next_event_virt(unsigned long evt,
722 struct clock_event_device *clk)
724 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
728 static int arch_timer_set_next_event_phys(unsigned long evt,
729 struct clock_event_device *clk)
731 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
735 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
736 struct clock_event_device *clk)
738 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
742 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
743 struct clock_event_device *clk)
745 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
749 static void __arch_timer_setup(unsigned type,
750 struct clock_event_device *clk)
752 clk->features = CLOCK_EVT_FEAT_ONESHOT;
754 if (type == ARCH_TIMER_TYPE_CP15) {
755 typeof(clk->set_next_event) sne;
757 arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
759 if (arch_timer_c3stop)
760 clk->features |= CLOCK_EVT_FEAT_C3STOP;
761 clk->name = "arch_sys_timer";
763 clk->cpumask = cpumask_of(smp_processor_id());
764 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
765 switch (arch_timer_uses_ppi) {
766 case ARCH_TIMER_VIRT_PPI:
767 clk->set_state_shutdown = arch_timer_shutdown_virt;
768 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
769 sne = erratum_handler(set_next_event_virt);
771 case ARCH_TIMER_PHYS_SECURE_PPI:
772 case ARCH_TIMER_PHYS_NONSECURE_PPI:
773 case ARCH_TIMER_HYP_PPI:
774 clk->set_state_shutdown = arch_timer_shutdown_phys;
775 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
776 sne = erratum_handler(set_next_event_phys);
782 clk->set_next_event = sne;
784 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
785 clk->name = "arch_mem_timer";
787 clk->cpumask = cpu_possible_mask;
788 if (arch_timer_mem_use_virtual) {
789 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
790 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
791 clk->set_next_event =
792 arch_timer_set_next_event_virt_mem;
794 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
795 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
796 clk->set_next_event =
797 arch_timer_set_next_event_phys_mem;
801 clk->set_state_shutdown(clk);
803 clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
806 static void arch_timer_evtstrm_enable(int divider)
808 u32 cntkctl = arch_timer_get_cntkctl();
810 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
811 /* Set the divider and enable virtual event stream */
812 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
813 | ARCH_TIMER_VIRT_EVT_EN;
814 arch_timer_set_cntkctl(cntkctl);
815 arch_timer_set_evtstrm_feature();
816 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
819 static void arch_timer_configure_evtstream(void)
821 int evt_stream_div, lsb;
824 * As the event stream can at most be generated at half the frequency
825 * of the counter, use half the frequency when computing the divider.
827 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
830 * Find the closest power of two to the divisor. If the adjacent bit
831 * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
833 lsb = fls(evt_stream_div) - 1;
834 if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
837 /* enable event stream */
838 arch_timer_evtstrm_enable(max(0, min(lsb, 15)));
841 static void arch_counter_set_user_access(void)
843 u32 cntkctl = arch_timer_get_cntkctl();
845 /* Disable user access to the timers and both counters */
846 /* Also disable virtual event stream */
847 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
848 | ARCH_TIMER_USR_VT_ACCESS_EN
849 | ARCH_TIMER_USR_VCT_ACCESS_EN
850 | ARCH_TIMER_VIRT_EVT_EN
851 | ARCH_TIMER_USR_PCT_ACCESS_EN);
854 * Enable user access to the virtual counter if it doesn't
855 * need to be workaround. The vdso may have been already
858 if (arch_timer_this_cpu_has_cntvct_wa())
859 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
861 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
863 arch_timer_set_cntkctl(cntkctl);
866 static bool arch_timer_has_nonsecure_ppi(void)
868 return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
869 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
872 static u32 check_ppi_trigger(int irq)
874 u32 flags = irq_get_trigger_type(irq);
876 if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
877 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
878 pr_warn("WARNING: Please fix your firmware\n");
879 flags = IRQF_TRIGGER_LOW;
885 static int arch_timer_starting_cpu(unsigned int cpu)
887 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
890 __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
892 flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
893 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
895 if (arch_timer_has_nonsecure_ppi()) {
896 flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
897 enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
901 arch_counter_set_user_access();
903 arch_timer_configure_evtstream();
909 * For historical reasons, when probing with DT we use whichever (non-zero)
910 * rate was probed first, and don't verify that others match. If the first node
911 * probed has a clock-frequency property, this overrides the HW register.
913 static void arch_timer_of_configure_rate(u32 rate, struct device_node *np)
915 /* Who has more than one independent system counter? */
919 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
920 arch_timer_rate = rate;
922 /* Check the timer frequency. */
923 if (arch_timer_rate == 0)
924 pr_warn("frequency not available\n");
927 static void arch_timer_banner(unsigned type)
929 pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
930 type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
931 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
933 type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
934 (unsigned long)arch_timer_rate / 1000000,
935 (unsigned long)(arch_timer_rate / 10000) % 100,
936 type & ARCH_TIMER_TYPE_CP15 ?
937 (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
939 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
940 type & ARCH_TIMER_TYPE_MEM ?
941 arch_timer_mem_use_virtual ? "virt" : "phys" :
945 u32 arch_timer_get_rate(void)
947 return arch_timer_rate;
950 bool arch_timer_evtstrm_available(void)
953 * We might get called from a preemptible context. This is fine
954 * because availability of the event stream should be always the same
955 * for a preemptible context and context where we might resume a task.
957 return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
960 static u64 arch_counter_get_cntvct_mem(void)
962 u32 vct_lo, vct_hi, tmp_hi;
965 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
966 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
967 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
968 } while (vct_hi != tmp_hi);
970 return ((u64) vct_hi << 32) | vct_lo;
973 static struct arch_timer_kvm_info arch_timer_kvm_info;
975 struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
977 return &arch_timer_kvm_info;
980 static void __init arch_counter_register(unsigned type)
984 /* Register the CP15 based counter if we have one */
985 if (type & ARCH_TIMER_TYPE_CP15) {
988 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
989 arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) {
990 if (arch_timer_counter_has_wa())
991 rd = arch_counter_get_cntvct_stable;
993 rd = arch_counter_get_cntvct;
995 if (arch_timer_counter_has_wa())
996 rd = arch_counter_get_cntpct_stable;
998 rd = arch_counter_get_cntpct;
1001 arch_timer_read_counter = rd;
1002 clocksource_counter.archdata.clock_mode = vdso_default;
1004 arch_timer_read_counter = arch_counter_get_cntvct_mem;
1007 if (!arch_counter_suspend_stop)
1008 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1009 start_count = arch_timer_read_counter();
1010 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
1011 cyclecounter.mult = clocksource_counter.mult;
1012 cyclecounter.shift = clocksource_counter.shift;
1013 timecounter_init(&arch_timer_kvm_info.timecounter,
1014 &cyclecounter, start_count);
1016 /* 56 bits minimum, so we assume worst case rollover */
1017 sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
1020 static void arch_timer_stop(struct clock_event_device *clk)
1022 pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
1024 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
1025 if (arch_timer_has_nonsecure_ppi())
1026 disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1028 clk->set_state_shutdown(clk);
1031 static int arch_timer_dying_cpu(unsigned int cpu)
1033 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1035 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1037 arch_timer_stop(clk);
1041 #ifdef CONFIG_CPU_PM
1042 static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
1043 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
1044 unsigned long action, void *hcpu)
1046 if (action == CPU_PM_ENTER) {
1047 __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
1049 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1050 } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
1051 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
1053 if (arch_timer_have_evtstrm_feature())
1054 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
1059 static struct notifier_block arch_timer_cpu_pm_notifier = {
1060 .notifier_call = arch_timer_cpu_pm_notify,
1063 static int __init arch_timer_cpu_pm_init(void)
1065 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
1068 static void __init arch_timer_cpu_pm_deinit(void)
1070 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
1074 static int __init arch_timer_cpu_pm_init(void)
1079 static void __init arch_timer_cpu_pm_deinit(void)
1084 static int __init arch_timer_register(void)
1089 arch_timer_evt = alloc_percpu(struct clock_event_device);
1090 if (!arch_timer_evt) {
1095 ppi = arch_timer_ppi[arch_timer_uses_ppi];
1096 switch (arch_timer_uses_ppi) {
1097 case ARCH_TIMER_VIRT_PPI:
1098 err = request_percpu_irq(ppi, arch_timer_handler_virt,
1099 "arch_timer", arch_timer_evt);
1101 case ARCH_TIMER_PHYS_SECURE_PPI:
1102 case ARCH_TIMER_PHYS_NONSECURE_PPI:
1103 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1104 "arch_timer", arch_timer_evt);
1105 if (!err && arch_timer_has_nonsecure_ppi()) {
1106 ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1107 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1108 "arch_timer", arch_timer_evt);
1110 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1114 case ARCH_TIMER_HYP_PPI:
1115 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1116 "arch_timer", arch_timer_evt);
1123 pr_err("can't register interrupt %d (%d)\n", ppi, err);
1127 err = arch_timer_cpu_pm_init();
1129 goto out_unreg_notify;
1131 /* Register and immediately configure the timer on the boot CPU */
1132 err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1133 "clockevents/arm/arch_timer:starting",
1134 arch_timer_starting_cpu, arch_timer_dying_cpu);
1136 goto out_unreg_cpupm;
1140 arch_timer_cpu_pm_deinit();
1143 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1144 if (arch_timer_has_nonsecure_ppi())
1145 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1149 free_percpu(arch_timer_evt);
1154 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
1158 struct arch_timer *t;
1160 t = kzalloc(sizeof(*t), GFP_KERNEL);
1166 __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
1168 if (arch_timer_mem_use_virtual)
1169 func = arch_timer_handler_virt_mem;
1171 func = arch_timer_handler_phys_mem;
1173 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
1175 pr_err("Failed to request mem timer irq\n");
1182 static const struct of_device_id arch_timer_of_match[] __initconst = {
1183 { .compatible = "arm,armv7-timer", },
1184 { .compatible = "arm,armv8-timer", },
1188 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
1189 { .compatible = "arm,armv7-timer-mem", },
1193 static bool __init arch_timer_needs_of_probing(void)
1195 struct device_node *dn;
1196 bool needs_probing = false;
1197 unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1199 /* We have two timers, and both device-tree nodes are probed. */
1200 if ((arch_timers_present & mask) == mask)
1204 * Only one type of timer is probed,
1205 * check if we have another type of timer node in device-tree.
1207 if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
1208 dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
1210 dn = of_find_matching_node(NULL, arch_timer_of_match);
1212 if (dn && of_device_is_available(dn))
1213 needs_probing = true;
1217 return needs_probing;
1220 static int __init arch_timer_common_init(void)
1222 arch_timer_banner(arch_timers_present);
1223 arch_counter_register(arch_timers_present);
1224 return arch_timer_arch_init();
1228 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1230 * If HYP mode is available, we know that the physical timer
1231 * has been configured to be accessible from PL1. Use it, so
1232 * that a guest can use the virtual timer instead.
1234 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1235 * accesses to CNTP_*_EL1 registers are silently redirected to
1236 * their CNTHP_*_EL2 counterparts, and use a different PPI
1239 * If no interrupt provided for virtual timer, we'll have to
1240 * stick to the physical timer. It'd better be accessible...
1241 * For arm64 we never use the secure interrupt.
1243 * Return: a suitable PPI type for the current system.
1245 static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1247 if (is_kernel_in_hyp_mode())
1248 return ARCH_TIMER_HYP_PPI;
1250 if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1251 return ARCH_TIMER_VIRT_PPI;
1253 if (IS_ENABLED(CONFIG_ARM64))
1254 return ARCH_TIMER_PHYS_NONSECURE_PPI;
1256 return ARCH_TIMER_PHYS_SECURE_PPI;
1259 static void __init arch_timer_populate_kvm_info(void)
1261 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1262 if (is_kernel_in_hyp_mode())
1263 arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1266 static int __init arch_timer_of_init(struct device_node *np)
1271 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1272 pr_warn("multiple nodes in dt, skipping\n");
1276 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1277 for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++)
1278 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
1280 arch_timer_populate_kvm_info();
1282 rate = arch_timer_get_cntfrq();
1283 arch_timer_of_configure_rate(rate, np);
1285 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1287 /* Check for globally applicable workarounds */
1288 arch_timer_check_ool_workaround(ate_match_dt, np);
1291 * If we cannot rely on firmware initializing the timer registers then
1292 * we should use the physical timers instead.
1294 if (IS_ENABLED(CONFIG_ARM) &&
1295 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1296 arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1298 arch_timer_uses_ppi = arch_timer_select_ppi();
1300 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1301 pr_err("No interrupt available, giving up\n");
1305 /* On some systems, the counter stops ticking when in suspend. */
1306 arch_counter_suspend_stop = of_property_read_bool(np,
1307 "arm,no-tick-in-suspend");
1309 ret = arch_timer_register();
1313 if (arch_timer_needs_of_probing())
1316 return arch_timer_common_init();
1318 TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1319 TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1322 arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
1327 base = ioremap(frame->cntbase, frame->size);
1329 pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
1333 rate = readl_relaxed(base + CNTFRQ);
1340 static struct arch_timer_mem_frame * __init
1341 arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
1343 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1344 void __iomem *cntctlbase;
1348 cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
1350 pr_err("Can't map CNTCTLBase @ %pa\n",
1351 &timer_mem->cntctlbase);
1355 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1358 * Try to find a virtual capable frame. Otherwise fall back to a
1359 * physical capable frame.
1361 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1362 u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1363 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1365 frame = &timer_mem->frame[i];
1369 /* Try enabling everything, and see what sticks */
1370 writel_relaxed(cntacr, cntctlbase + CNTACR(i));
1371 cntacr = readl_relaxed(cntctlbase + CNTACR(i));
1373 if ((cnttidr & CNTTIDR_VIRT(i)) &&
1374 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1376 arch_timer_mem_use_virtual = true;
1380 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1386 iounmap(cntctlbase);
1392 arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
1397 if (arch_timer_mem_use_virtual)
1398 irq = frame->virt_irq;
1400 irq = frame->phys_irq;
1403 pr_err("Frame missing %s irq.\n",
1404 arch_timer_mem_use_virtual ? "virt" : "phys");
1408 if (!request_mem_region(frame->cntbase, frame->size,
1412 base = ioremap(frame->cntbase, frame->size);
1414 pr_err("Can't map frame's registers\n");
1418 ret = arch_timer_mem_register(base, irq);
1424 arch_counter_base = base;
1425 arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1430 static int __init arch_timer_mem_of_init(struct device_node *np)
1432 struct arch_timer_mem *timer_mem;
1433 struct arch_timer_mem_frame *frame;
1434 struct device_node *frame_node;
1435 struct resource res;
1439 timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
1443 if (of_address_to_resource(np, 0, &res))
1445 timer_mem->cntctlbase = res.start;
1446 timer_mem->size = resource_size(&res);
1448 for_each_available_child_of_node(np, frame_node) {
1450 struct arch_timer_mem_frame *frame;
1452 if (of_property_read_u32(frame_node, "frame-number", &n)) {
1453 pr_err(FW_BUG "Missing frame-number.\n");
1454 of_node_put(frame_node);
1457 if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1458 pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1459 ARCH_TIMER_MEM_MAX_FRAMES - 1);
1460 of_node_put(frame_node);
1463 frame = &timer_mem->frame[n];
1466 pr_err(FW_BUG "Duplicated frame-number.\n");
1467 of_node_put(frame_node);
1471 if (of_address_to_resource(frame_node, 0, &res)) {
1472 of_node_put(frame_node);
1475 frame->cntbase = res.start;
1476 frame->size = resource_size(&res);
1478 frame->virt_irq = irq_of_parse_and_map(frame_node,
1479 ARCH_TIMER_VIRT_SPI);
1480 frame->phys_irq = irq_of_parse_and_map(frame_node,
1481 ARCH_TIMER_PHYS_SPI);
1483 frame->valid = true;
1486 frame = arch_timer_mem_find_best_frame(timer_mem);
1488 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1489 &timer_mem->cntctlbase);
1494 rate = arch_timer_mem_frame_get_cntfrq(frame);
1495 arch_timer_of_configure_rate(rate, np);
1497 ret = arch_timer_mem_frame_register(frame);
1498 if (!ret && !arch_timer_needs_of_probing())
1499 ret = arch_timer_common_init();
1504 TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1505 arch_timer_mem_of_init);
1507 #ifdef CONFIG_ACPI_GTDT
1509 arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
1511 struct arch_timer_mem_frame *frame;
1515 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1516 frame = &timer_mem->frame[i];
1521 rate = arch_timer_mem_frame_get_cntfrq(frame);
1522 if (rate == arch_timer_rate)
1525 pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1527 (unsigned long)rate, (unsigned long)arch_timer_rate);
1535 static int __init arch_timer_mem_acpi_init(int platform_timer_count)
1537 struct arch_timer_mem *timers, *timer;
1538 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1539 int timer_count, i, ret = 0;
1541 timers = kcalloc(platform_timer_count, sizeof(*timers),
1546 ret = acpi_arch_timer_mem_init(timers, &timer_count);
1547 if (ret || !timer_count)
1551 * While unlikely, it's theoretically possible that none of the frames
1552 * in a timer expose the combination of feature we want.
1554 for (i = 0; i < timer_count; i++) {
1557 frame = arch_timer_mem_find_best_frame(timer);
1561 ret = arch_timer_mem_verify_cntfrq(timer);
1563 pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1567 if (!best_frame) /* implies !frame */
1569 * Only complain about missing suitable frames if we
1570 * haven't already found one in a previous iteration.
1572 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1573 &timer->cntctlbase);
1577 ret = arch_timer_mem_frame_register(best_frame);
1583 /* Initialize per-processor generic timer and memory-mapped timer(if present) */
1584 static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1586 int ret, platform_timer_count;
1588 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1589 pr_warn("already initialized, skipping\n");
1593 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1595 ret = acpi_gtdt_init(table, &platform_timer_count);
1597 pr_err("Failed to init GTDT table.\n");
1601 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1602 acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
1604 arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1605 acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
1607 arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1608 acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
1610 arch_timer_populate_kvm_info();
1613 * When probing via ACPI, we have no mechanism to override the sysreg
1614 * CNTFRQ value. This *must* be correct.
1616 arch_timer_rate = arch_timer_get_cntfrq();
1617 if (!arch_timer_rate) {
1618 pr_err(FW_BUG "frequency not available.\n");
1622 arch_timer_uses_ppi = arch_timer_select_ppi();
1623 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1624 pr_err("No interrupt available, giving up\n");
1628 /* Always-on capability */
1629 arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1631 /* Check for globally applicable workarounds */
1632 arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1634 ret = arch_timer_register();
1638 if (platform_timer_count &&
1639 arch_timer_mem_acpi_init(platform_timer_count))
1640 pr_err("Failed to initialize memory-mapped timer.\n");
1642 return arch_timer_common_init();
1644 TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);