1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/clocksource/arm_arch_timer.c
5 * Copyright (C) 2011 ARM Ltd.
9 #define pr_fmt(fmt) "arch_timer: " fmt
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/device.h>
14 #include <linux/smp.h>
15 #include <linux/cpu.h>
16 #include <linux/cpu_pm.h>
17 #include <linux/clockchips.h>
18 #include <linux/clocksource.h>
19 #include <linux/clocksource_ids.h>
20 #include <linux/interrupt.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_address.h>
24 #include <linux/slab.h>
25 #include <linux/sched/clock.h>
26 #include <linux/sched_clock.h>
27 #include <linux/acpi.h>
28 #include <linux/arm-smccc.h>
29 #include <linux/ptp_kvm.h>
31 #include <asm/arch_timer.h>
34 #include <clocksource/arm_arch_timer.h>
37 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
39 #define CNTACR(n) (0x40 + ((n) * 4))
40 #define CNTACR_RPCT BIT(0)
41 #define CNTACR_RVCT BIT(1)
42 #define CNTACR_RFRQ BIT(2)
43 #define CNTACR_RVOFF BIT(3)
44 #define CNTACR_RWVT BIT(4)
45 #define CNTACR_RWPT BIT(5)
47 #define CNTPCT_LO 0x00
48 #define CNTVCT_LO 0x08
50 #define CNTP_CVAL_LO 0x20
52 #define CNTV_CVAL_LO 0x30
56 * The minimum amount of time a generic counter is guaranteed to not roll over
59 #define MIN_ROLLOVER_SECS (40ULL * 365 * 24 * 3600)
61 static unsigned arch_timers_present __initdata;
65 struct clock_event_device evt;
68 static struct arch_timer *arch_timer_mem __ro_after_init;
70 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
72 static u32 arch_timer_rate __ro_after_init;
73 static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI] __ro_after_init;
75 static const char *arch_timer_ppi_names[ARCH_TIMER_MAX_TIMER_PPI] = {
76 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
77 [ARCH_TIMER_PHYS_NONSECURE_PPI] = "phys",
78 [ARCH_TIMER_VIRT_PPI] = "virt",
79 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
80 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
83 static struct clock_event_device __percpu *arch_timer_evt;
85 static enum arch_timer_ppi_nr arch_timer_uses_ppi __ro_after_init = ARCH_TIMER_VIRT_PPI;
86 static bool arch_timer_c3stop __ro_after_init;
87 static bool arch_timer_mem_use_virtual __ro_after_init;
88 static bool arch_counter_suspend_stop __ro_after_init;
89 #ifdef CONFIG_GENERIC_GETTIMEOFDAY
90 static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_ARCHTIMER;
92 static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_NONE;
93 #endif /* CONFIG_GENERIC_GETTIMEOFDAY */
95 static cpumask_t evtstrm_available = CPU_MASK_NONE;
96 static bool evtstrm_enable __ro_after_init = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
98 static int __init early_evtstrm_cfg(char *buf)
100 return strtobool(buf, &evtstrm_enable);
102 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
105 * Makes an educated guess at a valid counter width based on the Generic Timer
106 * specification. Of note:
107 * 1) the system counter is at least 56 bits wide
108 * 2) a roll-over time of not less than 40 years
110 * See 'ARM DDI 0487G.a D11.1.2 ("The system counter")' for more details.
112 static int arch_counter_get_width(void)
114 u64 min_cycles = MIN_ROLLOVER_SECS * arch_timer_rate;
116 /* guarantee the returned width is within the valid range */
117 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64);
121 * Architected system timer support.
124 static __always_inline
125 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,
126 struct clock_event_device *clk)
128 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
129 struct arch_timer *timer = to_arch_timer(clk);
131 case ARCH_TIMER_REG_CTRL:
132 writel_relaxed((u32)val, timer->base + CNTP_CTL);
134 case ARCH_TIMER_REG_CVAL:
136 * Not guaranteed to be atomic, so the timer
137 * must be disabled at this point.
139 writeq_relaxed(val, timer->base + CNTP_CVAL_LO);
144 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
145 struct arch_timer *timer = to_arch_timer(clk);
147 case ARCH_TIMER_REG_CTRL:
148 writel_relaxed((u32)val, timer->base + CNTV_CTL);
150 case ARCH_TIMER_REG_CVAL:
151 /* Same restriction as above */
152 writeq_relaxed(val, timer->base + CNTV_CVAL_LO);
158 arch_timer_reg_write_cp15(access, reg, val);
162 static __always_inline
163 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
164 struct clock_event_device *clk)
168 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
169 struct arch_timer *timer = to_arch_timer(clk);
171 case ARCH_TIMER_REG_CTRL:
172 val = readl_relaxed(timer->base + CNTP_CTL);
177 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
178 struct arch_timer *timer = to_arch_timer(clk);
180 case ARCH_TIMER_REG_CTRL:
181 val = readl_relaxed(timer->base + CNTV_CTL);
187 val = arch_timer_reg_read_cp15(access, reg);
193 static notrace u64 arch_counter_get_cntpct_stable(void)
195 return __arch_counter_get_cntpct_stable();
198 static notrace u64 arch_counter_get_cntpct(void)
200 return __arch_counter_get_cntpct();
203 static notrace u64 arch_counter_get_cntvct_stable(void)
205 return __arch_counter_get_cntvct_stable();
208 static notrace u64 arch_counter_get_cntvct(void)
210 return __arch_counter_get_cntvct();
214 * Default to cp15 based access because arm64 uses this function for
215 * sched_clock() before DT is probed and the cp15 method is guaranteed
216 * to exist on arm64. arm doesn't use this before DT is probed so even
217 * if we don't have the cp15 accessors we won't have a problem.
219 u64 (*arch_timer_read_counter)(void) __ro_after_init = arch_counter_get_cntvct;
220 EXPORT_SYMBOL_GPL(arch_timer_read_counter);
222 static u64 arch_counter_read(struct clocksource *cs)
224 return arch_timer_read_counter();
227 static u64 arch_counter_read_cc(const struct cyclecounter *cc)
229 return arch_timer_read_counter();
232 static struct clocksource clocksource_counter = {
233 .name = "arch_sys_counter",
234 .id = CSID_ARM_ARCH_COUNTER,
236 .read = arch_counter_read,
237 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
240 static struct cyclecounter cyclecounter __ro_after_init = {
241 .read = arch_counter_read_cc,
244 struct ate_acpi_oem_info {
245 char oem_id[ACPI_OEM_ID_SIZE + 1];
246 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
250 #ifdef CONFIG_FSL_ERRATUM_A008585
252 * The number of retries is an arbitrary value well beyond the highest number
253 * of iterations the loop has been observed to take.
255 #define __fsl_a008585_read_reg(reg) ({ \
257 int _retries = 200; \
260 _old = read_sysreg(reg); \
261 _new = read_sysreg(reg); \
263 } while (unlikely(_old != _new) && _retries); \
265 WARN_ON_ONCE(!_retries); \
269 static u64 notrace fsl_a008585_read_cntpct_el0(void)
271 return __fsl_a008585_read_reg(cntpct_el0);
274 static u64 notrace fsl_a008585_read_cntvct_el0(void)
276 return __fsl_a008585_read_reg(cntvct_el0);
280 #ifdef CONFIG_HISILICON_ERRATUM_161010101
282 * Verify whether the value of the second read is larger than the first by
283 * less than 32 is the only way to confirm the value is correct, so clear the
284 * lower 5 bits to check whether the difference is greater than 32 or not.
285 * Theoretically the erratum should not occur more than twice in succession
286 * when reading the system counter, but it is possible that some interrupts
287 * may lead to more than twice read errors, triggering the warning, so setting
288 * the number of retries far beyond the number of iterations the loop has been
291 #define __hisi_161010101_read_reg(reg) ({ \
296 _old = read_sysreg(reg); \
297 _new = read_sysreg(reg); \
299 } while (unlikely((_new - _old) >> 5) && _retries); \
301 WARN_ON_ONCE(!_retries); \
305 static u64 notrace hisi_161010101_read_cntpct_el0(void)
307 return __hisi_161010101_read_reg(cntpct_el0);
310 static u64 notrace hisi_161010101_read_cntvct_el0(void)
312 return __hisi_161010101_read_reg(cntvct_el0);
315 static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
317 * Note that trailing spaces are required to properly match
318 * the OEM table information.
322 .oem_table_id = "HIP05 ",
327 .oem_table_id = "HIP06 ",
332 .oem_table_id = "HIP07 ",
335 { /* Sentinel indicating the end of the OEM array */ },
339 #ifdef CONFIG_ARM64_ERRATUM_858921
340 static u64 notrace arm64_858921_read_cntpct_el0(void)
344 old = read_sysreg(cntpct_el0);
345 new = read_sysreg(cntpct_el0);
346 return (((old ^ new) >> 32) & 1) ? old : new;
349 static u64 notrace arm64_858921_read_cntvct_el0(void)
353 old = read_sysreg(cntvct_el0);
354 new = read_sysreg(cntvct_el0);
355 return (((old ^ new) >> 32) & 1) ? old : new;
359 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
361 * The low bits of the counter registers are indeterminate while bit 10 or
362 * greater is rolling over. Since the counter value can jump both backward
363 * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
364 * with all ones or all zeros in the low bits. Bound the loop by the maximum
365 * number of CPU cycles in 3 consecutive 24 MHz counter periods.
367 #define __sun50i_a64_read_reg(reg) ({ \
369 int _retries = 150; \
372 _val = read_sysreg(reg); \
374 } while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries); \
376 WARN_ON_ONCE(!_retries); \
380 static u64 notrace sun50i_a64_read_cntpct_el0(void)
382 return __sun50i_a64_read_reg(cntpct_el0);
385 static u64 notrace sun50i_a64_read_cntvct_el0(void)
387 return __sun50i_a64_read_reg(cntvct_el0);
391 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
392 DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
393 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
395 static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0);
398 * Force the inlining of this function so that the register accesses
399 * can be themselves correctly inlined.
401 static __always_inline
402 void erratum_set_next_event_generic(const int access, unsigned long evt,
403 struct clock_event_device *clk)
408 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
409 ctrl |= ARCH_TIMER_CTRL_ENABLE;
410 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
412 if (access == ARCH_TIMER_PHYS_ACCESS) {
413 cval = evt + arch_counter_get_cntpct_stable();
414 write_sysreg(cval, cntp_cval_el0);
416 cval = evt + arch_counter_get_cntvct_stable();
417 write_sysreg(cval, cntv_cval_el0);
420 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
423 static __maybe_unused int erratum_set_next_event_virt(unsigned long evt,
424 struct clock_event_device *clk)
426 erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
430 static __maybe_unused int erratum_set_next_event_phys(unsigned long evt,
431 struct clock_event_device *clk)
433 erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
437 static const struct arch_timer_erratum_workaround ool_workarounds[] = {
438 #ifdef CONFIG_FSL_ERRATUM_A008585
440 .match_type = ate_match_dt,
441 .id = "fsl,erratum-a008585",
442 .desc = "Freescale erratum a005858",
443 .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
444 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
445 .set_next_event_phys = erratum_set_next_event_phys,
446 .set_next_event_virt = erratum_set_next_event_virt,
449 #ifdef CONFIG_HISILICON_ERRATUM_161010101
451 .match_type = ate_match_dt,
452 .id = "hisilicon,erratum-161010101",
453 .desc = "HiSilicon erratum 161010101",
454 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
455 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
456 .set_next_event_phys = erratum_set_next_event_phys,
457 .set_next_event_virt = erratum_set_next_event_virt,
460 .match_type = ate_match_acpi_oem_info,
461 .id = hisi_161010101_oem_info,
462 .desc = "HiSilicon erratum 161010101",
463 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
464 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
465 .set_next_event_phys = erratum_set_next_event_phys,
466 .set_next_event_virt = erratum_set_next_event_virt,
469 #ifdef CONFIG_ARM64_ERRATUM_858921
471 .match_type = ate_match_local_cap_id,
472 .id = (void *)ARM64_WORKAROUND_858921,
473 .desc = "ARM erratum 858921",
474 .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
475 .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
476 .set_next_event_phys = erratum_set_next_event_phys,
477 .set_next_event_virt = erratum_set_next_event_virt,
480 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
482 .match_type = ate_match_dt,
483 .id = "allwinner,erratum-unknown1",
484 .desc = "Allwinner erratum UNKNOWN1",
485 .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
486 .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
487 .set_next_event_phys = erratum_set_next_event_phys,
488 .set_next_event_virt = erratum_set_next_event_virt,
491 #ifdef CONFIG_ARM64_ERRATUM_1418040
493 .match_type = ate_match_local_cap_id,
494 .id = (void *)ARM64_WORKAROUND_1418040,
495 .desc = "ARM erratum 1418040",
496 .disable_compat_vdso = true,
501 typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
505 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
508 const struct device_node *np = arg;
510 return of_property_read_bool(np, wa->id);
514 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
517 return this_cpu_has_cap((uintptr_t)wa->id);
522 bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
525 static const struct ate_acpi_oem_info empty_oem_info = {};
526 const struct ate_acpi_oem_info *info = wa->id;
527 const struct acpi_table_header *table = arg;
529 /* Iterate over the ACPI OEM info array, looking for a match */
530 while (memcmp(info, &empty_oem_info, sizeof(*info))) {
531 if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
532 !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
533 info->oem_revision == table->oem_revision)
542 static const struct arch_timer_erratum_workaround *
543 arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
544 ate_match_fn_t match_fn,
549 for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
550 if (ool_workarounds[i].match_type != type)
553 if (match_fn(&ool_workarounds[i], arg))
554 return &ool_workarounds[i];
561 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
567 __this_cpu_write(timer_unstable_counter_workaround, wa);
569 for_each_possible_cpu(i)
570 per_cpu(timer_unstable_counter_workaround, i) = wa;
573 if (wa->read_cntvct_el0 || wa->read_cntpct_el0)
574 atomic_set(&timer_unstable_counter_workaround_in_use, 1);
577 * Don't use the vdso fastpath if errata require using the
578 * out-of-line counter accessor. We may change our mind pretty
579 * late in the game (with a per-CPU erratum, for example), so
580 * change both the default value and the vdso itself.
582 if (wa->read_cntvct_el0) {
583 clocksource_counter.vdso_clock_mode = VDSO_CLOCKMODE_NONE;
584 vdso_default = VDSO_CLOCKMODE_NONE;
585 } else if (wa->disable_compat_vdso && vdso_default != VDSO_CLOCKMODE_NONE) {
586 vdso_default = VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT;
587 clocksource_counter.vdso_clock_mode = vdso_default;
591 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
594 const struct arch_timer_erratum_workaround *wa, *__wa;
595 ate_match_fn_t match_fn = NULL;
600 match_fn = arch_timer_check_dt_erratum;
602 case ate_match_local_cap_id:
603 match_fn = arch_timer_check_local_cap_erratum;
606 case ate_match_acpi_oem_info:
607 match_fn = arch_timer_check_acpi_oem_erratum;
614 wa = arch_timer_iterate_errata(type, match_fn, arg);
618 __wa = __this_cpu_read(timer_unstable_counter_workaround);
619 if (__wa && wa != __wa)
620 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
621 wa->desc, __wa->desc);
626 arch_timer_enable_workaround(wa, local);
627 pr_info("Enabling %s workaround for %s\n",
628 local ? "local" : "global", wa->desc);
631 static bool arch_timer_this_cpu_has_cntvct_wa(void)
633 return has_erratum_handler(read_cntvct_el0);
636 static bool arch_timer_counter_has_wa(void)
638 return atomic_read(&timer_unstable_counter_workaround_in_use);
641 #define arch_timer_check_ool_workaround(t,a) do { } while(0)
642 #define arch_timer_this_cpu_has_cntvct_wa() ({false;})
643 #define arch_timer_counter_has_wa() ({false;})
644 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
646 static __always_inline irqreturn_t timer_handler(const int access,
647 struct clock_event_device *evt)
651 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
652 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
653 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
654 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
655 evt->event_handler(evt);
662 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
664 struct clock_event_device *evt = dev_id;
666 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
669 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
671 struct clock_event_device *evt = dev_id;
673 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
676 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
678 struct clock_event_device *evt = dev_id;
680 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
683 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
685 struct clock_event_device *evt = dev_id;
687 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
690 static __always_inline int timer_shutdown(const int access,
691 struct clock_event_device *clk)
695 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
696 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
697 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
702 static int arch_timer_shutdown_virt(struct clock_event_device *clk)
704 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
707 static int arch_timer_shutdown_phys(struct clock_event_device *clk)
709 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
712 static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
714 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
717 static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
719 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
722 static __always_inline void set_next_event(const int access, unsigned long evt,
723 struct clock_event_device *clk)
728 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
729 ctrl |= ARCH_TIMER_CTRL_ENABLE;
730 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
732 if (access == ARCH_TIMER_PHYS_ACCESS)
733 cnt = __arch_counter_get_cntpct();
735 cnt = __arch_counter_get_cntvct();
737 arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk);
738 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
741 static int arch_timer_set_next_event_virt(unsigned long evt,
742 struct clock_event_device *clk)
744 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
748 static int arch_timer_set_next_event_phys(unsigned long evt,
749 struct clock_event_device *clk)
751 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
755 static u64 arch_counter_get_cnt_mem(struct arch_timer *t, int offset_lo)
757 u32 cnt_lo, cnt_hi, tmp_hi;
760 cnt_hi = readl_relaxed(t->base + offset_lo + 4);
761 cnt_lo = readl_relaxed(t->base + offset_lo);
762 tmp_hi = readl_relaxed(t->base + offset_lo + 4);
763 } while (cnt_hi != tmp_hi);
765 return ((u64) cnt_hi << 32) | cnt_lo;
768 static __always_inline void set_next_event_mem(const int access, unsigned long evt,
769 struct clock_event_device *clk)
771 struct arch_timer *timer = to_arch_timer(clk);
775 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
776 ctrl |= ARCH_TIMER_CTRL_ENABLE;
777 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
779 if (access == ARCH_TIMER_MEM_VIRT_ACCESS)
780 cnt = arch_counter_get_cnt_mem(timer, CNTVCT_LO);
782 cnt = arch_counter_get_cnt_mem(timer, CNTPCT_LO);
784 arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk);
785 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
788 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
789 struct clock_event_device *clk)
791 set_next_event_mem(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
795 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
796 struct clock_event_device *clk)
798 set_next_event_mem(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
802 static u64 __arch_timer_check_delta(void)
805 const struct midr_range broken_cval_midrs[] = {
807 * XGene-1 implements CVAL in terms of TVAL, meaning
808 * that the maximum timer range is 32bit. Shame on them.
810 * Note that TVAL is signed, thus has only 31 of its
811 * 32 bits to express magnitude.
813 MIDR_ALL_VERSIONS(MIDR_CPU_MODEL(ARM_CPU_IMP_APM,
814 APM_CPU_PART_POTENZA)),
818 if (is_midr_in_range_list(read_cpuid_id(), broken_cval_midrs)) {
819 pr_warn_once("Broken CNTx_CVAL_EL1, using 31 bit TVAL instead.\n");
820 return CLOCKSOURCE_MASK(31);
823 return CLOCKSOURCE_MASK(arch_counter_get_width());
826 static void __arch_timer_setup(unsigned type,
827 struct clock_event_device *clk)
831 clk->features = CLOCK_EVT_FEAT_ONESHOT;
833 if (type == ARCH_TIMER_TYPE_CP15) {
834 typeof(clk->set_next_event) sne;
836 arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
838 if (arch_timer_c3stop)
839 clk->features |= CLOCK_EVT_FEAT_C3STOP;
840 clk->name = "arch_sys_timer";
842 clk->cpumask = cpumask_of(smp_processor_id());
843 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
844 switch (arch_timer_uses_ppi) {
845 case ARCH_TIMER_VIRT_PPI:
846 clk->set_state_shutdown = arch_timer_shutdown_virt;
847 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
848 sne = erratum_handler(set_next_event_virt);
850 case ARCH_TIMER_PHYS_SECURE_PPI:
851 case ARCH_TIMER_PHYS_NONSECURE_PPI:
852 case ARCH_TIMER_HYP_PPI:
853 clk->set_state_shutdown = arch_timer_shutdown_phys;
854 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
855 sne = erratum_handler(set_next_event_phys);
861 clk->set_next_event = sne;
862 max_delta = __arch_timer_check_delta();
864 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
865 clk->name = "arch_mem_timer";
867 clk->cpumask = cpu_possible_mask;
868 if (arch_timer_mem_use_virtual) {
869 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
870 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
871 clk->set_next_event =
872 arch_timer_set_next_event_virt_mem;
874 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
875 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
876 clk->set_next_event =
877 arch_timer_set_next_event_phys_mem;
880 max_delta = CLOCKSOURCE_MASK(56);
883 clk->set_state_shutdown(clk);
885 clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta);
888 static void arch_timer_evtstrm_enable(unsigned int divider)
890 u32 cntkctl = arch_timer_get_cntkctl();
893 /* ECV is likely to require a large divider. Use the EVNTIS flag. */
894 if (cpus_have_const_cap(ARM64_HAS_ECV) && divider > 15) {
895 cntkctl |= ARCH_TIMER_EVT_INTERVAL_SCALE;
900 divider = min(divider, 15U);
901 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
902 /* Set the divider and enable virtual event stream */
903 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
904 | ARCH_TIMER_VIRT_EVT_EN;
905 arch_timer_set_cntkctl(cntkctl);
906 arch_timer_set_evtstrm_feature();
907 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
910 static void arch_timer_configure_evtstream(void)
912 int evt_stream_div, lsb;
915 * As the event stream can at most be generated at half the frequency
916 * of the counter, use half the frequency when computing the divider.
918 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
921 * Find the closest power of two to the divisor. If the adjacent bit
922 * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
924 lsb = fls(evt_stream_div) - 1;
925 if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
928 /* enable event stream */
929 arch_timer_evtstrm_enable(max(0, lsb));
932 static void arch_counter_set_user_access(void)
934 u32 cntkctl = arch_timer_get_cntkctl();
936 /* Disable user access to the timers and both counters */
937 /* Also disable virtual event stream */
938 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
939 | ARCH_TIMER_USR_VT_ACCESS_EN
940 | ARCH_TIMER_USR_VCT_ACCESS_EN
941 | ARCH_TIMER_VIRT_EVT_EN
942 | ARCH_TIMER_USR_PCT_ACCESS_EN);
945 * Enable user access to the virtual counter if it doesn't
946 * need to be workaround. The vdso may have been already
949 if (arch_timer_this_cpu_has_cntvct_wa())
950 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
952 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
954 arch_timer_set_cntkctl(cntkctl);
957 static bool arch_timer_has_nonsecure_ppi(void)
959 return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
960 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
963 static u32 check_ppi_trigger(int irq)
965 u32 flags = irq_get_trigger_type(irq);
967 if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
968 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
969 pr_warn("WARNING: Please fix your firmware\n");
970 flags = IRQF_TRIGGER_LOW;
976 static int arch_timer_starting_cpu(unsigned int cpu)
978 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
981 __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
983 flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
984 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
986 if (arch_timer_has_nonsecure_ppi()) {
987 flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
988 enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
992 arch_counter_set_user_access();
994 arch_timer_configure_evtstream();
999 static int validate_timer_rate(void)
1001 if (!arch_timer_rate)
1004 /* Arch timer frequency < 1MHz can cause trouble */
1005 WARN_ON(arch_timer_rate < 1000000);
1011 * For historical reasons, when probing with DT we use whichever (non-zero)
1012 * rate was probed first, and don't verify that others match. If the first node
1013 * probed has a clock-frequency property, this overrides the HW register.
1015 static void __init arch_timer_of_configure_rate(u32 rate, struct device_node *np)
1017 /* Who has more than one independent system counter? */
1018 if (arch_timer_rate)
1021 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
1022 arch_timer_rate = rate;
1024 /* Check the timer frequency. */
1025 if (validate_timer_rate())
1026 pr_warn("frequency not available\n");
1029 static void __init arch_timer_banner(unsigned type)
1031 pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
1032 type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
1033 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
1035 type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
1036 (unsigned long)arch_timer_rate / 1000000,
1037 (unsigned long)(arch_timer_rate / 10000) % 100,
1038 type & ARCH_TIMER_TYPE_CP15 ?
1039 (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
1041 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
1042 type & ARCH_TIMER_TYPE_MEM ?
1043 arch_timer_mem_use_virtual ? "virt" : "phys" :
1047 u32 arch_timer_get_rate(void)
1049 return arch_timer_rate;
1052 bool arch_timer_evtstrm_available(void)
1055 * We might get called from a preemptible context. This is fine
1056 * because availability of the event stream should be always the same
1057 * for a preemptible context and context where we might resume a task.
1059 return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
1062 static u64 arch_counter_get_cntvct_mem(void)
1064 return arch_counter_get_cnt_mem(arch_timer_mem, CNTVCT_LO);
1067 static struct arch_timer_kvm_info arch_timer_kvm_info;
1069 struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
1071 return &arch_timer_kvm_info;
1074 static void __init arch_counter_register(unsigned type)
1079 /* Register the CP15 based counter if we have one */
1080 if (type & ARCH_TIMER_TYPE_CP15) {
1083 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
1084 arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) {
1085 if (arch_timer_counter_has_wa())
1086 rd = arch_counter_get_cntvct_stable;
1088 rd = arch_counter_get_cntvct;
1090 if (arch_timer_counter_has_wa())
1091 rd = arch_counter_get_cntpct_stable;
1093 rd = arch_counter_get_cntpct;
1096 arch_timer_read_counter = rd;
1097 clocksource_counter.vdso_clock_mode = vdso_default;
1099 arch_timer_read_counter = arch_counter_get_cntvct_mem;
1102 width = arch_counter_get_width();
1103 clocksource_counter.mask = CLOCKSOURCE_MASK(width);
1104 cyclecounter.mask = CLOCKSOURCE_MASK(width);
1106 if (!arch_counter_suspend_stop)
1107 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1108 start_count = arch_timer_read_counter();
1109 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
1110 cyclecounter.mult = clocksource_counter.mult;
1111 cyclecounter.shift = clocksource_counter.shift;
1112 timecounter_init(&arch_timer_kvm_info.timecounter,
1113 &cyclecounter, start_count);
1115 sched_clock_register(arch_timer_read_counter, width, arch_timer_rate);
1118 static void arch_timer_stop(struct clock_event_device *clk)
1120 pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
1122 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
1123 if (arch_timer_has_nonsecure_ppi())
1124 disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1126 clk->set_state_shutdown(clk);
1129 static int arch_timer_dying_cpu(unsigned int cpu)
1131 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1133 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1135 arch_timer_stop(clk);
1139 #ifdef CONFIG_CPU_PM
1140 static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
1141 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
1142 unsigned long action, void *hcpu)
1144 if (action == CPU_PM_ENTER) {
1145 __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
1147 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1148 } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
1149 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
1151 if (arch_timer_have_evtstrm_feature())
1152 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
1157 static struct notifier_block arch_timer_cpu_pm_notifier = {
1158 .notifier_call = arch_timer_cpu_pm_notify,
1161 static int __init arch_timer_cpu_pm_init(void)
1163 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
1166 static void __init arch_timer_cpu_pm_deinit(void)
1168 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
1172 static int __init arch_timer_cpu_pm_init(void)
1177 static void __init arch_timer_cpu_pm_deinit(void)
1182 static int __init arch_timer_register(void)
1187 arch_timer_evt = alloc_percpu(struct clock_event_device);
1188 if (!arch_timer_evt) {
1193 ppi = arch_timer_ppi[arch_timer_uses_ppi];
1194 switch (arch_timer_uses_ppi) {
1195 case ARCH_TIMER_VIRT_PPI:
1196 err = request_percpu_irq(ppi, arch_timer_handler_virt,
1197 "arch_timer", arch_timer_evt);
1199 case ARCH_TIMER_PHYS_SECURE_PPI:
1200 case ARCH_TIMER_PHYS_NONSECURE_PPI:
1201 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1202 "arch_timer", arch_timer_evt);
1203 if (!err && arch_timer_has_nonsecure_ppi()) {
1204 ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1205 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1206 "arch_timer", arch_timer_evt);
1208 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1212 case ARCH_TIMER_HYP_PPI:
1213 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1214 "arch_timer", arch_timer_evt);
1221 pr_err("can't register interrupt %d (%d)\n", ppi, err);
1225 err = arch_timer_cpu_pm_init();
1227 goto out_unreg_notify;
1229 /* Register and immediately configure the timer on the boot CPU */
1230 err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1231 "clockevents/arm/arch_timer:starting",
1232 arch_timer_starting_cpu, arch_timer_dying_cpu);
1234 goto out_unreg_cpupm;
1238 arch_timer_cpu_pm_deinit();
1241 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1242 if (arch_timer_has_nonsecure_ppi())
1243 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1247 free_percpu(arch_timer_evt);
1252 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
1257 arch_timer_mem = kzalloc(sizeof(*arch_timer_mem), GFP_KERNEL);
1258 if (!arch_timer_mem)
1261 arch_timer_mem->base = base;
1262 arch_timer_mem->evt.irq = irq;
1263 __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &arch_timer_mem->evt);
1265 if (arch_timer_mem_use_virtual)
1266 func = arch_timer_handler_virt_mem;
1268 func = arch_timer_handler_phys_mem;
1270 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &arch_timer_mem->evt);
1272 pr_err("Failed to request mem timer irq\n");
1273 kfree(arch_timer_mem);
1274 arch_timer_mem = NULL;
1280 static const struct of_device_id arch_timer_of_match[] __initconst = {
1281 { .compatible = "arm,armv7-timer", },
1282 { .compatible = "arm,armv8-timer", },
1286 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
1287 { .compatible = "arm,armv7-timer-mem", },
1291 static bool __init arch_timer_needs_of_probing(void)
1293 struct device_node *dn;
1294 bool needs_probing = false;
1295 unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1297 /* We have two timers, and both device-tree nodes are probed. */
1298 if ((arch_timers_present & mask) == mask)
1302 * Only one type of timer is probed,
1303 * check if we have another type of timer node in device-tree.
1305 if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
1306 dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
1308 dn = of_find_matching_node(NULL, arch_timer_of_match);
1310 if (dn && of_device_is_available(dn))
1311 needs_probing = true;
1315 return needs_probing;
1318 static int __init arch_timer_common_init(void)
1320 arch_timer_banner(arch_timers_present);
1321 arch_counter_register(arch_timers_present);
1322 return arch_timer_arch_init();
1326 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1328 * If HYP mode is available, we know that the physical timer
1329 * has been configured to be accessible from PL1. Use it, so
1330 * that a guest can use the virtual timer instead.
1332 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1333 * accesses to CNTP_*_EL1 registers are silently redirected to
1334 * their CNTHP_*_EL2 counterparts, and use a different PPI
1337 * If no interrupt provided for virtual timer, we'll have to
1338 * stick to the physical timer. It'd better be accessible...
1339 * For arm64 we never use the secure interrupt.
1341 * Return: a suitable PPI type for the current system.
1343 static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1345 if (is_kernel_in_hyp_mode())
1346 return ARCH_TIMER_HYP_PPI;
1348 if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1349 return ARCH_TIMER_VIRT_PPI;
1351 if (IS_ENABLED(CONFIG_ARM64))
1352 return ARCH_TIMER_PHYS_NONSECURE_PPI;
1354 return ARCH_TIMER_PHYS_SECURE_PPI;
1357 static void __init arch_timer_populate_kvm_info(void)
1359 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1360 if (is_kernel_in_hyp_mode())
1361 arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1364 static int __init arch_timer_of_init(struct device_node *np)
1370 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1371 pr_warn("multiple nodes in dt, skipping\n");
1375 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1377 has_names = of_property_read_bool(np, "interrupt-names");
1379 for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++) {
1381 irq = of_irq_get_byname(np, arch_timer_ppi_names[i]);
1383 irq = of_irq_get(np, i);
1385 arch_timer_ppi[i] = irq;
1388 arch_timer_populate_kvm_info();
1390 rate = arch_timer_get_cntfrq();
1391 arch_timer_of_configure_rate(rate, np);
1393 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1395 /* Check for globally applicable workarounds */
1396 arch_timer_check_ool_workaround(ate_match_dt, np);
1399 * If we cannot rely on firmware initializing the timer registers then
1400 * we should use the physical timers instead.
1402 if (IS_ENABLED(CONFIG_ARM) &&
1403 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1404 arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1406 arch_timer_uses_ppi = arch_timer_select_ppi();
1408 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1409 pr_err("No interrupt available, giving up\n");
1413 /* On some systems, the counter stops ticking when in suspend. */
1414 arch_counter_suspend_stop = of_property_read_bool(np,
1415 "arm,no-tick-in-suspend");
1417 ret = arch_timer_register();
1421 if (arch_timer_needs_of_probing())
1424 return arch_timer_common_init();
1426 TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1427 TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1430 arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
1435 base = ioremap(frame->cntbase, frame->size);
1437 pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
1441 rate = readl_relaxed(base + CNTFRQ);
1448 static struct arch_timer_mem_frame * __init
1449 arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
1451 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1452 void __iomem *cntctlbase;
1456 cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
1458 pr_err("Can't map CNTCTLBase @ %pa\n",
1459 &timer_mem->cntctlbase);
1463 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1466 * Try to find a virtual capable frame. Otherwise fall back to a
1467 * physical capable frame.
1469 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1470 u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1471 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1473 frame = &timer_mem->frame[i];
1477 /* Try enabling everything, and see what sticks */
1478 writel_relaxed(cntacr, cntctlbase + CNTACR(i));
1479 cntacr = readl_relaxed(cntctlbase + CNTACR(i));
1481 if ((cnttidr & CNTTIDR_VIRT(i)) &&
1482 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1484 arch_timer_mem_use_virtual = true;
1488 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1494 iounmap(cntctlbase);
1500 arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
1505 if (arch_timer_mem_use_virtual)
1506 irq = frame->virt_irq;
1508 irq = frame->phys_irq;
1511 pr_err("Frame missing %s irq.\n",
1512 arch_timer_mem_use_virtual ? "virt" : "phys");
1516 if (!request_mem_region(frame->cntbase, frame->size,
1520 base = ioremap(frame->cntbase, frame->size);
1522 pr_err("Can't map frame's registers\n");
1526 ret = arch_timer_mem_register(base, irq);
1532 arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1537 static int __init arch_timer_mem_of_init(struct device_node *np)
1539 struct arch_timer_mem *timer_mem;
1540 struct arch_timer_mem_frame *frame;
1541 struct device_node *frame_node;
1542 struct resource res;
1546 timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
1550 if (of_address_to_resource(np, 0, &res))
1552 timer_mem->cntctlbase = res.start;
1553 timer_mem->size = resource_size(&res);
1555 for_each_available_child_of_node(np, frame_node) {
1557 struct arch_timer_mem_frame *frame;
1559 if (of_property_read_u32(frame_node, "frame-number", &n)) {
1560 pr_err(FW_BUG "Missing frame-number.\n");
1561 of_node_put(frame_node);
1564 if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1565 pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1566 ARCH_TIMER_MEM_MAX_FRAMES - 1);
1567 of_node_put(frame_node);
1570 frame = &timer_mem->frame[n];
1573 pr_err(FW_BUG "Duplicated frame-number.\n");
1574 of_node_put(frame_node);
1578 if (of_address_to_resource(frame_node, 0, &res)) {
1579 of_node_put(frame_node);
1582 frame->cntbase = res.start;
1583 frame->size = resource_size(&res);
1585 frame->virt_irq = irq_of_parse_and_map(frame_node,
1586 ARCH_TIMER_VIRT_SPI);
1587 frame->phys_irq = irq_of_parse_and_map(frame_node,
1588 ARCH_TIMER_PHYS_SPI);
1590 frame->valid = true;
1593 frame = arch_timer_mem_find_best_frame(timer_mem);
1595 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1596 &timer_mem->cntctlbase);
1601 rate = arch_timer_mem_frame_get_cntfrq(frame);
1602 arch_timer_of_configure_rate(rate, np);
1604 ret = arch_timer_mem_frame_register(frame);
1605 if (!ret && !arch_timer_needs_of_probing())
1606 ret = arch_timer_common_init();
1611 TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1612 arch_timer_mem_of_init);
1614 #ifdef CONFIG_ACPI_GTDT
1616 arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
1618 struct arch_timer_mem_frame *frame;
1622 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1623 frame = &timer_mem->frame[i];
1628 rate = arch_timer_mem_frame_get_cntfrq(frame);
1629 if (rate == arch_timer_rate)
1632 pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1634 (unsigned long)rate, (unsigned long)arch_timer_rate);
1642 static int __init arch_timer_mem_acpi_init(int platform_timer_count)
1644 struct arch_timer_mem *timers, *timer;
1645 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1646 int timer_count, i, ret = 0;
1648 timers = kcalloc(platform_timer_count, sizeof(*timers),
1653 ret = acpi_arch_timer_mem_init(timers, &timer_count);
1654 if (ret || !timer_count)
1658 * While unlikely, it's theoretically possible that none of the frames
1659 * in a timer expose the combination of feature we want.
1661 for (i = 0; i < timer_count; i++) {
1664 frame = arch_timer_mem_find_best_frame(timer);
1668 ret = arch_timer_mem_verify_cntfrq(timer);
1670 pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1674 if (!best_frame) /* implies !frame */
1676 * Only complain about missing suitable frames if we
1677 * haven't already found one in a previous iteration.
1679 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1680 &timer->cntctlbase);
1684 ret = arch_timer_mem_frame_register(best_frame);
1690 /* Initialize per-processor generic timer and memory-mapped timer(if present) */
1691 static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1693 int ret, platform_timer_count;
1695 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1696 pr_warn("already initialized, skipping\n");
1700 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1702 ret = acpi_gtdt_init(table, &platform_timer_count);
1706 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1707 acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
1709 arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1710 acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
1712 arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1713 acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
1715 arch_timer_populate_kvm_info();
1718 * When probing via ACPI, we have no mechanism to override the sysreg
1719 * CNTFRQ value. This *must* be correct.
1721 arch_timer_rate = arch_timer_get_cntfrq();
1722 ret = validate_timer_rate();
1724 pr_err(FW_BUG "frequency not available.\n");
1728 arch_timer_uses_ppi = arch_timer_select_ppi();
1729 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1730 pr_err("No interrupt available, giving up\n");
1734 /* Always-on capability */
1735 arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1737 /* Check for globally applicable workarounds */
1738 arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1740 ret = arch_timer_register();
1744 if (platform_timer_count &&
1745 arch_timer_mem_acpi_init(platform_timer_count))
1746 pr_err("Failed to initialize memory-mapped timer.\n");
1748 return arch_timer_common_init();
1750 TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
1753 int kvm_arch_ptp_get_crosststamp(u64 *cycle, struct timespec64 *ts,
1754 struct clocksource **cs)
1756 struct arm_smccc_res hvc_res;
1760 if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY))
1763 if (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
1764 ptp_counter = KVM_PTP_VIRT_COUNTER;
1766 ptp_counter = KVM_PTP_PHYS_COUNTER;
1768 arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID,
1769 ptp_counter, &hvc_res);
1771 if ((int)(hvc_res.a0) < 0)
1774 ktime = (u64)hvc_res.a0 << 32 | hvc_res.a1;
1775 *ts = ktime_to_timespec64(ktime);
1777 *cycle = (u64)hvc_res.a2 << 32 | hvc_res.a3;
1779 *cs = &clocksource_counter;
1783 EXPORT_SYMBOL_GPL(kvm_arch_ptp_get_crosststamp);