2 * linux/drivers/clocksource/arm_arch_timer.c
4 * Copyright (C) 2011 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/device.h>
14 #include <linux/smp.h>
15 #include <linux/cpu.h>
16 #include <linux/cpu_pm.h>
17 #include <linux/clockchips.h>
18 #include <linux/clocksource.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_address.h>
23 #include <linux/slab.h>
24 #include <linux/sched_clock.h>
25 #include <linux/acpi.h>
27 #include <asm/arch_timer.h>
30 #include <clocksource/arm_arch_timer.h>
33 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
35 #define CNTVCT_LO 0x08
36 #define CNTVCT_HI 0x0c
38 #define CNTP_TVAL 0x28
40 #define CNTV_TVAL 0x38
43 #define ARCH_CP15_TIMER BIT(0)
44 #define ARCH_MEM_TIMER BIT(1)
45 static unsigned arch_timers_present __initdata;
47 static void __iomem *arch_counter_base;
51 struct clock_event_device evt;
54 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
56 static u32 arch_timer_rate;
66 static int arch_timer_ppi[MAX_TIMER_PPI];
68 static struct clock_event_device __percpu *arch_timer_evt;
70 static bool arch_timer_use_virtual = true;
71 static bool arch_timer_c3stop;
72 static bool arch_timer_mem_use_virtual;
75 * Architected system timer support.
78 static __always_inline
79 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
80 struct clock_event_device *clk)
82 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
83 struct arch_timer *timer = to_arch_timer(clk);
85 case ARCH_TIMER_REG_CTRL:
86 writel_relaxed(val, timer->base + CNTP_CTL);
88 case ARCH_TIMER_REG_TVAL:
89 writel_relaxed(val, timer->base + CNTP_TVAL);
92 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
93 struct arch_timer *timer = to_arch_timer(clk);
95 case ARCH_TIMER_REG_CTRL:
96 writel_relaxed(val, timer->base + CNTV_CTL);
98 case ARCH_TIMER_REG_TVAL:
99 writel_relaxed(val, timer->base + CNTV_TVAL);
103 arch_timer_reg_write_cp15(access, reg, val);
107 static __always_inline
108 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
109 struct clock_event_device *clk)
113 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
114 struct arch_timer *timer = to_arch_timer(clk);
116 case ARCH_TIMER_REG_CTRL:
117 val = readl_relaxed(timer->base + CNTP_CTL);
119 case ARCH_TIMER_REG_TVAL:
120 val = readl_relaxed(timer->base + CNTP_TVAL);
123 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
124 struct arch_timer *timer = to_arch_timer(clk);
126 case ARCH_TIMER_REG_CTRL:
127 val = readl_relaxed(timer->base + CNTV_CTL);
129 case ARCH_TIMER_REG_TVAL:
130 val = readl_relaxed(timer->base + CNTV_TVAL);
134 val = arch_timer_reg_read_cp15(access, reg);
140 static __always_inline irqreturn_t timer_handler(const int access,
141 struct clock_event_device *evt)
145 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
146 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
147 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
148 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
149 evt->event_handler(evt);
156 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
158 struct clock_event_device *evt = dev_id;
160 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
163 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
165 struct clock_event_device *evt = dev_id;
167 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
170 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
172 struct clock_event_device *evt = dev_id;
174 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
177 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
179 struct clock_event_device *evt = dev_id;
181 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
184 static __always_inline int timer_shutdown(const int access,
185 struct clock_event_device *clk)
189 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
190 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
191 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
196 static int arch_timer_shutdown_virt(struct clock_event_device *clk)
198 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
201 static int arch_timer_shutdown_phys(struct clock_event_device *clk)
203 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
206 static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
208 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
211 static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
213 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
216 static __always_inline void set_next_event(const int access, unsigned long evt,
217 struct clock_event_device *clk)
220 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
221 ctrl |= ARCH_TIMER_CTRL_ENABLE;
222 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
223 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
224 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
227 static int arch_timer_set_next_event_virt(unsigned long evt,
228 struct clock_event_device *clk)
230 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
234 static int arch_timer_set_next_event_phys(unsigned long evt,
235 struct clock_event_device *clk)
237 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
241 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
242 struct clock_event_device *clk)
244 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
248 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
249 struct clock_event_device *clk)
251 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
255 static void __arch_timer_setup(unsigned type,
256 struct clock_event_device *clk)
258 clk->features = CLOCK_EVT_FEAT_ONESHOT;
260 if (type == ARCH_CP15_TIMER) {
261 if (arch_timer_c3stop)
262 clk->features |= CLOCK_EVT_FEAT_C3STOP;
263 clk->name = "arch_sys_timer";
265 clk->cpumask = cpumask_of(smp_processor_id());
266 if (arch_timer_use_virtual) {
267 clk->irq = arch_timer_ppi[VIRT_PPI];
268 clk->set_state_shutdown = arch_timer_shutdown_virt;
269 clk->set_next_event = arch_timer_set_next_event_virt;
271 clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
272 clk->set_state_shutdown = arch_timer_shutdown_phys;
273 clk->set_next_event = arch_timer_set_next_event_phys;
276 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
277 clk->name = "arch_mem_timer";
279 clk->cpumask = cpu_all_mask;
280 if (arch_timer_mem_use_virtual) {
281 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
282 clk->set_next_event =
283 arch_timer_set_next_event_virt_mem;
285 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
286 clk->set_next_event =
287 arch_timer_set_next_event_phys_mem;
291 clk->set_state_shutdown(clk);
293 clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
296 static void arch_timer_evtstrm_enable(int divider)
298 u32 cntkctl = arch_timer_get_cntkctl();
300 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
301 /* Set the divider and enable virtual event stream */
302 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
303 | ARCH_TIMER_VIRT_EVT_EN;
304 arch_timer_set_cntkctl(cntkctl);
305 elf_hwcap |= HWCAP_EVTSTRM;
307 compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
311 static void arch_timer_configure_evtstream(void)
313 int evt_stream_div, lsb;
316 * As the event stream can at most be generated at half the frequency
317 * of the counter, use half the frequency when computing the divider.
319 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
322 * Find the closest power of two to the divisor. If the adjacent bit
323 * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
325 lsb = fls(evt_stream_div) - 1;
326 if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
329 /* enable event stream */
330 arch_timer_evtstrm_enable(max(0, min(lsb, 15)));
333 static void arch_counter_set_user_access(void)
335 u32 cntkctl = arch_timer_get_cntkctl();
337 /* Disable user access to the timers and the physical counter */
338 /* Also disable virtual event stream */
339 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
340 | ARCH_TIMER_USR_VT_ACCESS_EN
341 | ARCH_TIMER_VIRT_EVT_EN
342 | ARCH_TIMER_USR_PCT_ACCESS_EN);
344 /* Enable user access to the virtual counter */
345 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
347 arch_timer_set_cntkctl(cntkctl);
350 static int arch_timer_setup(struct clock_event_device *clk)
352 __arch_timer_setup(ARCH_CP15_TIMER, clk);
354 if (arch_timer_use_virtual)
355 enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
357 enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
358 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
359 enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
362 arch_counter_set_user_access();
363 if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM))
364 arch_timer_configure_evtstream();
370 arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
372 /* Who has more than one independent system counter? */
377 * Try to determine the frequency from the device tree or CNTFRQ,
378 * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
380 if (!acpi_disabled ||
381 of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
383 arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
385 arch_timer_rate = arch_timer_get_cntfrq();
388 /* Check the timer frequency. */
389 if (arch_timer_rate == 0)
390 pr_warn("Architected timer frequency not available\n");
393 static void arch_timer_banner(unsigned type)
395 pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
396 type & ARCH_CP15_TIMER ? "cp15" : "",
397 type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
398 type & ARCH_MEM_TIMER ? "mmio" : "",
399 (unsigned long)arch_timer_rate / 1000000,
400 (unsigned long)(arch_timer_rate / 10000) % 100,
401 type & ARCH_CP15_TIMER ?
402 arch_timer_use_virtual ? "virt" : "phys" :
404 type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
405 type & ARCH_MEM_TIMER ?
406 arch_timer_mem_use_virtual ? "virt" : "phys" :
410 u32 arch_timer_get_rate(void)
412 return arch_timer_rate;
415 static u64 arch_counter_get_cntvct_mem(void)
417 u32 vct_lo, vct_hi, tmp_hi;
420 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
421 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
422 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
423 } while (vct_hi != tmp_hi);
425 return ((u64) vct_hi << 32) | vct_lo;
429 * Default to cp15 based access because arm64 uses this function for
430 * sched_clock() before DT is probed and the cp15 method is guaranteed
431 * to exist on arm64. arm doesn't use this before DT is probed so even
432 * if we don't have the cp15 accessors we won't have a problem.
434 u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
436 static cycle_t arch_counter_read(struct clocksource *cs)
438 return arch_timer_read_counter();
441 static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
443 return arch_timer_read_counter();
446 static struct clocksource clocksource_counter = {
447 .name = "arch_sys_counter",
449 .read = arch_counter_read,
450 .mask = CLOCKSOURCE_MASK(56),
451 .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
454 static struct cyclecounter cyclecounter = {
455 .read = arch_counter_read_cc,
456 .mask = CLOCKSOURCE_MASK(56),
459 static struct timecounter timecounter;
461 struct timecounter *arch_timer_get_timecounter(void)
466 static void __init arch_counter_register(unsigned type)
470 /* Register the CP15 based counter if we have one */
471 if (type & ARCH_CP15_TIMER) {
472 if (IS_ENABLED(CONFIG_ARM64) || arch_timer_use_virtual)
473 arch_timer_read_counter = arch_counter_get_cntvct;
475 arch_timer_read_counter = arch_counter_get_cntpct;
477 arch_timer_read_counter = arch_counter_get_cntvct_mem;
479 /* If the clocksource name is "arch_sys_counter" the
480 * VDSO will attempt to read the CP15-based counter.
481 * Ensure this does not happen when CP15-based
482 * counter is not available.
484 clocksource_counter.name = "arch_mem_counter";
487 start_count = arch_timer_read_counter();
488 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
489 cyclecounter.mult = clocksource_counter.mult;
490 cyclecounter.shift = clocksource_counter.shift;
491 timecounter_init(&timecounter, &cyclecounter, start_count);
493 /* 56 bits minimum, so we assume worst case rollover */
494 sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
497 static void arch_timer_stop(struct clock_event_device *clk)
499 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
500 clk->irq, smp_processor_id());
502 if (arch_timer_use_virtual)
503 disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
505 disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
506 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
507 disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
510 clk->set_state_shutdown(clk);
513 static int arch_timer_cpu_notify(struct notifier_block *self,
514 unsigned long action, void *hcpu)
517 * Grab cpu pointer in each case to avoid spurious
518 * preemptible warnings
520 switch (action & ~CPU_TASKS_FROZEN) {
522 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
525 arch_timer_stop(this_cpu_ptr(arch_timer_evt));
532 static struct notifier_block arch_timer_cpu_nb = {
533 .notifier_call = arch_timer_cpu_notify,
537 static unsigned int saved_cntkctl;
538 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
539 unsigned long action, void *hcpu)
541 if (action == CPU_PM_ENTER)
542 saved_cntkctl = arch_timer_get_cntkctl();
543 else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
544 arch_timer_set_cntkctl(saved_cntkctl);
548 static struct notifier_block arch_timer_cpu_pm_notifier = {
549 .notifier_call = arch_timer_cpu_pm_notify,
552 static int __init arch_timer_cpu_pm_init(void)
554 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
557 static int __init arch_timer_cpu_pm_init(void)
563 static int __init arch_timer_register(void)
568 arch_timer_evt = alloc_percpu(struct clock_event_device);
569 if (!arch_timer_evt) {
574 if (arch_timer_use_virtual) {
575 ppi = arch_timer_ppi[VIRT_PPI];
576 err = request_percpu_irq(ppi, arch_timer_handler_virt,
577 "arch_timer", arch_timer_evt);
579 ppi = arch_timer_ppi[PHYS_SECURE_PPI];
580 err = request_percpu_irq(ppi, arch_timer_handler_phys,
581 "arch_timer", arch_timer_evt);
582 if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
583 ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
584 err = request_percpu_irq(ppi, arch_timer_handler_phys,
585 "arch_timer", arch_timer_evt);
587 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
593 pr_err("arch_timer: can't register interrupt %d (%d)\n",
598 err = register_cpu_notifier(&arch_timer_cpu_nb);
602 err = arch_timer_cpu_pm_init();
604 goto out_unreg_notify;
606 /* Immediately configure the timer on the boot CPU */
607 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
612 unregister_cpu_notifier(&arch_timer_cpu_nb);
614 if (arch_timer_use_virtual)
615 free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
617 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
619 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
620 free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
625 free_percpu(arch_timer_evt);
630 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
634 struct arch_timer *t;
636 t = kzalloc(sizeof(*t), GFP_KERNEL);
642 __arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
644 if (arch_timer_mem_use_virtual)
645 func = arch_timer_handler_virt_mem;
647 func = arch_timer_handler_phys_mem;
649 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
651 pr_err("arch_timer: Failed to request mem timer irq\n");
658 static const struct of_device_id arch_timer_of_match[] __initconst = {
659 { .compatible = "arm,armv7-timer", },
660 { .compatible = "arm,armv8-timer", },
664 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
665 { .compatible = "arm,armv7-timer-mem", },
670 arch_timer_needs_probing(int type, const struct of_device_id *matches)
672 struct device_node *dn;
673 bool needs_probing = false;
675 dn = of_find_matching_node(NULL, matches);
676 if (dn && of_device_is_available(dn) && !(arch_timers_present & type))
677 needs_probing = true;
680 return needs_probing;
683 static void __init arch_timer_common_init(void)
685 unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
687 /* Wait until both nodes are probed if we have two timers */
688 if ((arch_timers_present & mask) != mask) {
689 if (arch_timer_needs_probing(ARCH_MEM_TIMER, arch_timer_mem_of_match))
691 if (arch_timer_needs_probing(ARCH_CP15_TIMER, arch_timer_of_match))
695 arch_timer_banner(arch_timers_present);
696 arch_counter_register(arch_timers_present);
697 arch_timer_arch_init();
700 static void __init arch_timer_init(void)
703 * If HYP mode is available, we know that the physical timer
704 * has been configured to be accessible from PL1. Use it, so
705 * that a guest can use the virtual timer instead.
707 * If no interrupt provided for virtual timer, we'll have to
708 * stick to the physical timer. It'd better be accessible...
710 if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
711 arch_timer_use_virtual = false;
713 if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
714 !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
715 pr_warn("arch_timer: No interrupt available, giving up\n");
720 arch_timer_register();
721 arch_timer_common_init();
724 static void __init arch_timer_of_init(struct device_node *np)
728 if (arch_timers_present & ARCH_CP15_TIMER) {
729 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
733 arch_timers_present |= ARCH_CP15_TIMER;
734 for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
735 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
737 arch_timer_detect_rate(NULL, np);
739 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
742 * If we cannot rely on firmware initializing the timer registers then
743 * we should use the physical timers instead.
745 if (IS_ENABLED(CONFIG_ARM) &&
746 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
747 arch_timer_use_virtual = false;
751 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
752 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
754 static void __init arch_timer_mem_init(struct device_node *np)
756 struct device_node *frame, *best_frame = NULL;
757 void __iomem *cntctlbase, *base;
761 arch_timers_present |= ARCH_MEM_TIMER;
762 cntctlbase = of_iomap(np, 0);
764 pr_err("arch_timer: Can't find CNTCTLBase\n");
768 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
772 * Try to find a virtual capable frame. Otherwise fall back to a
773 * physical capable frame.
775 for_each_available_child_of_node(np, frame) {
778 if (of_property_read_u32(frame, "frame-number", &n)) {
779 pr_err("arch_timer: Missing frame-number\n");
780 of_node_put(best_frame);
785 if (cnttidr & CNTTIDR_VIRT(n)) {
786 of_node_put(best_frame);
788 arch_timer_mem_use_virtual = true;
791 of_node_put(best_frame);
792 best_frame = of_node_get(frame);
795 base = arch_counter_base = of_iomap(best_frame, 0);
797 pr_err("arch_timer: Can't map frame's registers\n");
798 of_node_put(best_frame);
802 if (arch_timer_mem_use_virtual)
803 irq = irq_of_parse_and_map(best_frame, 1);
805 irq = irq_of_parse_and_map(best_frame, 0);
806 of_node_put(best_frame);
808 pr_err("arch_timer: Frame missing %s irq",
809 arch_timer_mem_use_virtual ? "virt" : "phys");
813 arch_timer_detect_rate(base, np);
814 arch_timer_mem_register(base, irq);
815 arch_timer_common_init();
817 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
818 arch_timer_mem_init);
821 static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags)
823 int trigger, polarity;
828 trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE
829 : ACPI_LEVEL_SENSITIVE;
831 polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW
834 return acpi_register_gsi(NULL, interrupt, trigger, polarity);
837 /* Initialize per-processor generic timer */
838 static int __init arch_timer_acpi_init(struct acpi_table_header *table)
840 struct acpi_table_gtdt *gtdt;
842 if (arch_timers_present & ARCH_CP15_TIMER) {
843 pr_warn("arch_timer: already initialized, skipping\n");
847 gtdt = container_of(table, struct acpi_table_gtdt, header);
849 arch_timers_present |= ARCH_CP15_TIMER;
851 arch_timer_ppi[PHYS_SECURE_PPI] =
852 map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
853 gtdt->secure_el1_flags);
855 arch_timer_ppi[PHYS_NONSECURE_PPI] =
856 map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
857 gtdt->non_secure_el1_flags);
859 arch_timer_ppi[VIRT_PPI] =
860 map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
861 gtdt->virtual_timer_flags);
863 arch_timer_ppi[HYP_PPI] =
864 map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
865 gtdt->non_secure_el2_flags);
867 /* Get the frequency from CNTFRQ */
868 arch_timer_detect_rate(NULL, NULL);
870 /* Always-on capability */
871 arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
876 CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);