1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC PLL driver
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
10 #include <linux/slab.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
17 * @set_pll_mode: Whether an IOCTL_SET_PLL_FRAC_MODE request be sent to ATF
25 #define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw)
27 #define PLL_FBDIV_MIN 25
28 #define PLL_FBDIV_MAX 125
30 #define PS_PLL_VCO_MIN 1500000000
31 #define PS_PLL_VCO_MAX 3000000000UL
38 #define FRAC_OFFSET 0x8
39 #define PLLFCFG_FRAC_EN BIT(31)
40 #define FRAC_DIV BIT(16) /* 2^16 */
43 * zynqmp_pll_get_mode() - Get mode of PLL
44 * @hw: Handle between common and hardware-specific interfaces
48 static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw)
50 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
51 u32 clk_id = clk->clk_id;
52 const char *clk_name = clk_hw_get_name(hw);
53 u32 ret_payload[PAYLOAD_ARG_CNT];
56 ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload);
58 pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n",
59 __func__, clk_name, ret);
61 return ret_payload[1];
65 * zynqmp_pll_set_mode() - Set the PLL mode
66 * @hw: Handle between common and hardware-specific interfaces
67 * @on: Flag to determine the mode
69 static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
71 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
72 u32 clk_id = clk->clk_id;
73 const char *clk_name = clk_hw_get_name(hw);
82 ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode);
84 pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
85 __func__, clk_name, ret);
87 clk->set_pll_mode = true;
91 * zynqmp_pll_round_rate() - Round a clock frequency
92 * @hw: Handle between common and hardware-specific interfaces
93 * @rate: Desired clock frequency
94 * @prate: Clock frequency of parent clock
96 * Return: Frequency closest to @rate the hardware can generate
98 static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
104 /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */
105 if (rate > PS_PLL_VCO_MAX) {
106 div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX);
109 if (rate < PS_PLL_VCO_MIN) {
110 mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
114 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
115 if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) {
116 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
117 rate = *prate * fbdiv;
124 * zynqmp_pll_recalc_rate() - Recalculate clock frequency
125 * @hw: Handle between common and hardware-specific interfaces
126 * @parent_rate: Clock frequency of parent clock
128 * Return: Current clock frequency
130 static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw,
131 unsigned long parent_rate)
133 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
134 u32 clk_id = clk->clk_id;
135 const char *clk_name = clk_hw_get_name(hw);
137 unsigned long rate, frac;
138 u32 ret_payload[PAYLOAD_ARG_CNT];
141 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv);
143 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
144 __func__, clk_name, ret);
146 rate = parent_rate * fbdiv;
147 if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
148 zynqmp_pm_get_pll_frac_data(clk_id, ret_payload);
149 data = ret_payload[1];
150 frac = (parent_rate * data) / FRAC_DIV;
158 * zynqmp_pll_set_rate() - Set rate of PLL
159 * @hw: Handle between common and hardware-specific interfaces
160 * @rate: Frequency of clock to be set
161 * @parent_rate: Clock frequency of parent clock
163 * Set PLL divider to set desired rate.
165 * Returns: rate which is set on success else error code
167 static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
168 unsigned long parent_rate)
170 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
171 u32 clk_id = clk->clk_id;
172 const char *clk_name = clk_hw_get_name(hw);
174 long rate_div, frac, m, f;
177 rate_div = (rate * FRAC_DIV) / parent_rate;
178 f = rate_div % FRAC_DIV;
179 zynqmp_pll_set_mode(hw, !!f);
182 m = rate_div / FRAC_DIV;
183 m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
184 rate = parent_rate * m;
185 frac = (parent_rate * f) / FRAC_DIV;
187 ret = zynqmp_pm_clock_setdivider(clk_id, m);
189 WARN(1, "More than allowed devices are using the %s, which is forbidden\n",
192 pr_warn_once("%s() set divider failed for %s, ret = %d\n",
193 __func__, clk_name, ret);
194 zynqmp_pm_set_pll_frac_data(clk_id, f);
199 fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
200 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
201 ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv);
203 pr_warn_once("%s() set divider failed for %s, ret = %d\n",
204 __func__, clk_name, ret);
206 return parent_rate * fbdiv;
210 * zynqmp_pll_is_enabled() - Check if a clock is enabled
211 * @hw: Handle between common and hardware-specific interfaces
213 * Return: 1 if the clock is enabled, 0 otherwise
215 static int zynqmp_pll_is_enabled(struct clk_hw *hw)
217 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
218 const char *clk_name = clk_hw_get_name(hw);
219 u32 clk_id = clk->clk_id;
223 ret = zynqmp_pm_clock_getstate(clk_id, &state);
225 pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
226 __func__, clk_name, ret);
230 return state ? 1 : 0;
234 * zynqmp_pll_enable() - Enable clock
235 * @hw: Handle between common and hardware-specific interfaces
237 * Return: 0 on success else error code
239 static int zynqmp_pll_enable(struct clk_hw *hw)
241 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
242 const char *clk_name = clk_hw_get_name(hw);
243 u32 clk_id = clk->clk_id;
247 * Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request
248 * that has been sent to ATF.
250 if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode))
253 clk->set_pll_mode = false;
255 ret = zynqmp_pm_clock_enable(clk_id);
257 pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
258 __func__, clk_name, ret);
264 * zynqmp_pll_disable() - Disable clock
265 * @hw: Handle between common and hardware-specific interfaces
267 static void zynqmp_pll_disable(struct clk_hw *hw)
269 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
270 const char *clk_name = clk_hw_get_name(hw);
271 u32 clk_id = clk->clk_id;
274 if (!zynqmp_pll_is_enabled(hw))
277 ret = zynqmp_pm_clock_disable(clk_id);
279 pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
280 __func__, clk_name, ret);
283 static const struct clk_ops zynqmp_pll_ops = {
284 .enable = zynqmp_pll_enable,
285 .disable = zynqmp_pll_disable,
286 .is_enabled = zynqmp_pll_is_enabled,
287 .round_rate = zynqmp_pll_round_rate,
288 .recalc_rate = zynqmp_pll_recalc_rate,
289 .set_rate = zynqmp_pll_set_rate,
293 * zynqmp_clk_register_pll() - Register PLL with the clock framework
296 * @parents: Name of this clock's parents
297 * @num_parents: Number of parents
298 * @nodes: Clock topology node
300 * Return: clock hardware to the registered clock
302 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
303 const char * const *parents,
305 const struct clock_topology *nodes)
307 struct zynqmp_pll *pll;
309 struct clk_init_data init;
313 init.ops = &zynqmp_pll_ops;
314 init.flags = nodes->flag;
315 init.parent_names = parents;
316 init.num_parents = 1;
318 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
320 return ERR_PTR(-ENOMEM);
322 pll->hw.init = &init;
323 pll->clk_id = clk_id;
326 ret = clk_hw_register(NULL, hw);
332 clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX);
334 pr_err("%s:ERROR clk_set_rate_range failed %d\n", name, ret);