2 * Copyright 2014 Linaro Ltd.
3 * Copyright (C) 2014 ZTE Corporation.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk-provider.h>
11 #include <linux/err.h>
13 #include <linux/iopoll.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <asm/div64.h>
20 #define to_clk_zx_pll(_hw) container_of(_hw, struct clk_zx_pll, hw)
21 #define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw)
23 #define CFG0_CFG1_OFFSET 4
27 static int rate_to_idx(struct clk_zx_pll *zx_pll, unsigned long rate)
29 const struct zx_pll_config *config = zx_pll->lookup_table;
32 for (i = 0; i < zx_pll->count; i++) {
33 if (config[i].rate > rate)
34 return i > 0 ? i - 1 : 0;
36 if (config[i].rate == rate)
43 static int hw_to_idx(struct clk_zx_pll *zx_pll)
45 const struct zx_pll_config *config = zx_pll->lookup_table;
49 hw_cfg0 = readl_relaxed(zx_pll->reg_base);
50 hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET);
52 /* For matching the value in lookup table */
53 hw_cfg0 &= ~BIT(zx_pll->lock_bit);
54 hw_cfg0 |= BIT(zx_pll->pd_bit);
56 for (i = 0; i < zx_pll->count; i++) {
57 if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1)
64 static unsigned long zx_pll_recalc_rate(struct clk_hw *hw,
65 unsigned long parent_rate)
67 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
70 idx = hw_to_idx(zx_pll);
71 if (unlikely(idx == -EINVAL))
74 return zx_pll->lookup_table[idx].rate;
77 static long zx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
80 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
83 idx = rate_to_idx(zx_pll, rate);
85 return zx_pll->lookup_table[idx].rate;
88 static int zx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
89 unsigned long parent_rate)
91 /* Assume current cpu is not running on current PLL */
92 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
93 const struct zx_pll_config *config;
96 idx = rate_to_idx(zx_pll, rate);
97 config = &zx_pll->lookup_table[idx];
99 writel_relaxed(config->cfg0, zx_pll->reg_base);
100 writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET);
105 static int zx_pll_enable(struct clk_hw *hw)
107 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
110 reg = readl_relaxed(zx_pll->reg_base);
111 writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
113 return readl_relaxed_poll_timeout(zx_pll->reg_base, reg,
114 reg & BIT(zx_pll->lock_bit), 0, 100);
117 static void zx_pll_disable(struct clk_hw *hw)
119 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
122 reg = readl_relaxed(zx_pll->reg_base);
123 writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);
126 static int zx_pll_is_enabled(struct clk_hw *hw)
128 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
131 reg = readl_relaxed(zx_pll->reg_base);
133 return !(reg & BIT(zx_pll->pd_bit));
136 const struct clk_ops zx_pll_ops = {
137 .recalc_rate = zx_pll_recalc_rate,
138 .round_rate = zx_pll_round_rate,
139 .set_rate = zx_pll_set_rate,
140 .enable = zx_pll_enable,
141 .disable = zx_pll_disable,
142 .is_enabled = zx_pll_is_enabled,
144 EXPORT_SYMBOL(zx_pll_ops);
146 struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
147 unsigned long flags, void __iomem *reg_base,
148 const struct zx_pll_config *lookup_table,
149 int count, spinlock_t *lock)
151 struct clk_zx_pll *zx_pll;
153 struct clk_init_data init;
155 zx_pll = kzalloc(sizeof(*zx_pll), GFP_KERNEL);
157 return ERR_PTR(-ENOMEM);
160 init.ops = &zx_pll_ops;
162 init.parent_names = parent_name ? &parent_name : NULL;
163 init.num_parents = parent_name ? 1 : 0;
165 zx_pll->reg_base = reg_base;
166 zx_pll->lookup_table = lookup_table;
167 zx_pll->count = count;
168 zx_pll->lock_bit = LOCK_FLAG;
169 zx_pll->pd_bit = POWER_DOWN;
171 zx_pll->hw.init = &init;
173 clk = clk_register(NULL, &zx_pll->hw);
181 static u32 calc_reg(u32 parent_rate, u32 rate)
183 u32 sel, integ, fra_div, tmp;
184 u64 tmp64 = (u64)parent_rate * BPAR;
187 integ = (u32)tmp64 / BPAR;
190 tmp = (u32)tmp64 % BPAR;
194 fra_div = tmp * 0xff / BPAR;
195 tmp = (sel << 24) | (integ << 16) | (0xff << 8) | fra_div;
197 /* Set I2S integer divider as 1. This bit is reserved for SPDIF
204 static u32 calc_rate(u32 reg, u32 parent_rate)
206 u32 sel, integ, fra_div, tmp;
207 u64 tmp64 = (u64)parent_rate * BPAR;
210 sel = (tmp >> 24) & BIT(0);
211 integ = (tmp >> 16) & 0xff;
212 fra_div = tmp & 0xff;
214 tmp = fra_div * BPAR;
217 tmp += 2 * integ * BPAR;
223 static unsigned long zx_audio_recalc_rate(struct clk_hw *hw,
224 unsigned long parent_rate)
226 struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
229 reg = readl_relaxed(zx_audio->reg_base);
230 return calc_rate(reg, parent_rate);
233 static long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate,
234 unsigned long *prate)
238 if (rate * 2 > *prate)
241 reg = calc_reg(*prate, rate);
242 return calc_rate(reg, *prate);
245 static int zx_audio_set_rate(struct clk_hw *hw, unsigned long rate,
246 unsigned long parent_rate)
248 struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
251 reg = calc_reg(parent_rate, rate);
252 writel_relaxed(reg, zx_audio->reg_base);
257 #define ZX_AUDIO_EN BIT(25)
258 static int zx_audio_enable(struct clk_hw *hw)
260 struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
263 reg = readl_relaxed(zx_audio->reg_base);
264 writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base);
268 static void zx_audio_disable(struct clk_hw *hw)
270 struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
273 reg = readl_relaxed(zx_audio->reg_base);
274 writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base);
277 static const struct clk_ops zx_audio_ops = {
278 .recalc_rate = zx_audio_recalc_rate,
279 .round_rate = zx_audio_round_rate,
280 .set_rate = zx_audio_set_rate,
281 .enable = zx_audio_enable,
282 .disable = zx_audio_disable,
285 struct clk *clk_register_zx_audio(const char *name,
286 const char * const parent_name,
288 void __iomem *reg_base)
290 struct clk_zx_audio *zx_audio;
292 struct clk_init_data init;
294 zx_audio = kzalloc(sizeof(*zx_audio), GFP_KERNEL);
296 return ERR_PTR(-ENOMEM);
299 init.ops = &zx_audio_ops;
301 init.parent_names = parent_name ? &parent_name : NULL;
302 init.num_parents = parent_name ? 1 : 0;
304 zx_audio->reg_base = reg_base;
305 zx_audio->hw.init = &init;
307 clk = clk_register(NULL, &zx_audio->hw);