1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2014 Linaro Ltd.
4 * Copyright (C) 2014 ZTE Corporation.
7 #include <linux/clk-provider.h>
11 #include <linux/iopoll.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
14 #include <asm/div64.h>
18 #define to_clk_zx_pll(_hw) container_of(_hw, struct clk_zx_pll, hw)
19 #define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw)
21 #define CFG0_CFG1_OFFSET 4
25 static int rate_to_idx(struct clk_zx_pll *zx_pll, unsigned long rate)
27 const struct zx_pll_config *config = zx_pll->lookup_table;
30 for (i = 0; i < zx_pll->count; i++) {
31 if (config[i].rate > rate)
32 return i > 0 ? i - 1 : 0;
34 if (config[i].rate == rate)
41 static int hw_to_idx(struct clk_zx_pll *zx_pll)
43 const struct zx_pll_config *config = zx_pll->lookup_table;
47 hw_cfg0 = readl_relaxed(zx_pll->reg_base);
48 hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET);
50 /* For matching the value in lookup table */
51 hw_cfg0 &= ~BIT(zx_pll->lock_bit);
53 /* Check availability of pd_bit */
54 if (zx_pll->pd_bit < 32)
55 hw_cfg0 |= BIT(zx_pll->pd_bit);
57 for (i = 0; i < zx_pll->count; i++) {
58 if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1)
65 static unsigned long zx_pll_recalc_rate(struct clk_hw *hw,
66 unsigned long parent_rate)
68 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
71 idx = hw_to_idx(zx_pll);
72 if (unlikely(idx == -EINVAL))
75 return zx_pll->lookup_table[idx].rate;
78 static long zx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
81 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
84 idx = rate_to_idx(zx_pll, rate);
86 return zx_pll->lookup_table[idx].rate;
89 static int zx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
90 unsigned long parent_rate)
92 /* Assume current cpu is not running on current PLL */
93 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
94 const struct zx_pll_config *config;
97 idx = rate_to_idx(zx_pll, rate);
98 config = &zx_pll->lookup_table[idx];
100 writel_relaxed(config->cfg0, zx_pll->reg_base);
101 writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET);
106 static int zx_pll_enable(struct clk_hw *hw)
108 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
111 /* If pd_bit is not available, simply return success. */
112 if (zx_pll->pd_bit > 31)
115 reg = readl_relaxed(zx_pll->reg_base);
116 writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
118 return readl_relaxed_poll_timeout(zx_pll->reg_base, reg,
119 reg & BIT(zx_pll->lock_bit), 0, 100);
122 static void zx_pll_disable(struct clk_hw *hw)
124 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
127 if (zx_pll->pd_bit > 31)
130 reg = readl_relaxed(zx_pll->reg_base);
131 writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);
134 static int zx_pll_is_enabled(struct clk_hw *hw)
136 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
139 reg = readl_relaxed(zx_pll->reg_base);
141 return !(reg & BIT(zx_pll->pd_bit));
144 const struct clk_ops zx_pll_ops = {
145 .recalc_rate = zx_pll_recalc_rate,
146 .round_rate = zx_pll_round_rate,
147 .set_rate = zx_pll_set_rate,
148 .enable = zx_pll_enable,
149 .disable = zx_pll_disable,
150 .is_enabled = zx_pll_is_enabled,
152 EXPORT_SYMBOL(zx_pll_ops);
154 struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
155 unsigned long flags, void __iomem *reg_base,
156 const struct zx_pll_config *lookup_table,
157 int count, spinlock_t *lock)
159 struct clk_zx_pll *zx_pll;
161 struct clk_init_data init;
163 zx_pll = kzalloc(sizeof(*zx_pll), GFP_KERNEL);
165 return ERR_PTR(-ENOMEM);
168 init.ops = &zx_pll_ops;
170 init.parent_names = parent_name ? &parent_name : NULL;
171 init.num_parents = parent_name ? 1 : 0;
173 zx_pll->reg_base = reg_base;
174 zx_pll->lookup_table = lookup_table;
175 zx_pll->count = count;
176 zx_pll->lock_bit = LOCK_FLAG;
177 zx_pll->pd_bit = POWER_DOWN;
179 zx_pll->hw.init = &init;
181 clk = clk_register(NULL, &zx_pll->hw);
189 static u32 calc_reg(u32 parent_rate, u32 rate)
191 u32 sel, integ, fra_div, tmp;
192 u64 tmp64 = (u64)parent_rate * BPAR;
195 integ = (u32)tmp64 / BPAR;
198 tmp = (u32)tmp64 % BPAR;
202 fra_div = tmp * 0xff / BPAR;
203 tmp = (sel << 24) | (integ << 16) | (0xff << 8) | fra_div;
205 /* Set I2S integer divider as 1. This bit is reserved for SPDIF
212 static u32 calc_rate(u32 reg, u32 parent_rate)
214 u32 sel, integ, fra_div, tmp;
215 u64 tmp64 = (u64)parent_rate * BPAR;
218 sel = (tmp >> 24) & BIT(0);
219 integ = (tmp >> 16) & 0xff;
220 fra_div = tmp & 0xff;
222 tmp = fra_div * BPAR;
225 tmp += 2 * integ * BPAR;
231 static unsigned long zx_audio_recalc_rate(struct clk_hw *hw,
232 unsigned long parent_rate)
234 struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
237 reg = readl_relaxed(zx_audio->reg_base);
238 return calc_rate(reg, parent_rate);
241 static long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate,
242 unsigned long *prate)
246 if (rate * 2 > *prate)
249 reg = calc_reg(*prate, rate);
250 return calc_rate(reg, *prate);
253 static int zx_audio_set_rate(struct clk_hw *hw, unsigned long rate,
254 unsigned long parent_rate)
256 struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
259 reg = calc_reg(parent_rate, rate);
260 writel_relaxed(reg, zx_audio->reg_base);
265 #define ZX_AUDIO_EN BIT(25)
266 static int zx_audio_enable(struct clk_hw *hw)
268 struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
271 reg = readl_relaxed(zx_audio->reg_base);
272 writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base);
276 static void zx_audio_disable(struct clk_hw *hw)
278 struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
281 reg = readl_relaxed(zx_audio->reg_base);
282 writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base);
285 static const struct clk_ops zx_audio_ops = {
286 .recalc_rate = zx_audio_recalc_rate,
287 .round_rate = zx_audio_round_rate,
288 .set_rate = zx_audio_set_rate,
289 .enable = zx_audio_enable,
290 .disable = zx_audio_disable,
293 struct clk *clk_register_zx_audio(const char *name,
294 const char * const parent_name,
296 void __iomem *reg_base)
298 struct clk_zx_audio *zx_audio;
300 struct clk_init_data init;
302 zx_audio = kzalloc(sizeof(*zx_audio), GFP_KERNEL);
304 return ERR_PTR(-ENOMEM);
307 init.ops = &zx_audio_ops;
309 init.parent_names = parent_name ? &parent_name : NULL;
310 init.num_parents = parent_name ? 1 : 0;
312 zx_audio->reg_base = reg_base;
313 zx_audio->hw.init = &init;
315 clk = clk_register(NULL, &zx_audio->hw);
322 #define CLK_AUDIO_DIV_FRAC BIT(0)
323 #define CLK_AUDIO_DIV_INT BIT(1)
324 #define CLK_AUDIO_DIV_UNCOMMON BIT(1)
326 #define CLK_AUDIO_DIV_FRAC_NSHIFT 16
327 #define CLK_AUDIO_DIV_INT_FRAC_RE BIT(16)
328 #define CLK_AUDIO_DIV_INT_FRAC_MAX (0xffff)
329 #define CLK_AUDIO_DIV_INT_FRAC_MIN (0x2)
330 #define CLK_AUDIO_DIV_INT_INT_SHIFT 24
331 #define CLK_AUDIO_DIV_INT_INT_WIDTH 4
333 struct zx_clk_audio_div_table {
335 unsigned int int_reg;
336 unsigned int frac_reg;
339 #define to_clk_zx_audio_div(_hw) container_of(_hw, struct clk_zx_audio_divider, hw)
341 static unsigned long audio_calc_rate(struct clk_zx_audio_divider *audio_div,
342 u32 reg_frac, u32 reg_int,
343 unsigned long parent_rate)
345 unsigned long rate, m, n;
347 m = reg_frac & 0xffff;
348 n = (reg_frac >> 16) & 0xffff;
350 m = (reg_int & 0xffff) * n + m;
351 rate = (parent_rate * n) / m;
356 static void audio_calc_reg(struct clk_zx_audio_divider *audio_div,
357 struct zx_clk_audio_div_table *div_table,
358 unsigned long rate, unsigned long parent_rate)
360 unsigned int reg_int, reg_frac;
361 unsigned long m, n, div;
363 reg_int = parent_rate / rate;
365 if (reg_int > CLK_AUDIO_DIV_INT_FRAC_MAX)
366 reg_int = CLK_AUDIO_DIV_INT_FRAC_MAX;
367 else if (reg_int < CLK_AUDIO_DIV_INT_FRAC_MIN)
369 m = parent_rate - rate * reg_int;
376 if ((m >> 16) || (n >> 16)) {
385 reg_frac = m | (n << 16);
387 div_table->rate = parent_rate * n / (reg_int * n + m);
388 div_table->int_reg = reg_int;
389 div_table->frac_reg = reg_frac;
392 static unsigned long zx_audio_div_recalc_rate(struct clk_hw *hw,
393 unsigned long parent_rate)
395 struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
396 u32 reg_frac, reg_int;
398 reg_frac = readl_relaxed(zx_audio_div->reg_base);
399 reg_int = readl_relaxed(zx_audio_div->reg_base + 0x4);
401 return audio_calc_rate(zx_audio_div, reg_frac, reg_int, parent_rate);
404 static long zx_audio_div_round_rate(struct clk_hw *hw, unsigned long rate,
405 unsigned long *prate)
407 struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
408 struct zx_clk_audio_div_table divt;
410 audio_calc_reg(zx_audio_div, &divt, rate, *prate);
412 return audio_calc_rate(zx_audio_div, divt.frac_reg, divt.int_reg, *prate);
415 static int zx_audio_div_set_rate(struct clk_hw *hw, unsigned long rate,
416 unsigned long parent_rate)
418 struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
419 struct zx_clk_audio_div_table divt;
422 audio_calc_reg(zx_audio_div, &divt, rate, parent_rate);
423 if (divt.rate != rate)
424 pr_debug("the real rate is:%ld", divt.rate);
426 writel_relaxed(divt.frac_reg, zx_audio_div->reg_base);
428 val = readl_relaxed(zx_audio_div->reg_base + 0x4);
430 val |= divt.int_reg | CLK_AUDIO_DIV_INT_FRAC_RE;
431 writel_relaxed(val, zx_audio_div->reg_base + 0x4);
435 val = readl_relaxed(zx_audio_div->reg_base + 0x4);
436 val &= ~CLK_AUDIO_DIV_INT_FRAC_RE;
437 writel_relaxed(val, zx_audio_div->reg_base + 0x4);
442 const struct clk_ops zx_audio_div_ops = {
443 .recalc_rate = zx_audio_div_recalc_rate,
444 .round_rate = zx_audio_div_round_rate,
445 .set_rate = zx_audio_div_set_rate,