drivers/clk/zte/clk-zx296718.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 - 2016 ZTE Corporation.
   4  * Copyright (C) 2016 Linaro Ltd.
   5  */
   6 #include <linux/clk-provider.h>
   7 #include <linux/device.h>
   8 #include <linux/kernel.h>
   9 #include <linux/of_address.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12
  13 #include <dt-bindings/clock/zx296718-clock.h>
  14 #include "clk.h"
  15
  16 /* TOP CRM */
  17 #define TOP_CLK_MUX0    0x04
  18 #define TOP_CLK_MUX1    0x08
  19 #define TOP_CLK_MUX2    0x0c
  20 #define TOP_CLK_MUX3    0x10
  21 #define TOP_CLK_MUX4    0x14
  22 #define TOP_CLK_MUX5    0x18
  23 #define TOP_CLK_MUX6    0x1c
  24 #define TOP_CLK_MUX7    0x20
  25 #define TOP_CLK_MUX9    0x28
  26
  27
  28 #define TOP_CLK_GATE0   0x34
  29 #define TOP_CLK_GATE1   0x38
  30 #define TOP_CLK_GATE2   0x3c
  31 #define TOP_CLK_GATE3   0x40
  32 #define TOP_CLK_GATE4   0x44
  33 #define TOP_CLK_GATE5   0x48
  34 #define TOP_CLK_GATE6   0x4c
  35
  36 #define TOP_CLK_DIV0    0x58
  37
  38 #define PLL_CPU_REG     0x80
  39 #define PLL_VGA_REG     0xb0
  40 #define PLL_DDR_REG     0xa0
  41
  42 /* LSP0 CRM */
  43 #define LSP0_TIMER3_CLK 0x4
  44 #define LSP0_TIMER4_CLK 0x8
  45 #define LSP0_TIMER5_CLK 0xc
  46 #define LSP0_UART3_CLK  0x10
  47 #define LSP0_UART1_CLK  0x14
  48 #define LSP0_UART2_CLK  0x18
  49 #define LSP0_SPIFC0_CLK 0x1c
  50 #define LSP0_I2C4_CLK   0x20
  51 #define LSP0_I2C5_CLK   0x24
  52 #define LSP0_SSP0_CLK   0x28
  53 #define LSP0_SSP1_CLK   0x2c
  54 #define LSP0_USIM0_CLK  0x30
  55 #define LSP0_GPIO_CLK   0x34
  56 #define LSP0_I2C3_CLK   0x38
  57
  58 /* LSP1 CRM */
  59 #define LSP1_UART4_CLK  0x08
  60 #define LSP1_UART5_CLK  0x0c
  61 #define LSP1_PWM_CLK    0x10
  62 #define LSP1_I2C2_CLK   0x14
  63 #define LSP1_SSP2_CLK   0x1c
  64 #define LSP1_SSP3_CLK   0x20
  65 #define LSP1_SSP4_CLK   0x24
  66 #define LSP1_USIM1_CLK  0x28
  67
  68 /* audio lsp */
  69 #define AUDIO_I2S0_DIV_CFG1     0x10
  70 #define AUDIO_I2S0_DIV_CFG2     0x14
  71 #define AUDIO_I2S0_CLK          0x18
  72 #define AUDIO_I2S1_DIV_CFG1     0x20
  73 #define AUDIO_I2S1_DIV_CFG2     0x24
  74 #define AUDIO_I2S1_CLK          0x28
  75 #define AUDIO_I2S2_DIV_CFG1     0x30
  76 #define AUDIO_I2S2_DIV_CFG2     0x34
  77 #define AUDIO_I2S2_CLK          0x38
  78 #define AUDIO_I2S3_DIV_CFG1     0x40
  79 #define AUDIO_I2S3_DIV_CFG2     0x44
  80 #define AUDIO_I2S3_CLK          0x48
  81 #define AUDIO_I2C0_CLK          0x50
  82 #define AUDIO_SPDIF0_DIV_CFG1   0x60
  83 #define AUDIO_SPDIF0_DIV_CFG2   0x64
  84 #define AUDIO_SPDIF0_CLK        0x68
  85 #define AUDIO_SPDIF1_DIV_CFG1   0x70
  86 #define AUDIO_SPDIF1_DIV_CFG2   0x74
  87 #define AUDIO_SPDIF1_CLK        0x78
  88 #define AUDIO_TIMER_CLK         0x80
  89 #define AUDIO_TDM_CLK           0x90
  90 #define AUDIO_TS_CLK            0xa0
  91
  92 static DEFINE_SPINLOCK(clk_lock);
  93
  94 static const struct zx_pll_config pll_cpu_table[] = {
  95         PLL_RATE(1312000000, 0x00103621, 0x04aaaaaa),
  96         PLL_RATE(1407000000, 0x00103a21, 0x04aaaaaa),
  97         PLL_RATE(1503000000, 0x00103e21, 0x04aaaaaa),
  98         PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa),
  99 };
 100
 101 static const struct zx_pll_config pll_vga_table[] = {
 102         PLL_RATE(36000000,  0x00102464, 0x04000000), /* 800x600@56 */
 103         PLL_RATE(40000000,  0x00102864, 0x04000000), /* 800x600@60 */
 104         PLL_RATE(49500000,  0x00103164, 0x04800000), /* 800x600@75 */
 105         PLL_RATE(50000000,  0x00103264, 0x04000000), /* 800x600@72 */
 106         PLL_RATE(56250000,  0x00103864, 0x04400000), /* 800x600@85 */
 107         PLL_RATE(65000000,  0x00104164, 0x04000000), /* 1024x768@60 */
 108         PLL_RATE(74375000,  0x00104a64, 0x04600000), /* 1280x720@60 */
 109         PLL_RATE(75000000,  0x00104b64, 0x04800000), /* 1024x768@70 */
 110         PLL_RATE(78750000,  0x00104e64, 0x04c00000), /* 1024x768@75 */
 111         PLL_RATE(85500000,  0x00105564, 0x04800000), /* 1360x768@60 */
 112         PLL_RATE(106500000, 0x00106a64, 0x04800000), /* 1440x900@60 */
 113         PLL_RATE(108000000, 0x00106c64, 0x04000000), /* 1280x1024@60 */
 114         PLL_RATE(110000000, 0x00106e64, 0x04000000), /* 1024x768@85 */
 115         PLL_RATE(135000000, 0x00105a44, 0x04000000), /* 1280x1024@75 */
 116         PLL_RATE(136750000, 0x00104462, 0x04600000), /* 1440x900@75 */
 117         PLL_RATE(148500000, 0x00104a62, 0x04400000), /* 1920x1080@60 */
 118         PLL_RATE(157000000, 0x00104e62, 0x04800000), /* 1440x900@85 */
 119         PLL_RATE(157500000, 0x00104e62, 0x04c00000), /* 1280x1024@85 */
 120         PLL_RATE(162000000, 0x00105162, 0x04000000), /* 1600x1200@60 */
 121         PLL_RATE(193250000, 0x00106062, 0x04a00000), /* 1920x1200@60 */
 122 };
 123
 124 PNAME(osc) = {
 125         "osc24m",
 126         "osc32k",
 127 };
 128
 129 PNAME(dbg_wclk_p) = {
 130         "clk334m",
 131         "clk466m",
 132         "clk396m",
 133         "clk250m",
 134 };
 135
 136 PNAME(a72_coreclk_p) = {
 137         "osc24m",
 138         "pll_mm0_1188m",
 139         "pll_mm1_1296m",
 140         "clk1000m",
 141         "clk648m",
 142         "clk1600m",
 143         "pll_audio_1800m",
 144         "pll_vga_1800m",
 145 };
 146
 147 PNAME(cpu_periclk_p) = {
 148         "osc24m",
 149         "clk500m",
 150         "clk594m",
 151         "clk466m",
 152         "clk294m",
 153         "clk334m",
 154         "clk250m",
 155         "clk125m",
 156 };
 157
 158 PNAME(a53_coreclk_p) = {
 159         "osc24m",
 160         "clk1000m",
 161         "pll_mm0_1188m",
 162         "clk648m",
 163         "clk500m",
 164         "clk800m",
 165         "clk1600m",
 166         "pll_audio_1800m",
 167 };
 168
 169 PNAME(sec_wclk_p) = {
 170         "osc24m",
 171         "clk396m",
 172         "clk334m",
 173         "clk297m",
 174         "clk250m",
 175         "clk198m",
 176         "clk148m5",
 177         "clk99m",
 178 };
 179
 180 PNAME(sd_nand_wclk_p) = {
 181         "osc24m",
 182         "clk49m5",
 183         "clk99m",
 184         "clk198m",
 185         "clk167m",
 186         "clk148m5",
 187         "clk125m",
 188         "clk216m",
 189 };
 190
 191 PNAME(emmc_wclk_p) = {
 192         "osc24m",
 193         "clk198m",
 194         "clk99m",
 195         "clk396m",
 196         "clk334m",
 197         "clk297m",
 198         "clk250m",
 199         "clk148m5",
 200 };
 201
 202 PNAME(clk32_p) = {
 203         "osc32k",
 204         "clk32k768",
 205 };
 206
 207 PNAME(usb_ref24m_p) = {
 208         "osc32k",
 209         "clk32k768",
 210 };
 211
 212 PNAME(sys_noc_alck_p) = {
 213         "osc24m",
 214         "clk250m",
 215         "clk198m",
 216         "clk148m5",
 217         "clk108m",
 218         "clk54m",
 219         "clk216m",
 220         "clk240m",
 221 };
 222
 223 PNAME(vde_aclk_p) = {
 224         "clk334m",
 225         "clk594m",
 226         "clk500m",
 227         "clk432m",
 228         "clk480m",
 229         "clk297m",
 230         "clk_vga",  /*600MHz*/
 231         "clk294m",
 232 };
 233
 234 PNAME(vce_aclk_p) = {
 235         "clk334m",
 236         "clk594m",
 237         "clk500m",
 238         "clk432m",
 239         "clk396m",
 240         "clk297m",
 241         "clk_vga",  /*600MHz*/
 242         "clk294m",
 243 };
 244
 245 PNAME(hde_aclk_p) = {
 246         "clk334m",
 247         "clk594m",
 248         "clk500m",
 249         "clk432m",
 250         "clk396m",
 251         "clk297m",
 252         "clk_vga",  /*600MHz*/
 253         "clk294m",
 254 };
 255
 256 PNAME(gpu_aclk_p) = {
 257         "clk334m",
 258         "clk648m",
 259         "clk594m",
 260         "clk500m",
 261         "clk396m",
 262         "clk297m",
 263         "clk_vga",  /*600MHz*/
 264         "clk294m",
 265 };
 266
 267 PNAME(sappu_aclk_p) = {
 268         "clk396m",
 269         "clk500m",
 270         "clk250m",
 271         "clk148m5",
 272 };
 273
 274 PNAME(sappu_wclk_p) = {
 275         "clk198m",
 276         "clk396m",
 277         "clk334m",
 278         "clk297m",
 279         "clk250m",
 280         "clk148m5",
 281         "clk125m",
 282         "clk99m",
 283 };
 284
 285 PNAME(vou_aclk_p) = {
 286         "clk334m",
 287         "clk594m",
 288         "clk500m",
 289         "clk432m",
 290         "clk396m",
 291         "clk297m",
 292         "clk_vga",  /*600MHz*/
 293         "clk294m",
 294 };
 295
 296 PNAME(vou_main_wclk_p) = {
 297         "clk108m",
 298         "clk594m",
 299         "clk297m",
 300         "clk148m5",
 301         "clk74m25",
 302         "clk54m",
 303         "clk27m",
 304         "clk_vga",
 305 };
 306
 307 PNAME(vou_aux_wclk_p) = {
 308         "clk108m",
 309         "clk148m5",
 310         "clk74m25",
 311         "clk54m",
 312         "clk27m",
 313         "clk_vga",
 314         "clk54m_mm0",
 315         "clk"
 316 };
 317
 318 PNAME(vou_ppu_wclk_p) = {
 319         "clk334m",
 320         "clk432m",
 321         "clk396m",
 322         "clk297m",
 323         "clk250m",
 324         "clk125m",
 325         "clk198m",
 326         "clk99m",
 327 };
 328
 329 PNAME(vga_i2c_wclk_p) = {
 330         "osc24m",
 331         "clk99m",
 332 };
 333
 334 PNAME(viu_m0_aclk_p) = {
 335         "clk334m",
 336         "clk432m",
 337         "clk396m",
 338         "clk297m",
 339         "clk250m",
 340         "clk125m",
 341         "clk198m",
 342         "osc24m",
 343 };
 344
 345 PNAME(viu_m1_aclk_p) = {
 346         "clk198m",
 347         "clk250m",
 348         "clk297m",
 349         "clk125m",
 350         "clk396m",
 351         "clk334m",
 352         "clk148m5",
 353         "osc24m",
 354 };
 355
 356 PNAME(viu_clk_p) = {
 357         "clk198m",
 358         "clk334m",
 359         "clk297m",
 360         "clk250m",
 361         "clk396m",
 362         "clk125m",
 363         "clk99m",
 364         "clk148m5",
 365 };
 366
 367 PNAME(viu_jpeg_clk_p) = {
 368         "clk334m",
 369         "clk480m",
 370         "clk432m",
 371         "clk396m",
 372         "clk297m",
 373         "clk250m",
 374         "clk125m",
 375         "clk198m",
 376 };
 377
 378 PNAME(ts_sys_clk_p) = {
 379         "clk192m",
 380         "clk167m",
 381         "clk125m",
 382         "clk99m",
 383 };
 384
 385 PNAME(wdt_ares_p) = {
 386         "osc24m",
 387         "clk32k"
 388 };
 389
 390 static struct clk_zx_pll zx296718_pll_clk[] = {
 391         ZX296718_PLL("pll_cpu", "osc24m",       PLL_CPU_REG,    pll_cpu_table),
 392         ZX296718_PLL("pll_vga", "osc24m",       PLL_VGA_REG,    pll_vga_table),
 393 };
 394
 395 static struct zx_clk_fixed_factor top_ffactor_clk[] = {
 396         FFACTOR(0, "clk4m",             "osc24m", 1, 6,  0),
 397         FFACTOR(0, "clk2m",             "osc24m", 1, 12, 0),
 398         /* pll cpu */
 399         FFACTOR(0, "clk1600m",          "pll_cpu", 1, 1, CLK_SET_RATE_PARENT),
 400         FFACTOR(0, "clk800m",           "pll_cpu", 1, 2, CLK_SET_RATE_PARENT),
 401         /* pll mac */
 402         FFACTOR(0, "clk25m",            "pll_mac", 1, 40, 0),
 403         FFACTOR(0, "clk125m",           "pll_mac", 1, 8, 0),
 404         FFACTOR(0, "clk250m",           "pll_mac", 1, 4, 0),
 405         FFACTOR(0, "clk50m",            "pll_mac", 1, 20, 0),
 406         FFACTOR(0, "clk500m",           "pll_mac", 1, 2, 0),
 407         FFACTOR(0, "clk1000m",          "pll_mac", 1, 1, 0),
 408         FFACTOR(0, "clk334m",           "pll_mac", 1, 3, 0),
 409         FFACTOR(0, "clk167m",           "pll_mac", 1, 6, 0),
 410         /* pll mm */
 411         FFACTOR(0, "clk54m_mm0",        "pll_mm0", 1, 22, 0),
 412         FFACTOR(0, "clk74m25",          "pll_mm0", 1, 16, 0),
 413         FFACTOR(0, "clk148m5",          "pll_mm0", 1, 8, 0),
 414         FFACTOR(0, "clk297m",           "pll_mm0", 1, 4, 0),
 415         FFACTOR(0, "clk594m",           "pll_mm0", 1, 2, 0),
 416         FFACTOR(0, "pll_mm0_1188m",     "pll_mm0", 1, 1, 0),
 417         FFACTOR(0, "clk396m",           "pll_mm0", 1, 3, 0),
 418         FFACTOR(0, "clk198m",           "pll_mm0", 1, 6, 0),
 419         FFACTOR(0, "clk99m",            "pll_mm0", 1, 12, 0),
 420         FFACTOR(0, "clk49m5",           "pll_mm0", 1, 24, 0),
 421         /* pll mm */
 422         FFACTOR(0, "clk324m",           "pll_mm1", 1, 4, 0),
 423         FFACTOR(0, "clk648m",           "pll_mm1", 1, 2, 0),
 424         FFACTOR(0, "pll_mm1_1296m",     "pll_mm1", 1, 1, 0),
 425         FFACTOR(0, "clk216m",           "pll_mm1", 1, 6, 0),
 426         FFACTOR(0, "clk432m",           "pll_mm1", 1, 3, 0),
 427         FFACTOR(0, "clk108m",           "pll_mm1", 1, 12, 0),
 428         FFACTOR(0, "clk72m",            "pll_mm1", 1, 18, 0),
 429         FFACTOR(0, "clk27m",            "pll_mm1", 1, 48, 0),
 430         FFACTOR(0, "clk54m",            "pll_mm1", 1, 24, 0),
 431         /* vga */
 432         FFACTOR(0, "pll_vga_1800m",     "pll_vga", 1, 1, 0),
 433         FFACTOR(0, "clk_vga",           "pll_vga", 1, 1, CLK_SET_RATE_PARENT),
 434         /* pll ddr */
 435         FFACTOR(0, "clk466m",           "pll_ddr", 1, 2, 0),
 436
 437         /* pll audio */
 438         FFACTOR(0, "pll_audio_1800m",   "pll_audio", 1, 1, 0),
 439         FFACTOR(0, "clk32k768",         "pll_audio", 1, 27000, 0),
 440         FFACTOR(0, "clk16m384",         "pll_audio", 1, 54, 0),
 441         FFACTOR(0, "clk294m",           "pll_audio", 1, 3, 0),
 442
 443         /* pll hsic*/
 444         FFACTOR(0, "clk240m",           "pll_hsic", 1, 4, 0),
 445         FFACTOR(0, "clk480m",           "pll_hsic", 1, 2, 0),
 446         FFACTOR(0, "clk192m",           "pll_hsic", 1, 5, 0),
 447         FFACTOR(0, "clk_pll_24m",       "pll_hsic", 1, 40, 0),
 448         FFACTOR(0, "emmc_mux_div2",     "emmc_mux", 1, 2, CLK_SET_RATE_PARENT),
 449 };
 450
 451 static const struct clk_div_table noc_div_table[] = {
 452         { .val = 1, .div = 2, },
 453         { .val = 3, .div = 4, },
 454 };
 455 static struct zx_clk_div top_div_clk[] = {
 456         DIV_T(0, "sys_noc_hclk", "sys_noc_aclk", TOP_CLK_DIV0, 0, 2, 0, noc_div_table),
 457         DIV_T(0, "sys_noc_pclk", "sys_noc_aclk", TOP_CLK_DIV0, 4, 2, 0, noc_div_table),
 458 };
 459
 460 static struct zx_clk_mux top_mux_clk[] = {
 461         MUX(0, "dbg_mux",        dbg_wclk_p,      TOP_CLK_MUX0, 12, 2),
 462         MUX(0, "a72_mux",        a72_coreclk_p,   TOP_CLK_MUX0, 8, 3),
 463         MUX(0, "cpu_peri_mux",   cpu_periclk_p,   TOP_CLK_MUX0, 4, 3),
 464         MUX_F(0, "a53_mux",      a53_coreclk_p,   TOP_CLK_MUX0, 0, 3, CLK_SET_RATE_PARENT, 0),
 465         MUX(0, "sys_noc_aclk",   sys_noc_alck_p,  TOP_CLK_MUX1, 0, 3),
 466         MUX(0, "sec_mux",        sec_wclk_p,      TOP_CLK_MUX2, 16, 3),
 467         MUX(0, "sd1_mux",        sd_nand_wclk_p,  TOP_CLK_MUX2, 12, 3),
 468         MUX(0, "sd0_mux",        sd_nand_wclk_p,  TOP_CLK_MUX2, 8, 3),
 469         MUX(0, "emmc_mux",       emmc_wclk_p,     TOP_CLK_MUX2, 4, 3),
 470         MUX(0, "nand_mux",       sd_nand_wclk_p,  TOP_CLK_MUX2, 0, 3),
 471         MUX(0, "usb_ref24m_mux", usb_ref24m_p,    TOP_CLK_MUX9, 16, 1),
 472         MUX(0, "clk32k",         clk32_p,         TOP_CLK_MUX9, 12, 1),
 473         MUX_F(0, "wdt_mux",      wdt_ares_p,      TOP_CLK_MUX9, 8, 1, CLK_SET_RATE_PARENT, 0),
 474         MUX(0, "timer_mux",      osc,             TOP_CLK_MUX9, 4, 1),
 475         MUX(0, "vde_mux",        vde_aclk_p,      TOP_CLK_MUX4,  0, 3),
 476         MUX(0, "vce_mux",        vce_aclk_p,      TOP_CLK_MUX4,  4, 3),
 477         MUX(0, "hde_mux",        hde_aclk_p,      TOP_CLK_MUX4,  8, 3),
 478         MUX(0, "gpu_mux",        gpu_aclk_p,      TOP_CLK_MUX5,  0, 3),
 479         MUX(0, "sappu_a_mux",    sappu_aclk_p,    TOP_CLK_MUX5,  4, 2),
 480         MUX(0, "sappu_w_mux",    sappu_wclk_p,    TOP_CLK_MUX5,  8, 3),
 481         MUX(0, "vou_a_mux",      vou_aclk_p,      TOP_CLK_MUX7,  0, 3),
 482         MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7,  4, 3, CLK_SET_RATE_PARENT, 0),
 483         MUX_F(0, "vou_aux_w_mux",  vou_aux_wclk_p,  TOP_CLK_MUX7,  8, 3, CLK_SET_RATE_PARENT, 0),
 484         MUX(0, "vou_ppu_w_mux",  vou_ppu_wclk_p,  TOP_CLK_MUX7, 12, 3),
 485         MUX(0, "vga_i2c_mux",    vga_i2c_wclk_p,  TOP_CLK_MUX7, 16, 1),
 486         MUX(0, "viu_m0_a_mux",   viu_m0_aclk_p,   TOP_CLK_MUX6,  0, 3),
 487         MUX(0, "viu_m1_a_mux",   viu_m1_aclk_p,   TOP_CLK_MUX6,  4, 3),
 488         MUX(0, "viu_w_mux",      viu_clk_p,       TOP_CLK_MUX6,  8, 3),
 489         MUX(0, "viu_jpeg_w_mux", viu_jpeg_clk_p,  TOP_CLK_MUX6, 12, 3),
 490         MUX(0, "ts_sys_mux",     ts_sys_clk_p,    TOP_CLK_MUX6, 16, 2),
 491 };
 492
 493 static struct zx_clk_gate top_gate_clk[] = {
 494         GATE(CPU_DBG_GATE,    "dbg_wclk",        "dbg_mux",        TOP_CLK_GATE0, 4, CLK_SET_RATE_PARENT, 0),
 495         GATE(A72_GATE,        "a72_coreclk",     "a72_mux",        TOP_CLK_GATE0, 3, CLK_SET_RATE_PARENT, 0),
 496         GATE(CPU_PERI_GATE,   "cpu_peri",        "cpu_peri_mux",   TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
 497         GATE(A53_GATE,        "a53_coreclk",     "a53_mux",        TOP_CLK_GATE0, 0, CLK_SET_RATE_PARENT, 0),
 498         GATE(SD1_WCLK,        "sd1_wclk",        "sd1_mux",        TOP_CLK_GATE1, 13, CLK_SET_RATE_PARENT, 0),
 499         GATE(SD0_WCLK,        "sd0_wclk",        "sd0_mux",        TOP_CLK_GATE1, 9, CLK_SET_RATE_PARENT, 0),
 500         GATE(EMMC_WCLK,       "emmc_wclk",       "emmc_mux_div2",  TOP_CLK_GATE0, 5, CLK_SET_RATE_PARENT, 0),
 501         GATE(EMMC_NAND_AXI,   "emmc_nand_aclk",  "sys_noc_aclk",   TOP_CLK_GATE1, 4, CLK_SET_RATE_PARENT, 0),
 502         GATE(NAND_WCLK,       "nand_wclk",       "nand_mux",       TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
 503         GATE(EMMC_NAND_AHB,   "emmc_nand_hclk",  "sys_noc_hclk",   TOP_CLK_GATE1, 0, CLK_SET_RATE_PARENT, 0),
 504         GATE(0,               "lsp1_pclk",       "sys_noc_pclk",   TOP_CLK_GATE2, 31, 0,                  0),
 505         GATE(LSP1_148M5,      "lsp1_148m5",      "clk148m5",       TOP_CLK_GATE2, 30, 0,                  0),
 506         GATE(LSP1_99M,        "lsp1_99m",        "clk99m",         TOP_CLK_GATE2, 29, 0,                  0),
 507         GATE(LSP1_24M,        "lsp1_24m",        "osc24m",         TOP_CLK_GATE2, 28, 0,                  0),
 508         GATE(LSP0_74M25,      "lsp0_74m25",      "clk74m25",       TOP_CLK_GATE2, 25, 0,                  0),
 509         GATE(0,               "lsp0_pclk",       "sys_noc_pclk",   TOP_CLK_GATE2, 24, 0,                  0),
 510         GATE(LSP0_32K,        "lsp0_32k",        "osc32k",         TOP_CLK_GATE2, 23, 0,                  0),
 511         GATE(LSP0_148M5,      "lsp0_148m5",      "clk148m5",       TOP_CLK_GATE2, 22, 0,                  0),
 512         GATE(LSP0_99M,        "lsp0_99m",        "clk99m",         TOP_CLK_GATE2, 21, 0,                  0),
 513         GATE(LSP0_24M,        "lsp0_24m",        "osc24m",         TOP_CLK_GATE2, 20, 0,                  0),
 514         GATE(AUDIO_99M,       "audio_99m",       "clk99m",         TOP_CLK_GATE5, 27, 0,                  0),
 515         GATE(AUDIO_24M,       "audio_24m",       "osc24m",         TOP_CLK_GATE5, 28, 0,                  0),
 516         GATE(AUDIO_16M384,    "audio_16m384",    "clk16m384",      TOP_CLK_GATE5, 29, 0,                  0),
 517         GATE(AUDIO_32K,       "audio_32k",       "clk32k",         TOP_CLK_GATE5, 30, 0,                  0),
 518         GATE(WDT_WCLK,        "wdt_wclk",        "wdt_mux",        TOP_CLK_GATE6, 9, CLK_SET_RATE_PARENT, 0),
 519         GATE(TIMER_WCLK,      "timer_wclk",      "timer_mux",      TOP_CLK_GATE6, 5, CLK_SET_RATE_PARENT, 0),
 520         GATE(VDE_ACLK,        "vde_aclk",        "vde_mux",        TOP_CLK_GATE3, 0,  CLK_SET_RATE_PARENT, 0),
 521         GATE(VCE_ACLK,        "vce_aclk",        "vce_mux",        TOP_CLK_GATE3, 4,  CLK_SET_RATE_PARENT, 0),
 522         GATE(HDE_ACLK,        "hde_aclk",        "hde_mux",        TOP_CLK_GATE3, 8,  CLK_SET_RATE_PARENT, 0),
 523         GATE(GPU_ACLK,        "gpu_aclk",        "gpu_mux",        TOP_CLK_GATE3, 16, CLK_SET_RATE_PARENT, 0),
 524         GATE(SAPPU_ACLK,      "sappu_aclk",      "sappu_a_mux",    TOP_CLK_GATE3, 20, CLK_SET_RATE_PARENT, 0),
 525         GATE(SAPPU_WCLK,      "sappu_wclk",      "sappu_w_mux",    TOP_CLK_GATE3, 22, CLK_SET_RATE_PARENT, 0),
 526         GATE(VOU_ACLK,        "vou_aclk",        "vou_a_mux",      TOP_CLK_GATE4, 16, CLK_SET_RATE_PARENT, 0),
 527         GATE(VOU_MAIN_WCLK,   "vou_main_wclk",   "vou_main_w_mux", TOP_CLK_GATE4, 18, CLK_SET_RATE_PARENT, 0),
 528         GATE(VOU_AUX_WCLK,    "vou_aux_wclk",    "vou_aux_w_mux",  TOP_CLK_GATE4, 19, CLK_SET_RATE_PARENT, 0),
 529         GATE(VOU_PPU_WCLK,    "vou_ppu_wclk",    "vou_ppu_w_mux",  TOP_CLK_GATE4, 20, CLK_SET_RATE_PARENT, 0),
 530         GATE(MIPI_CFG_CLK,    "mipi_cfg_clk",    "osc24m",         TOP_CLK_GATE4, 21, 0,                   0),
 531         GATE(VGA_I2C_WCLK,    "vga_i2c_wclk",    "vga_i2c_mux",    TOP_CLK_GATE4, 23, CLK_SET_RATE_PARENT, 0),
 532         GATE(MIPI_REF_CLK,    "mipi_ref_clk",    "clk27m",         TOP_CLK_GATE4, 24, 0,                   0),
 533         GATE(HDMI_OSC_CEC,    "hdmi_osc_cec",    "clk2m",          TOP_CLK_GATE4, 22, 0,                   0),
 534         GATE(HDMI_OSC_CLK,    "hdmi_osc_clk",    "clk240m",        TOP_CLK_GATE4, 25, 0,                   0),
 535         GATE(HDMI_XCLK,       "hdmi_xclk",       "osc24m",         TOP_CLK_GATE4, 26, 0,                   0),
 536         GATE(VIU_M0_ACLK,     "viu_m0_aclk",     "viu_m0_a_mux",   TOP_CLK_GATE4, 0,  CLK_SET_RATE_PARENT, 0),
 537         GATE(VIU_M1_ACLK,     "viu_m1_aclk",     "viu_m1_a_mux",   TOP_CLK_GATE4, 1,  CLK_SET_RATE_PARENT, 0),
 538         GATE(VIU_WCLK,        "viu_wclk",        "viu_w_mux",      TOP_CLK_GATE4, 2,  CLK_SET_RATE_PARENT, 0),
 539         GATE(VIU_JPEG_WCLK,   "viu_jpeg_wclk",   "viu_jpeg_w_mux", TOP_CLK_GATE4, 3,  CLK_SET_RATE_PARENT, 0),
 540         GATE(VIU_CFG_CLK,     "viu_cfg_clk",     "osc24m",         TOP_CLK_GATE4, 6,  0,                   0),
 541         GATE(TS_SYS_WCLK,     "ts_sys_wclk",     "ts_sys_mux",     TOP_CLK_GATE5, 2,  CLK_SET_RATE_PARENT, 0),
 542         GATE(TS_SYS_108M,     "ts_sys_108m",     "clk108m",        TOP_CLK_GATE5, 3,  0,                   0),
 543         GATE(USB20_HCLK,      "usb20_hclk",      "sys_noc_hclk",   TOP_CLK_GATE2, 12, 0,                   0),
 544         GATE(USB20_PHY_CLK,   "usb20_phy_clk",   "usb_ref24m_mux", TOP_CLK_GATE2, 13, 0,                   0),
 545         GATE(USB21_HCLK,      "usb21_hclk",      "sys_noc_hclk",   TOP_CLK_GATE2, 14, 0,                   0),
 546         GATE(USB21_PHY_CLK,   "usb21_phy_clk",   "usb_ref24m_mux", TOP_CLK_GATE2, 15, 0,                   0),
 547         GATE(GMAC_RMIICLK,    "gmac_rmii_clk",   "clk50m",         TOP_CLK_GATE2, 3, 0,                    0),
 548         GATE(GMAC_PCLK,       "gmac_pclk",       "clk198m",        TOP_CLK_GATE2, 1, 0,                    0),
 549         GATE(GMAC_ACLK,       "gmac_aclk",       "clk49m5",        TOP_CLK_GATE2, 0, 0,                    0),
 550         GATE(GMAC_RFCLK,      "gmac_refclk",     "clk25m",         TOP_CLK_GATE2, 4, 0,                    0),
 551         GATE(SD1_AHB,         "sd1_hclk",        "sys_noc_hclk",   TOP_CLK_GATE1, 12,  0,                  0),
 552         GATE(SD0_AHB,         "sd0_hclk",        "sys_noc_hclk",   TOP_CLK_GATE1, 8,  0,                   0),
 553         GATE(TEMPSENSOR_GATE, "tempsensor_gate", "clk4m",          TOP_CLK_GATE5, 31,  0,                  0),
 554 };
 555
 556 static struct clk_hw_onecell_data top_hw_onecell_data = {
 557         .num = TOP_NR_CLKS,
 558         .hws = {
 559                 [TOP_NR_CLKS - 1] = NULL,
 560         },
 561 };
 562
 563 static int __init top_clocks_init(struct device_node *np)
 564 {
 565         void __iomem *reg_base;
 566         int i, ret;
 567         const char *name;
 568
 569         reg_base = of_iomap(np, 0);
 570         if (!reg_base) {
 571                 pr_err("%s: Unable to map clk base\n", __func__);
 572                 return -ENXIO;
 573         }
 574
 575         for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) {
 576                 zx296718_pll_clk[i].reg_base += (uintptr_t)reg_base;
 577                 name = zx296718_pll_clk[i].hw.init->name;
 578                 ret = clk_hw_register(NULL, &zx296718_pll_clk[i].hw);
 579                 if (ret)
 580                         pr_warn("top clk %s init error!\n", name);
 581         }
 582
 583         for (i = 0; i < ARRAY_SIZE(top_ffactor_clk); i++) {
 584                 if (top_ffactor_clk[i].id)
 585                         top_hw_onecell_data.hws[top_ffactor_clk[i].id] =
 586                                         &top_ffactor_clk[i].factor.hw;
 587
 588                 name = top_ffactor_clk[i].factor.hw.init->name;
 589                 ret = clk_hw_register(NULL, &top_ffactor_clk[i].factor.hw);
 590                 if (ret)
 591                         pr_warn("top clk %s init error!\n", name);
 592         }
 593
 594         for (i = 0; i < ARRAY_SIZE(top_mux_clk); i++) {
 595                 if (top_mux_clk[i].id)
 596                         top_hw_onecell_data.hws[top_mux_clk[i].id] =
 597                                         &top_mux_clk[i].mux.hw;
 598
 599                 top_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 600                 name = top_mux_clk[i].mux.hw.init->name;
 601                 ret = clk_hw_register(NULL, &top_mux_clk[i].mux.hw);
 602                 if (ret)
 603                         pr_warn("top clk %s init error!\n", name);
 604         }
 605
 606         for (i = 0; i < ARRAY_SIZE(top_gate_clk); i++) {
 607                 if (top_gate_clk[i].id)
 608                         top_hw_onecell_data.hws[top_gate_clk[i].id] =
 609                                         &top_gate_clk[i].gate.hw;
 610
 611                 top_gate_clk[i].gate.reg += (uintptr_t)reg_base;
 612                 name = top_gate_clk[i].gate.hw.init->name;
 613                 ret = clk_hw_register(NULL, &top_gate_clk[i].gate.hw);
 614                 if (ret)
 615                         pr_warn("top clk %s init error!\n", name);
 616         }
 617
 618         for (i = 0; i < ARRAY_SIZE(top_div_clk); i++) {
 619                 if (top_div_clk[i].id)
 620                         top_hw_onecell_data.hws[top_div_clk[i].id] =
 621                                         &top_div_clk[i].div.hw;
 622
 623                 top_div_clk[i].div.reg += (uintptr_t)reg_base;
 624                 name = top_div_clk[i].div.hw.init->name;
 625                 ret = clk_hw_register(NULL, &top_div_clk[i].div.hw);
 626                 if (ret)
 627                         pr_warn("top clk %s init error!\n", name);
 628         }
 629
 630         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
 631                                      &top_hw_onecell_data);
 632         if (ret) {
 633                 pr_err("failed to register top clk provider: %d\n", ret);
 634                 return ret;
 635         }
 636
 637         return 0;
 638 }
 639
 640 static const struct clk_div_table common_even_div_table[] = {
 641         { .val = 0, .div = 1, },
 642         { .val = 1, .div = 2, },
 643         { .val = 3, .div = 4, },
 644         { .val = 5, .div = 6, },
 645         { .val = 7, .div = 8, },
 646         { .val = 9, .div = 10, },
 647         { .val = 11, .div = 12, },
 648         { .val = 13, .div = 14, },
 649         { .val = 15, .div = 16, },
 650 };
 651
 652 static const struct clk_div_table common_div_table[] = {
 653         { .val = 0, .div = 1, },
 654         { .val = 1, .div = 2, },
 655         { .val = 2, .div = 3, },
 656         { .val = 3, .div = 4, },
 657         { .val = 4, .div = 5, },
 658         { .val = 5, .div = 6, },
 659         { .val = 6, .div = 7, },
 660         { .val = 7, .div = 8, },
 661         { .val = 8, .div = 9, },
 662         { .val = 9, .div = 10, },
 663         { .val = 10, .div = 11, },
 664         { .val = 11, .div = 12, },
 665         { .val = 12, .div = 13, },
 666         { .val = 13, .div = 14, },
 667         { .val = 14, .div = 15, },
 668         { .val = 15, .div = 16, },
 669 };
 670
 671 PNAME(lsp0_wclk_common_p) = {
 672         "lsp0_24m",
 673         "lsp0_99m",
 674 };
 675
 676 PNAME(lsp0_wclk_timer3_p) = {
 677         "timer3_div",
 678         "lsp0_32k"
 679 };
 680
 681 PNAME(lsp0_wclk_timer4_p) = {
 682         "timer4_div",
 683         "lsp0_32k"
 684 };
 685
 686 PNAME(lsp0_wclk_timer5_p) = {
 687         "timer5_div",
 688         "lsp0_32k"
 689 };
 690
 691 PNAME(lsp0_wclk_spifc0_p) = {
 692         "lsp0_148m5",
 693         "lsp0_24m",
 694         "lsp0_99m",
 695         "lsp0_74m25"
 696 };
 697
 698 PNAME(lsp0_wclk_ssp_p) = {
 699         "lsp0_148m5",
 700         "lsp0_99m",
 701         "lsp0_24m",
 702 };
 703
 704 static struct zx_clk_mux lsp0_mux_clk[] = {
 705         MUX(0, "timer3_wclk_mux", lsp0_wclk_timer3_p, LSP0_TIMER3_CLK, 4, 1),
 706         MUX(0, "timer4_wclk_mux", lsp0_wclk_timer4_p, LSP0_TIMER4_CLK, 4, 1),
 707         MUX(0, "timer5_wclk_mux", lsp0_wclk_timer5_p, LSP0_TIMER5_CLK, 4, 1),
 708         MUX(0, "uart3_wclk_mux",  lsp0_wclk_common_p, LSP0_UART3_CLK,  4, 1),
 709         MUX(0, "uart1_wclk_mux",  lsp0_wclk_common_p, LSP0_UART1_CLK,  4, 1),
 710         MUX(0, "uart2_wclk_mux",  lsp0_wclk_common_p, LSP0_UART2_CLK,  4, 1),
 711         MUX(0, "spifc0_wclk_mux", lsp0_wclk_spifc0_p, LSP0_SPIFC0_CLK, 4, 2),
 712         MUX(0, "i2c4_wclk_mux",   lsp0_wclk_common_p, LSP0_I2C4_CLK,   4, 1),
 713         MUX(0, "i2c5_wclk_mux",   lsp0_wclk_common_p, LSP0_I2C5_CLK,   4, 1),
 714         MUX(0, "ssp0_wclk_mux",   lsp0_wclk_ssp_p,    LSP0_SSP0_CLK,   4, 1),
 715         MUX(0, "ssp1_wclk_mux",   lsp0_wclk_ssp_p,    LSP0_SSP1_CLK,   4, 1),
 716         MUX(0, "i2c3_wclk_mux",   lsp0_wclk_common_p, LSP0_I2C3_CLK,   4, 1),
 717 };
 718
 719 static struct zx_clk_gate lsp0_gate_clk[] = {
 720         GATE(LSP0_TIMER3_WCLK, "timer3_wclk", "timer3_wclk_mux", LSP0_TIMER3_CLK, 1, CLK_SET_RATE_PARENT, 0),
 721         GATE(LSP0_TIMER4_WCLK, "timer4_wclk", "timer4_wclk_mux", LSP0_TIMER4_CLK, 1, CLK_SET_RATE_PARENT, 0),
 722         GATE(LSP0_TIMER5_WCLK, "timer5_wclk", "timer5_wclk_mux", LSP0_TIMER5_CLK, 1, CLK_SET_RATE_PARENT, 0),
 723         GATE(LSP0_UART3_WCLK,  "uart3_wclk",  "uart3_wclk_mux",  LSP0_UART3_CLK,  1, CLK_SET_RATE_PARENT, 0),
 724         GATE(LSP0_UART1_WCLK,  "uart1_wclk",  "uart1_wclk_mux",  LSP0_UART1_CLK,  1, CLK_SET_RATE_PARENT, 0),
 725         GATE(LSP0_UART2_WCLK,  "uart2_wclk",  "uart2_wclk_mux",  LSP0_UART2_CLK,  1, CLK_SET_RATE_PARENT, 0),
 726         GATE(LSP0_SPIFC0_WCLK, "spifc0_wclk", "spifc0_wclk_mux", LSP0_SPIFC0_CLK, 1, CLK_SET_RATE_PARENT, 0),
 727         GATE(LSP0_I2C4_WCLK,   "i2c4_wclk",   "i2c4_wclk_mux",   LSP0_I2C4_CLK,   1, CLK_SET_RATE_PARENT, 0),
 728         GATE(LSP0_I2C5_WCLK,   "i2c5_wclk",   "i2c5_wclk_mux",   LSP0_I2C5_CLK,   1, CLK_SET_RATE_PARENT, 0),
 729         GATE(LSP0_SSP0_WCLK,   "ssp0_wclk",   "ssp0_div",        LSP0_SSP0_CLK,   1, CLK_SET_RATE_PARENT, 0),
 730         GATE(LSP0_SSP1_WCLK,   "ssp1_wclk",   "ssp1_div",        LSP0_SSP1_CLK,   1, CLK_SET_RATE_PARENT, 0),
 731         GATE(LSP0_I2C3_WCLK,   "i2c3_wclk",   "i2c3_wclk_mux",   LSP0_I2C3_CLK,   1, CLK_SET_RATE_PARENT, 0),
 732 };
 733
 734 static struct zx_clk_div lsp0_div_clk[] = {
 735         DIV_T(0, "timer3_div", "lsp0_24m", LSP0_TIMER3_CLK,  12, 4, 0, common_even_div_table),
 736         DIV_T(0, "timer4_div", "lsp0_24m", LSP0_TIMER4_CLK,  12, 4, 0, common_even_div_table),
 737         DIV_T(0, "timer5_div", "lsp0_24m", LSP0_TIMER5_CLK,  12, 4, 0, common_even_div_table),
 738         DIV_T(0, "ssp0_div", "ssp0_wclk_mux", LSP0_SSP0_CLK, 12, 4, 0, common_even_div_table),
 739         DIV_T(0, "ssp1_div", "ssp1_wclk_mux", LSP0_SSP1_CLK, 12, 4, 0, common_even_div_table),
 740 };
 741
 742 static struct clk_hw_onecell_data lsp0_hw_onecell_data = {
 743         .num = LSP0_NR_CLKS,
 744         .hws = {
 745                 [LSP0_NR_CLKS - 1] = NULL,
 746         },
 747 };
 748
 749 static int __init lsp0_clocks_init(struct device_node *np)
 750 {
 751         void __iomem *reg_base;
 752         int i, ret;
 753         const char *name;
 754
 755         reg_base = of_iomap(np, 0);
 756         if (!reg_base) {
 757                 pr_err("%s: Unable to map clk base\n", __func__);
 758                 return -ENXIO;
 759         }
 760
 761         for (i = 0; i < ARRAY_SIZE(lsp0_mux_clk); i++) {
 762                 if (lsp0_mux_clk[i].id)
 763                         lsp0_hw_onecell_data.hws[lsp0_mux_clk[i].id] =
 764                                         &lsp0_mux_clk[i].mux.hw;
 765
 766                 lsp0_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 767                 name = lsp0_mux_clk[i].mux.hw.init->name;
 768                 ret = clk_hw_register(NULL, &lsp0_mux_clk[i].mux.hw);
 769                 if (ret)
 770                         pr_warn("lsp0 clk %s init error!\n", name);
 771         }
 772
 773         for (i = 0; i < ARRAY_SIZE(lsp0_gate_clk); i++) {
 774                 if (lsp0_gate_clk[i].id)
 775                         lsp0_hw_onecell_data.hws[lsp0_gate_clk[i].id] =
 776                                         &lsp0_gate_clk[i].gate.hw;
 777
 778                 lsp0_gate_clk[i].gate.reg += (uintptr_t)reg_base;
 779                 name = lsp0_gate_clk[i].gate.hw.init->name;
 780                 ret = clk_hw_register(NULL, &lsp0_gate_clk[i].gate.hw);
 781                 if (ret)
 782                         pr_warn("lsp0 clk %s init error!\n", name);
 783         }
 784
 785         for (i = 0; i < ARRAY_SIZE(lsp0_div_clk); i++) {
 786                 if (lsp0_div_clk[i].id)
 787                         lsp0_hw_onecell_data.hws[lsp0_div_clk[i].id] =
 788                                         &lsp0_div_clk[i].div.hw;
 789
 790                 lsp0_div_clk[i].div.reg += (uintptr_t)reg_base;
 791                 name = lsp0_div_clk[i].div.hw.init->name;
 792                 ret = clk_hw_register(NULL, &lsp0_div_clk[i].div.hw);
 793                 if (ret)
 794                         pr_warn("lsp0 clk %s init error!\n", name);
 795         }
 796
 797         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
 798                                      &lsp0_hw_onecell_data);
 799         if (ret) {
 800                 pr_err("failed to register lsp0 clk provider: %d\n", ret);
 801                 return ret;
 802         }
 803
 804         return 0;
 805 }
 806
 807 PNAME(lsp1_wclk_common_p) = {
 808         "lsp1_24m",
 809         "lsp1_99m",
 810 };
 811
 812 PNAME(lsp1_wclk_ssp_p) = {
 813         "lsp1_148m5",
 814         "lsp1_99m",
 815         "lsp1_24m",
 816 };
 817
 818 static struct zx_clk_mux lsp1_mux_clk[] = {
 819         MUX(0, "uart4_wclk_mux", lsp1_wclk_common_p, LSP1_UART4_CLK, 4, 1),
 820         MUX(0, "uart5_wclk_mux", lsp1_wclk_common_p, LSP1_UART5_CLK, 4, 1),
 821         MUX(0, "pwm_wclk_mux",   lsp1_wclk_common_p, LSP1_PWM_CLK,   4, 1),
 822         MUX(0, "i2c2_wclk_mux",  lsp1_wclk_common_p, LSP1_I2C2_CLK,  4, 1),
 823         MUX(0, "ssp2_wclk_mux",  lsp1_wclk_ssp_p,    LSP1_SSP2_CLK,  4, 2),
 824         MUX(0, "ssp3_wclk_mux",  lsp1_wclk_ssp_p,    LSP1_SSP3_CLK,  4, 2),
 825         MUX(0, "ssp4_wclk_mux",  lsp1_wclk_ssp_p,    LSP1_SSP4_CLK,  4, 2),
 826         MUX(0, "usim1_wclk_mux", lsp1_wclk_common_p, LSP1_USIM1_CLK, 4, 1),
 827 };
 828
 829 static struct zx_clk_div lsp1_div_clk[] = {
 830         DIV_T(0, "pwm_div",  "pwm_wclk_mux",  LSP1_PWM_CLK,  12, 4, CLK_SET_RATE_PARENT, common_div_table),
 831         DIV_T(0, "ssp2_div", "ssp2_wclk_mux", LSP1_SSP2_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
 832         DIV_T(0, "ssp3_div", "ssp3_wclk_mux", LSP1_SSP3_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
 833         DIV_T(0, "ssp4_div", "ssp4_wclk_mux", LSP1_SSP4_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
 834 };
 835
 836 static struct zx_clk_gate lsp1_gate_clk[] = {
 837         GATE(LSP1_UART4_WCLK, "lsp1_uart4_wclk", "uart4_wclk_mux", LSP1_UART4_CLK, 1, CLK_SET_RATE_PARENT, 0),
 838         GATE(LSP1_UART5_WCLK, "lsp1_uart5_wclk", "uart5_wclk_mux", LSP1_UART5_CLK, 1, CLK_SET_RATE_PARENT, 0),
 839         GATE(LSP1_PWM_WCLK,   "lsp1_pwm_wclk",   "pwm_div",        LSP1_PWM_CLK,   1, CLK_SET_RATE_PARENT, 0),
 840         GATE(LSP1_PWM_PCLK,   "lsp1_pwm_pclk",   "lsp1_pclk",      LSP1_PWM_CLK,   0, 0,                   0),
 841         GATE(LSP1_I2C2_WCLK,  "lsp1_i2c2_wclk",  "i2c2_wclk_mux",  LSP1_I2C2_CLK,  1, CLK_SET_RATE_PARENT, 0),
 842         GATE(LSP1_SSP2_WCLK,  "lsp1_ssp2_wclk",  "ssp2_div",       LSP1_SSP2_CLK,  1, CLK_SET_RATE_PARENT, 0),
 843         GATE(LSP1_SSP3_WCLK,  "lsp1_ssp3_wclk",  "ssp3_div",       LSP1_SSP3_CLK,  1, CLK_SET_RATE_PARENT, 0),
 844         GATE(LSP1_SSP4_WCLK,  "lsp1_ssp4_wclk",  "ssp4_div",       LSP1_SSP4_CLK,  1, CLK_SET_RATE_PARENT, 0),
 845         GATE(LSP1_USIM1_WCLK, "lsp1_usim1_wclk", "usim1_wclk_mux", LSP1_USIM1_CLK, 1, CLK_SET_RATE_PARENT, 0),
 846 };
 847
 848 static struct clk_hw_onecell_data lsp1_hw_onecell_data = {
 849         .num = LSP1_NR_CLKS,
 850         .hws = {
 851                 [LSP1_NR_CLKS - 1] = NULL,
 852         },
 853 };
 854
 855 static int __init lsp1_clocks_init(struct device_node *np)
 856 {
 857         void __iomem *reg_base;
 858         int i, ret;
 859         const char *name;
 860
 861         reg_base = of_iomap(np, 0);
 862         if (!reg_base) {
 863                 pr_err("%s: Unable to map clk base\n", __func__);
 864                 return -ENXIO;
 865         }
 866
 867         for (i = 0; i < ARRAY_SIZE(lsp1_mux_clk); i++) {
 868                 if (lsp1_mux_clk[i].id)
 869                         lsp1_hw_onecell_data.hws[lsp1_mux_clk[i].id] =
 870                                         &lsp0_mux_clk[i].mux.hw;
 871
 872                 lsp1_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 873                 name = lsp1_mux_clk[i].mux.hw.init->name;
 874                 ret = clk_hw_register(NULL, &lsp1_mux_clk[i].mux.hw);
 875                 if (ret)
 876                         pr_warn("lsp1 clk %s init error!\n", name);
 877         }
 878
 879         for (i = 0; i < ARRAY_SIZE(lsp1_gate_clk); i++) {
 880                 if (lsp1_gate_clk[i].id)
 881                         lsp1_hw_onecell_data.hws[lsp1_gate_clk[i].id] =
 882                                         &lsp1_gate_clk[i].gate.hw;
 883
 884                 lsp1_gate_clk[i].gate.reg += (uintptr_t)reg_base;
 885                 name = lsp1_gate_clk[i].gate.hw.init->name;
 886                 ret = clk_hw_register(NULL, &lsp1_gate_clk[i].gate.hw);
 887                 if (ret)
 888                         pr_warn("lsp1 clk %s init error!\n", name);
 889         }
 890
 891         for (i = 0; i < ARRAY_SIZE(lsp1_div_clk); i++) {
 892                 if (lsp1_div_clk[i].id)
 893                         lsp1_hw_onecell_data.hws[lsp1_div_clk[i].id] =
 894                                         &lsp1_div_clk[i].div.hw;
 895
 896                 lsp1_div_clk[i].div.reg += (uintptr_t)reg_base;
 897                 name = lsp1_div_clk[i].div.hw.init->name;
 898                 ret = clk_hw_register(NULL, &lsp1_div_clk[i].div.hw);
 899                 if (ret)
 900                         pr_warn("lsp1 clk %s init error!\n", name);
 901         }
 902
 903         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
 904                                      &lsp1_hw_onecell_data);
 905         if (ret) {
 906                 pr_err("failed to register lsp1 clk provider: %d\n", ret);
 907                 return ret;
 908         }
 909
 910         return 0;
 911 }
 912
 913 PNAME(audio_wclk_common_p) = {
 914         "audio_99m",
 915         "audio_24m",
 916 };
 917
 918 PNAME(audio_timer_p) = {
 919         "audio_24m",
 920         "audio_32k",
 921 };
 922
 923 static struct zx_clk_mux audio_mux_clk[] = {
 924         MUX(I2S0_WCLK_MUX, "i2s0_wclk_mux", audio_wclk_common_p, AUDIO_I2S0_CLK, 0, 1),
 925         MUX(I2S1_WCLK_MUX, "i2s1_wclk_mux", audio_wclk_common_p, AUDIO_I2S1_CLK, 0, 1),
 926         MUX(I2S2_WCLK_MUX, "i2s2_wclk_mux", audio_wclk_common_p, AUDIO_I2S2_CLK, 0, 1),
 927         MUX(I2S3_WCLK_MUX, "i2s3_wclk_mux", audio_wclk_common_p, AUDIO_I2S3_CLK, 0, 1),
 928         MUX(0, "i2c0_wclk_mux", audio_wclk_common_p, AUDIO_I2C0_CLK, 0, 1),
 929         MUX(0, "spdif0_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF0_CLK, 0, 1),
 930         MUX(0, "spdif1_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF1_CLK, 0, 1),
 931         MUX(0, "timer_wclk_mux", audio_timer_p, AUDIO_TIMER_CLK, 0, 1),
 932 };
 933
 934 static struct clk_zx_audio_divider audio_adiv_clk[] = {
 935         AUDIO_DIV(0, "i2s0_wclk_div", "i2s0_wclk_mux", AUDIO_I2S0_DIV_CFG1),
 936         AUDIO_DIV(0, "i2s1_wclk_div", "i2s1_wclk_mux", AUDIO_I2S1_DIV_CFG1),
 937         AUDIO_DIV(0, "i2s2_wclk_div", "i2s2_wclk_mux", AUDIO_I2S2_DIV_CFG1),
 938         AUDIO_DIV(0, "i2s3_wclk_div", "i2s3_wclk_mux", AUDIO_I2S3_DIV_CFG1),
 939         AUDIO_DIV(0, "spdif0_wclk_div", "spdif0_wclk_mux", AUDIO_SPDIF0_DIV_CFG1),
 940         AUDIO_DIV(0, "spdif1_wclk_div", "spdif1_wclk_mux", AUDIO_SPDIF1_DIV_CFG1),
 941 };
 942
 943 static struct zx_clk_div audio_div_clk[] = {
 944         DIV_T(0, "tdm_wclk_div", "audio_16m384", AUDIO_TDM_CLK, 8, 4, 0, common_div_table),
 945 };
 946
 947 static struct zx_clk_gate audio_gate_clk[] = {
 948         GATE(AUDIO_I2S0_WCLK, "i2s0_wclk", "i2s0_wclk_div", AUDIO_I2S0_CLK, 9, CLK_SET_RATE_PARENT, 0),
 949         GATE(AUDIO_I2S1_WCLK, "i2s1_wclk", "i2s1_wclk_div", AUDIO_I2S1_CLK, 9, CLK_SET_RATE_PARENT, 0),
 950         GATE(AUDIO_I2S2_WCLK, "i2s2_wclk", "i2s2_wclk_div", AUDIO_I2S2_CLK, 9, CLK_SET_RATE_PARENT, 0),
 951         GATE(AUDIO_I2S3_WCLK, "i2s3_wclk", "i2s3_wclk_div", AUDIO_I2S3_CLK, 9, CLK_SET_RATE_PARENT, 0),
 952         GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
 953         GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
 954         GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
 955         GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
 956         GATE(AUDIO_I2C0_WCLK, "i2c0_wclk", "i2c0_wclk_mux", AUDIO_I2C0_CLK, 9, CLK_SET_RATE_PARENT, 0),
 957         GATE(AUDIO_SPDIF0_WCLK, "spdif0_wclk", "spdif0_wclk_div", AUDIO_SPDIF0_CLK, 9, CLK_SET_RATE_PARENT, 0),
 958         GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div", AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
 959         GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17, CLK_SET_RATE_PARENT, 0),
 960         GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0, 0),
 961 };
 962
 963 static struct clk_hw_onecell_data audio_hw_onecell_data = {
 964         .num = AUDIO_NR_CLKS,
 965         .hws = {
 966                 [AUDIO_NR_CLKS - 1] = NULL,
 967         },
 968 };
 969
 970 static int __init audio_clocks_init(struct device_node *np)
 971 {
 972         void __iomem *reg_base;
 973         int i, ret;
 974         const char *name;
 975
 976         reg_base = of_iomap(np, 0);
 977         if (!reg_base) {
 978                 pr_err("%s: Unable to map audio clk base\n", __func__);
 979                 return -ENXIO;
 980         }
 981
 982         for (i = 0; i < ARRAY_SIZE(audio_mux_clk); i++) {
 983                 if (audio_mux_clk[i].id)
 984                         audio_hw_onecell_data.hws[audio_mux_clk[i].id] =
 985                                         &audio_mux_clk[i].mux.hw;
 986
 987                 audio_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 988                 name = audio_mux_clk[i].mux.hw.init->name;
 989                 ret = clk_hw_register(NULL, &audio_mux_clk[i].mux.hw);
 990                 if (ret)
 991                         pr_warn("audio clk %s init error!\n", name);
 992         }
 993
 994         for (i = 0; i < ARRAY_SIZE(audio_adiv_clk); i++) {
 995                 if (audio_adiv_clk[i].id)
 996                         audio_hw_onecell_data.hws[audio_adiv_clk[i].id] =
 997                                         &audio_adiv_clk[i].hw;
 998
 999                 audio_adiv_clk[i].reg_base += (uintptr_t)reg_base;
1000                 name = audio_adiv_clk[i].hw.init->name;
1001                 ret = clk_hw_register(NULL, &audio_adiv_clk[i].hw);
1002                 if (ret)
1003                         pr_warn("audio clk %s init error!\n", name);
1004         }
1005
1006         for (i = 0; i < ARRAY_SIZE(audio_div_clk); i++) {
1007                 if (audio_div_clk[i].id)
1008                         audio_hw_onecell_data.hws[audio_div_clk[i].id] =
1009                                         &audio_div_clk[i].div.hw;
1010
1011                 audio_div_clk[i].div.reg += (uintptr_t)reg_base;
1012                 name = audio_div_clk[i].div.hw.init->name;
1013                 ret = clk_hw_register(NULL, &audio_div_clk[i].div.hw);
1014                 if (ret)
1015                         pr_warn("audio clk %s init error!\n", name);
1016         }
1017
1018         for (i = 0; i < ARRAY_SIZE(audio_gate_clk); i++) {
1019                 if (audio_gate_clk[i].id)
1020                         audio_hw_onecell_data.hws[audio_gate_clk[i].id] =
1021                                         &audio_gate_clk[i].gate.hw;
1022
1023                 audio_gate_clk[i].gate.reg += (uintptr_t)reg_base;
1024                 name = audio_gate_clk[i].gate.hw.init->name;
1025                 ret = clk_hw_register(NULL, &audio_gate_clk[i].gate.hw);
1026                 if (ret)
1027                         pr_warn("audio clk %s init error!\n", name);
1028         }
1029
1030         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
1031                                      &audio_hw_onecell_data);
1032         if (ret) {
1033                 pr_err("failed to register audio clk provider: %d\n", ret);
1034                 return ret;
1035         }
1036
1037         return 0;
1038 }
1039
1040 static const struct of_device_id zx_clkc_match_table[] = {
1041         { .compatible = "zte,zx296718-topcrm", .data = &top_clocks_init },
1042         { .compatible = "zte,zx296718-lsp0crm", .data = &lsp0_clocks_init },
1043         { .compatible = "zte,zx296718-lsp1crm", .data = &lsp1_clocks_init },
1044         { .compatible = "zte,zx296718-audiocrm", .data = &audio_clocks_init },
1045         { }
1046 };
1047
1048 static int zx_clkc_probe(struct platform_device *pdev)
1049 {
1050         int (*init_fn)(struct device_node *np);
1051         struct device_node *np = pdev->dev.of_node;
1052
1053         init_fn = of_device_get_match_data(&pdev->dev);
1054         if (!init_fn) {
1055                 dev_err(&pdev->dev, "Error: No device match found\n");
1056                 return -ENODEV;
1057         }
1058
1059         return init_fn(np);
1060 }
1061
1062 static struct platform_driver zx_clk_driver = {
1063         .probe          = zx_clkc_probe,
1064         .driver         = {
1065                 .name   = "zx296718-clkc",
1066                 .of_match_table = zx_clkc_match_table,
1067         },
1068 };
1069
1070 static int __init zx_clk_init(void)
1071 {
1072         return platform_driver_register(&zx_clk_driver);
1073 }
1074 core_initcall(zx_clk_init);