1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright(c) 2020 Intel Corporation.
4 * Zhu YiXin <yixin.zhu@intel.com>
5 * Rahul Tanwar <rahul.tanwar@intel.com>
15 void __iomem *membase;
23 struct lgm_clk_divider {
25 void __iomem *membase;
32 const struct clk_div_table *table;
38 void __iomem *membase;
56 void __iomem *membase;
67 CLK_TYPE_FIXED_FACTOR,
73 * struct lgm_clk_provider
74 * @membase: IO mem base address for CGU.
77 * @clk_data: array of hw clocks and clk number.
79 struct lgm_clk_provider {
80 void __iomem *membase;
81 struct device_node *np;
83 struct clk_hw_onecell_data clk_data;
95 void __iomem *membase;
103 * struct lgm_pll_clk_data
104 * @id: platform specific id of the clock.
105 * @name: name of this pll clock.
106 * @parent_data: parent clock data.
107 * @num_parents: number of parents.
108 * @flags: optional flags for basic clock.
109 * @type: platform type of pll.
110 * @reg: offset of the register.
112 struct lgm_pll_clk_data {
115 const struct clk_parent_data *parent_data;
122 #define LGM_PLL(_id, _name, _pdata, _flags, \
127 .parent_data = _pdata, \
128 .num_parents = ARRAY_SIZE(_pdata), \
134 struct lgm_clk_ddiv_data {
137 const struct clk_parent_data *parent_data;
139 unsigned long div_flags;
151 #define LGM_DDIV(_id, _name, _pname, _flags, _reg, \
152 _shft0, _wdth0, _shft1, _wdth1, \
153 _shft_gate, _wdth_gate, _xshft, _df) \
157 .parent_data = &(const struct clk_parent_data){ \
167 .shift_gate = _shft_gate, \
168 .width_gate = _wdth_gate, \
169 .ex_shift = _xshft, \
174 struct lgm_clk_branch {
176 enum lgm_clk_type type;
178 const struct clk_parent_data *parent_data;
181 unsigned int mux_off;
184 unsigned long mux_flags;
185 unsigned int mux_val;
186 unsigned int div_off;
191 unsigned long div_flags;
192 unsigned int div_val;
193 const struct clk_div_table *div_table;
194 unsigned int gate_off;
196 unsigned long gate_flags;
197 unsigned int gate_val;
202 /* clock flags definition */
203 #define CLOCK_FLAG_VAL_INIT BIT(16)
204 #define MUX_CLK_SW BIT(17)
206 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \
207 _shift, _width, _cf, _v) \
210 .type = CLK_TYPE_MUX, \
212 .parent_data = _pdata, \
213 .num_parents = ARRAY_SIZE(_pdata), \
216 .mux_shift = _shift, \
217 .mux_width = _width, \
222 #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \
223 _shift_gate, _width_gate, _cf, _v, _dtable) \
226 .type = CLK_TYPE_DIVIDER, \
228 .parent_data = &(const struct clk_parent_data){ \
235 .div_shift = _shift, \
236 .div_width = _width, \
237 .div_shift_gate = _shift_gate, \
238 .div_width_gate = _width_gate, \
241 .div_table = _dtable, \
244 #define LGM_GATE(_id, _name, _pname, _f, _reg, \
248 .type = CLK_TYPE_GATE, \
250 .parent_data = &(const struct clk_parent_data){ \
254 .num_parents = !_pname ? 0 : 1, \
257 .gate_shift = _shift, \
262 #define LGM_FIXED(_id, _name, _pname, _f, _reg, \
263 _shift, _width, _cf, _freq, _v) \
266 .type = CLK_TYPE_FIXED, \
268 .parent_data = &(const struct clk_parent_data){ \
272 .num_parents = !_pname ? 0 : 1, \
275 .div_shift = _shift, \
276 .div_width = _width, \
279 .mux_flags = _freq, \
282 #define LGM_FIXED_FACTOR(_id, _name, _pname, _f, _reg, \
283 _shift, _width, _cf, _v, _m, _d) \
286 .type = CLK_TYPE_FIXED_FACTOR, \
288 .parent_data = &(const struct clk_parent_data){ \
295 .div_shift = _shift, \
296 .div_width = _width, \
303 static inline void lgm_set_clk_val(void __iomem *membase, u32 reg,
304 u8 shift, u8 width, u32 set_val)
306 u32 mask = (GENMASK(width - 1, 0) << shift);
309 regval = readl(membase + reg);
310 regval = (regval & ~mask) | ((set_val << shift) & mask);
311 writel(regval, membase + reg);
314 static inline u32 lgm_get_clk_val(void __iomem *membase, u32 reg,
317 u32 mask = (GENMASK(width - 1, 0) << shift);
320 val = readl(membase + reg);
321 val = (val & mask) >> shift;
326 int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
327 const struct lgm_clk_branch *list,
328 unsigned int nr_clk);
329 int lgm_clk_register_plls(struct lgm_clk_provider *ctx,
330 const struct lgm_pll_clk_data *list,
331 unsigned int nr_clk);
332 int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
333 const struct lgm_clk_ddiv_data *list,
334 unsigned int nr_clk);
335 #endif /* __CLK_CGU_H */