1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the ICST307 VCO clock found in the ARM Reference designs.
4 * We wrap the custom interface from <asm/hardware/icst.h> into the generic
7 * Copyright (C) 2012-2015 Linus Walleij
9 * TODO: when all ARM reference designs are migrated to generic clocks, the
10 * ICST clock code from the ARM tree should probably be merged into this
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/err.h>
17 #include <linux/clk-provider.h>
19 #include <linux/regmap.h>
20 #include <linux/mfd/syscon.h>
25 /* Magic unlocking token used on all Versatile boards */
26 #define VERSATILE_LOCK_VAL 0xA05F
28 #define VERSATILE_AUX_OSC_BITS 0x7FFFF
29 #define INTEGRATOR_AP_CM_BITS 0xFF
30 #define INTEGRATOR_AP_SYS_BITS 0xFF
31 #define INTEGRATOR_CP_CM_CORE_BITS 0x7FF
32 #define INTEGRATOR_CP_CM_MEM_BITS 0x7FF000
34 #define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8)
37 * struct clk_icst - ICST VCO clock wrapper
38 * @hw: corresponding clock hardware entry
39 * @vcoreg: VCO register address
40 * @lockreg: VCO lock register address
41 * @params: parameters for this ICST instance
43 * @ctype: the type of control register for the ICST
50 struct icst_params *params;
52 enum icst_control_type ctype;
55 #define to_icst(_hw) container_of(_hw, struct clk_icst, hw)
58 * vco_get() - get ICST VCO settings from a certain ICST
59 * @icst: the ICST clock to get
60 * @vco: the VCO struct to return the value in
62 static int vco_get(struct clk_icst *icst, struct icst_vco *vco)
67 ret = regmap_read(icst->map, icst->vcoreg_off, &val);
72 * The Integrator/AP core clock can only access the low eight
73 * bits of the v PLL divider. Bit 8 is tied low and always zero,
74 * r is hardwired to 22 and output divider s is hardwired to 1
75 * (divide by 2) according to the document
76 * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and
77 * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14.
79 if (icst->ctype == ICST_INTEGRATOR_AP_CM) {
80 vco->v = val & INTEGRATOR_AP_CM_BITS;
87 * The Integrator/AP system clock on the base board can only
88 * access the low eight bits of the v PLL divider. Bit 8 is tied low
89 * and always zero, r is hardwired to 46, and the output divider is
90 * hardwired to 3 (divide by 4) according to the document
91 * "Integrator AP ASIC Development Motherboard" ARM DUI 0098B,
94 if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
95 vco->v = val & INTEGRATOR_AP_SYS_BITS;
102 * The Integrator/AP PCI clock is using an odd pattern to create
103 * the child clock, basically a single bit called DIVX/Y is used
104 * to select between two different hardwired values: setting the
105 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the
106 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies
107 * 33 or 25 MHz respectively.
109 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
110 bool divxy = !!(val & INTEGRATOR_AP_PCI_25_33_MHZ);
112 vco->v = divxy ? 17 : 14;
113 vco->r = divxy ? 22 : 14;
119 * The Integrator/CP core clock can access the low eight bits
120 * of the v PLL divider. Bit 8 is tied low and always zero,
121 * r is hardwired to 22 and the output divider s is accessible
122 * in bits 8 thru 10 according to the document
123 * "Integrator/CM940T, CM920T, CM740T, and CM720T User Guide"
124 * ARM DUI 0157A, page 3-20 thru 3-23 and 4-10.
126 if (icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
129 vco->s = (val >> 8) & 7;
133 if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
134 vco->v = (val >> 12) & 0xFF;
136 vco->s = (val >> 20) & 7;
140 vco->v = val & 0x1ff;
141 vco->r = (val >> 9) & 0x7f;
142 vco->s = (val >> 16) & 03;
147 * vco_set() - commit changes to an ICST VCO
148 * @icst: the ICST clock to set
149 * @vco: the VCO struct to set the changes from
151 static int vco_set(struct clk_icst *icst, struct icst_vco vco)
157 /* Mask the bits used by the VCO */
158 switch (icst->ctype) {
159 case ICST_INTEGRATOR_AP_CM:
160 mask = INTEGRATOR_AP_CM_BITS;
163 pr_err("ICST error: tried to set bit 8 of VDW\n");
165 pr_err("ICST error: tried to use VOD != 1\n");
167 pr_err("ICST error: tried to use RDW != 22\n");
169 case ICST_INTEGRATOR_AP_SYS:
170 mask = INTEGRATOR_AP_SYS_BITS;
173 pr_err("ICST error: tried to set bit 8 of VDW\n");
175 pr_err("ICST error: tried to use VOD != 1\n");
177 pr_err("ICST error: tried to use RDW != 22\n");
179 case ICST_INTEGRATOR_CP_CM_CORE:
180 mask = INTEGRATOR_CP_CM_CORE_BITS; /* Uses 12 bits */
181 val = (vco.v & 0xFF) | vco.s << 8;
183 pr_err("ICST error: tried to set bit 8 of VDW\n");
185 pr_err("ICST error: tried to use RDW != 22\n");
187 case ICST_INTEGRATOR_CP_CM_MEM:
188 mask = INTEGRATOR_CP_CM_MEM_BITS; /* Uses 12 bits */
189 val = ((vco.v & 0xFF) << 12) | (vco.s << 20);
191 pr_err("ICST error: tried to set bit 8 of VDW\n");
193 pr_err("ICST error: tried to use RDW != 22\n");
196 /* Regular auxilary oscillator */
197 mask = VERSATILE_AUX_OSC_BITS;
198 val = vco.v | (vco.r << 9) | (vco.s << 16);
202 pr_debug("ICST: new val = 0x%08x\n", val);
204 /* This magic unlocks the VCO so it can be controlled */
205 ret = regmap_write(icst->map, icst->lockreg_off, VERSATILE_LOCK_VAL);
208 ret = regmap_update_bits(icst->map, icst->vcoreg_off, mask, val);
211 /* This locks the VCO again */
212 ret = regmap_write(icst->map, icst->lockreg_off, 0);
218 static unsigned long icst_recalc_rate(struct clk_hw *hw,
219 unsigned long parent_rate)
221 struct clk_icst *icst = to_icst(hw);
226 icst->params->ref = parent_rate;
227 ret = vco_get(icst, &vco);
229 pr_err("ICST: could not get VCO setting\n");
232 icst->rate = icst_hz(icst->params, vco);
236 static long icst_round_rate(struct clk_hw *hw, unsigned long rate,
237 unsigned long *prate)
239 struct clk_icst *icst = to_icst(hw);
242 if (icst->ctype == ICST_INTEGRATOR_AP_CM ||
243 icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
244 if (rate <= 12000000)
246 if (rate >= 160000000)
248 /* Slam to closest megahertz */
249 return DIV_ROUND_CLOSEST(rate, 1000000) * 1000000;
252 if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
255 if (rate >= 66000000)
257 /* Slam to closest 0.5 megahertz */
258 return DIV_ROUND_CLOSEST(rate, 500000) * 500000;
261 if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
262 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */
265 if (rate >= 50000000)
267 /* Slam to closest 0.25 MHz */
268 return DIV_ROUND_CLOSEST(rate, 250000) * 250000;
271 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
273 * If we're below or less than halfway from 25 to 33 MHz
276 if (rate <= 25000000 || rate < 29000000)
278 /* Else just return the default frequency */
282 vco = icst_hz_to_vco(icst->params, rate);
283 return icst_hz(icst->params, vco);
286 static int icst_set_rate(struct clk_hw *hw, unsigned long rate,
287 unsigned long parent_rate)
289 struct clk_icst *icst = to_icst(hw);
292 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
293 /* This clock is especially primitive */
297 if (rate == 25000000) {
299 } else if (rate == 33000000) {
300 val = INTEGRATOR_AP_PCI_25_33_MHZ;
302 pr_err("ICST: cannot set PCI frequency %lu\n",
306 ret = regmap_write(icst->map, icst->lockreg_off,
310 ret = regmap_update_bits(icst->map, icst->vcoreg_off,
311 INTEGRATOR_AP_PCI_25_33_MHZ,
315 /* This locks the VCO again */
316 ret = regmap_write(icst->map, icst->lockreg_off, 0);
323 icst->params->ref = parent_rate;
324 vco = icst_hz_to_vco(icst->params, rate);
325 icst->rate = icst_hz(icst->params, vco);
326 return vco_set(icst, vco);
329 static const struct clk_ops icst_ops = {
330 .recalc_rate = icst_recalc_rate,
331 .round_rate = icst_round_rate,
332 .set_rate = icst_set_rate,
335 struct clk *icst_clk_setup(struct device *dev,
336 const struct clk_icst_desc *desc,
338 const char *parent_name,
340 enum icst_control_type ctype)
343 struct clk_icst *icst;
344 struct clk_init_data init;
345 struct icst_params *pclone;
347 icst = kzalloc(sizeof(*icst), GFP_KERNEL);
349 return ERR_PTR(-ENOMEM);
351 pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL);
354 return ERR_PTR(-ENOMEM);
358 init.ops = &icst_ops;
360 init.parent_names = (parent_name ? &parent_name : NULL);
361 init.num_parents = (parent_name ? 1 : 0);
363 icst->hw.init = &init;
364 icst->params = pclone;
365 icst->vcoreg_off = desc->vco_offset;
366 icst->lockreg_off = desc->lock_offset;
369 clk = clk_register(dev, &icst->hw);
377 EXPORT_SYMBOL_GPL(icst_clk_setup);
379 struct clk *icst_clk_register(struct device *dev,
380 const struct clk_icst_desc *desc,
382 const char *parent_name,
385 struct regmap_config icst_regmap_conf = {
392 map = regmap_init_mmio(dev, base, &icst_regmap_conf);
394 pr_err("could not initialize ICST regmap\n");
395 return ERR_CAST(map);
397 return icst_clk_setup(dev, desc, name, parent_name, map,
400 EXPORT_SYMBOL_GPL(icst_clk_register);
404 * In a device tree, an memory-mapped ICST clock appear as a child
405 * of a syscon node. Assume this and probe it only as a child of a
409 static const struct icst_params icst525_params = {
410 .vco_max = ICST525_VCO_MAX_5V,
411 .vco_min = ICST525_VCO_MIN,
416 .s2div = icst525_s2div,
417 .idx2s = icst525_idx2s,
420 static const struct icst_params icst307_params = {
421 .vco_max = ICST307_VCO_MAX,
422 .vco_min = ICST307_VCO_MIN,
427 .s2div = icst307_s2div,
428 .idx2s = icst307_idx2s,
432 * The core modules on the Integrator/AP and Integrator/CP have
433 * especially crippled ICST525 control.
435 static const struct icst_params icst525_apcp_cm_params = {
436 .vco_max = ICST525_VCO_MAX_5V,
437 .vco_min = ICST525_VCO_MIN,
438 /* Minimum 12 MHz, VDW = 4 */
441 * Maximum 160 MHz, VDW = 152 for all core modules, but
442 * CM926EJ-S, CM1026EJ-S and CM1136JF-S can actually
443 * go to 200 MHz (max VDW = 192).
446 /* r is hardcoded to 22 and this is the actual divisor, +2 */
449 .s2div = icst525_s2div,
450 .idx2s = icst525_idx2s,
453 static const struct icst_params icst525_ap_sys_params = {
454 .vco_max = ICST525_VCO_MAX_5V,
455 .vco_min = ICST525_VCO_MIN,
456 /* Minimum 3 MHz, VDW = 4 */
458 /* Maximum 50 MHz, VDW = 192 */
460 /* r is hardcoded to 46 and this is the actual divisor, +2 */
463 .s2div = icst525_s2div,
464 .idx2s = icst525_idx2s,
467 static const struct icst_params icst525_ap_pci_params = {
468 .vco_max = ICST525_VCO_MAX_5V,
469 .vco_min = ICST525_VCO_MIN,
474 /* r is hardcoded to 14 or 22 and this is the actual divisors +2 */
477 .s2div = icst525_s2div,
478 .idx2s = icst525_idx2s,
481 static void __init of_syscon_icst_setup(struct device_node *np)
483 struct device_node *parent;
485 struct clk_icst_desc icst_desc;
486 const char *name = np->name;
487 const char *parent_name;
489 enum icst_control_type ctype;
491 /* We do not release this reference, we are using it perpetually */
492 parent = of_get_parent(np);
494 pr_err("no parent node for syscon ICST clock\n");
497 map = syscon_node_to_regmap(parent);
499 pr_err("no regmap for syscon ICST clock parent\n");
503 if (of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) {
504 pr_err("no VCO register offset for ICST clock\n");
507 if (of_property_read_u32(np, "lock-offset", &icst_desc.lock_offset)) {
508 pr_err("no lock register offset for ICST clock\n");
512 if (of_device_is_compatible(np, "arm,syscon-icst525")) {
513 icst_desc.params = &icst525_params;
514 ctype = ICST_VERSATILE;
515 } else if (of_device_is_compatible(np, "arm,syscon-icst307")) {
516 icst_desc.params = &icst307_params;
517 ctype = ICST_VERSATILE;
518 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-cm")) {
519 icst_desc.params = &icst525_apcp_cm_params;
520 ctype = ICST_INTEGRATOR_AP_CM;
521 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-sys")) {
522 icst_desc.params = &icst525_ap_sys_params;
523 ctype = ICST_INTEGRATOR_AP_SYS;
524 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-pci")) {
525 icst_desc.params = &icst525_ap_pci_params;
526 ctype = ICST_INTEGRATOR_AP_PCI;
527 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-core")) {
528 icst_desc.params = &icst525_apcp_cm_params;
529 ctype = ICST_INTEGRATOR_CP_CM_CORE;
530 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-mem")) {
531 icst_desc.params = &icst525_apcp_cm_params;
532 ctype = ICST_INTEGRATOR_CP_CM_MEM;
534 pr_err("unknown ICST clock %s\n", name);
538 /* Parent clock name is not the same as node parent */
539 parent_name = of_clk_get_parent_name(np, 0);
541 regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype);
542 if (IS_ERR(regclk)) {
543 pr_err("error setting up syscon ICST clock %s\n", name);
546 of_clk_add_provider(np, of_clk_src_simple_get, regclk);
547 pr_debug("registered syscon ICST clock %s\n", name);
550 CLK_OF_DECLARE(arm_syscon_icst525_clk,
551 "arm,syscon-icst525", of_syscon_icst_setup);
552 CLK_OF_DECLARE(arm_syscon_icst307_clk,
553 "arm,syscon-icst307", of_syscon_icst_setup);
554 CLK_OF_DECLARE(arm_syscon_integratorap_cm_clk,
555 "arm,syscon-icst525-integratorap-cm", of_syscon_icst_setup);
556 CLK_OF_DECLARE(arm_syscon_integratorap_sys_clk,
557 "arm,syscon-icst525-integratorap-sys", of_syscon_icst_setup);
558 CLK_OF_DECLARE(arm_syscon_integratorap_pci_clk,
559 "arm,syscon-icst525-integratorap-pci", of_syscon_icst_setup);
560 CLK_OF_DECLARE(arm_syscon_integratorcp_cm_core_clk,
561 "arm,syscon-icst525-integratorcp-cm-core", of_syscon_icst_setup);
562 CLK_OF_DECLARE(arm_syscon_integratorcp_cm_mem_clk,
563 "arm,syscon-icst525-integratorcp-cm-mem", of_syscon_icst_setup);