4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
31 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
32 int num_parents = clk_hw_get_num_parents(hw);
36 * FIXME need a mux-specific flag to determine if val is bitwise or
37 * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
38 * from 0x1 to 0x7 (index starts at one)
39 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
40 * val = 0x4 really means "bit 2, index starts at bit 0"
42 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift;
48 for (i = 0; i < num_parents; i++)
49 if (mux->table[i] == val)
54 if (val && (mux->flags & CLK_MUX_INDEX_BIT))
57 if (val && (mux->flags & CLK_MUX_INDEX_ONE))
60 if (val >= num_parents)
66 static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
68 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
72 index = mux->table[index];
74 if (mux->flags & CLK_MUX_INDEX_BIT)
75 index = (1 << ffs(index));
77 if (mux->flags & CLK_MUX_INDEX_ONE)
81 if (mux->flags & CLK_MUX_HIWORD_MASK) {
82 val = mux->mask << (mux->shift + 16);
84 val = ti_clk_ll_ops->clk_readl(&mux->reg);
85 val &= ~(mux->mask << mux->shift);
87 val |= index << mux->shift;
88 ti_clk_ll_ops->clk_writel(val, &mux->reg);
89 ti_clk_latch(&mux->reg, mux->latch);
95 * clk_mux_save_context - Save the parent selcted in the mux
96 * @hw: pointer struct clk_hw
98 * Save the parent mux value.
100 static int clk_mux_save_context(struct clk_hw *hw)
102 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
104 mux->saved_parent = ti_clk_mux_get_parent(hw);
109 * clk_mux_restore_context - Restore the parent in the mux
110 * @hw: pointer struct clk_hw
112 * Restore the saved parent mux value.
114 static void clk_mux_restore_context(struct clk_hw *hw)
116 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
118 ti_clk_mux_set_parent(hw, mux->saved_parent);
121 const struct clk_ops ti_clk_mux_ops = {
122 .get_parent = ti_clk_mux_get_parent,
123 .set_parent = ti_clk_mux_set_parent,
124 .determine_rate = __clk_mux_determine_rate,
125 .save_context = clk_mux_save_context,
126 .restore_context = clk_mux_restore_context,
129 static struct clk *_register_mux(struct device_node *node, const char *name,
130 const char * const *parent_names,
131 u8 num_parents, unsigned long flags,
132 struct clk_omap_reg *reg, u8 shift, u32 mask,
133 s8 latch, u8 clk_mux_flags, u32 *table)
135 struct clk_omap_mux *mux;
137 struct clk_init_data init;
139 /* allocate the mux */
140 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
142 return ERR_PTR(-ENOMEM);
145 init.ops = &ti_clk_mux_ops;
147 init.parent_names = parent_names;
148 init.num_parents = num_parents;
150 /* struct clk_mux assignments */
151 memcpy(&mux->reg, reg, sizeof(*reg));
155 mux->flags = clk_mux_flags;
157 mux->hw.init = &init;
159 clk = of_ti_clk_register(node, &mux->hw, name);
168 * of_mux_clk_setup - Setup function for simple mux rate clock
169 * @node: DT node for the clock
171 * Sets up a basic clock multiplexer.
173 static void of_mux_clk_setup(struct device_node *node)
176 struct clk_omap_reg reg;
177 unsigned int num_parents;
178 const char **parent_names;
180 u8 clk_mux_flags = 0;
184 u32 flags = CLK_SET_RATE_NO_REPARENT;
186 num_parents = of_clk_get_parent_count(node);
187 if (num_parents < 2) {
188 pr_err("mux-clock %pOFn must have parents\n", node);
191 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
195 of_clk_parent_fill(node, parent_names, num_parents);
197 if (ti_clk_get_reg_addr(node, 0, ®))
200 of_property_read_u32(node, "ti,bit-shift", &shift);
202 of_property_read_u32(node, "ti,latch-bit", &latch);
204 if (of_property_read_bool(node, "ti,index-starts-at-one"))
205 clk_mux_flags |= CLK_MUX_INDEX_ONE;
207 if (of_property_read_bool(node, "ti,set-rate-parent"))
208 flags |= CLK_SET_RATE_PARENT;
210 /* Generate bit-mask based on parent info */
212 if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
215 mask = (1 << fls(mask)) - 1;
217 name = ti_dt_clk_name(node);
218 clk = _register_mux(node, name, parent_names, num_parents,
219 flags, ®, shift, mask, latch, clk_mux_flags,
223 of_clk_add_provider(node, of_clk_src_simple_get, clk);
228 CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
230 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
232 struct clk_omap_mux *mux;
238 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
240 return ERR_PTR(-ENOMEM);
242 mux->shift = setup->bit_shift;
243 mux->latch = -EINVAL;
245 mux->reg.index = setup->module;
246 mux->reg.offset = setup->reg;
248 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
249 mux->flags |= CLK_MUX_INDEX_ONE;
251 num_parents = setup->num_parents;
253 mux->mask = num_parents - 1;
254 mux->mask = (1 << fls(mux->mask)) - 1;
259 static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
261 struct clk_omap_mux *mux;
262 unsigned int num_parents;
265 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
269 if (ti_clk_get_reg_addr(node, 0, &mux->reg))
272 if (!of_property_read_u32(node, "ti,bit-shift", &val))
275 if (of_property_read_bool(node, "ti,index-starts-at-one"))
276 mux->flags |= CLK_MUX_INDEX_ONE;
278 num_parents = of_clk_get_parent_count(node);
280 if (num_parents < 2) {
281 pr_err("%pOFn must have parents\n", node);
285 mux->mask = num_parents - 1;
286 mux->mask = (1 << fls(mux->mask)) - 1;
288 if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
294 CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
295 of_ti_composite_mux_clk_setup);