2 * OMAP gate clock support
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
28 #define pr_fmt(fmt) "%s: " fmt, __func__
30 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
32 static const struct clk_ops omap_gate_clkdm_clk_ops = {
33 .init = &omap2_init_clk_clkdm,
34 .enable = &omap2_clkops_enable_clkdm,
35 .disable = &omap2_clkops_disable_clkdm,
38 const struct clk_ops omap_gate_clk_ops = {
39 .init = &omap2_init_clk_clkdm,
40 .enable = &omap2_dflt_clk_enable,
41 .disable = &omap2_dflt_clk_disable,
42 .is_enabled = &omap2_dflt_clk_is_enabled,
45 static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
46 .init = &omap2_init_clk_clkdm,
47 .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
48 .disable = &omap2_dflt_clk_disable,
49 .is_enabled = &omap2_dflt_clk_is_enabled,
53 * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
54 * from HSDivider PWRDN problem Implements Errata ID: i556.
55 * @clk: DPLL output struct clk
57 * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
58 * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
59 * valueafter their respective PWRDN bits are set. Any dummy write
60 * (Any other value different from the Read value) to the
61 * corresponding CM_CLKSEL register will refresh the dividers.
63 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
65 struct clk_omap_divider *parent;
66 struct clk_hw *parent_hw;
70 /* Clear PWRDN bit of HSDIVIDER */
71 ret = omap2_dflt_clk_enable(hw);
73 /* Parent is the x2 node, get parent of parent for the m2 div */
74 parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw));
75 parent = to_clk_omap_divider(parent_hw);
77 /* Restore the dividers */
79 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg);
82 /* Write any other value different from the Read value */
83 dummy_v ^= (1 << parent->shift);
84 ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg);
86 /* Write the original divider */
87 ti_clk_ll_ops->clk_writel(orig_v, &parent->reg);
93 static struct clk *_register_gate(struct device *dev, const char *name,
94 const char *parent_name, unsigned long flags,
95 struct clk_omap_reg *reg, u8 bit_idx,
96 u8 clk_gate_flags, const struct clk_ops *ops,
97 const struct clk_hw_omap_ops *hw_ops)
99 struct clk_init_data init = { NULL };
100 struct clk_hw_omap *clk_hw;
103 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
105 return ERR_PTR(-ENOMEM);
107 clk_hw->hw.init = &init;
112 memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
113 clk_hw->enable_bit = bit_idx;
114 clk_hw->ops = hw_ops;
116 clk_hw->flags = clk_gate_flags;
118 init.parent_names = &parent_name;
119 init.num_parents = 1;
123 clk = ti_clk_register(NULL, &clk_hw->hw, name);
131 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
132 struct clk *ti_clk_register_gate(struct ti_clk *setup)
134 const struct clk_ops *ops = &omap_gate_clk_ops;
135 const struct clk_hw_omap_ops *hw_ops = NULL;
136 struct clk_omap_reg reg;
138 u8 clk_gate_flags = 0;
139 struct ti_clk_gate *gate;
143 if (gate->flags & CLKF_INTERFACE)
144 return ti_clk_register_interface(setup);
146 if (gate->flags & CLKF_SET_RATE_PARENT)
147 flags |= CLK_SET_RATE_PARENT;
149 if (gate->flags & CLKF_SET_BIT_TO_DISABLE)
150 clk_gate_flags |= INVERT_ENABLE;
152 if (gate->flags & CLKF_HSDIV) {
153 ops = &omap_gate_clk_hsdiv_restore_ops;
154 hw_ops = &clkhwops_wait;
157 if (gate->flags & CLKF_DSS)
158 hw_ops = &clkhwops_omap3430es2_dss_usbhost_wait;
160 if (gate->flags & CLKF_WAIT)
161 hw_ops = &clkhwops_wait;
163 if (gate->flags & CLKF_CLKDM)
164 ops = &omap_gate_clkdm_clk_ops;
166 if (gate->flags & CLKF_AM35XX)
167 hw_ops = &clkhwops_am35xx_ipss_module_wait;
169 reg.index = gate->module;
170 reg.offset = gate->reg;
173 return _register_gate(NULL, setup->name, gate->parent, flags,
174 ®, gate->bit_shift,
175 clk_gate_flags, ops, hw_ops);
178 struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
180 struct clk_hw_omap *gate;
181 struct clk_omap_reg *reg;
182 const struct clk_hw_omap_ops *ops = &clkhwops_wait;
187 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
189 return ERR_PTR(-ENOMEM);
191 reg = (struct clk_omap_reg *)&gate->enable_reg;
192 reg->index = setup->module;
193 reg->offset = setup->reg;
195 gate->enable_bit = setup->bit_shift;
197 if (setup->flags & CLKF_NO_WAIT)
200 if (setup->flags & CLKF_INTERFACE)
201 ops = &clkhwops_iclk_wait;
209 static void __init _of_ti_gate_clk_setup(struct device_node *node,
210 const struct clk_ops *ops,
211 const struct clk_hw_omap_ops *hw_ops)
214 const char *parent_name;
215 struct clk_omap_reg reg;
219 u8 clk_gate_flags = 0;
221 if (ops != &omap_gate_clkdm_clk_ops) {
222 if (ti_clk_get_reg_addr(node, 0, ®))
225 if (!of_property_read_u32(node, "ti,bit-shift", &val))
229 if (of_clk_get_parent_count(node) != 1) {
230 pr_err("%s must have 1 parent\n", node->name);
234 parent_name = of_clk_get_parent_name(node, 0);
236 if (of_property_read_bool(node, "ti,set-rate-parent"))
237 flags |= CLK_SET_RATE_PARENT;
239 if (of_property_read_bool(node, "ti,set-bit-to-disable"))
240 clk_gate_flags |= INVERT_ENABLE;
242 clk = _register_gate(NULL, node->name, parent_name, flags, ®,
243 enable_bit, clk_gate_flags, ops, hw_ops);
246 of_clk_add_provider(node, of_clk_src_simple_get, clk);
250 _of_ti_composite_gate_clk_setup(struct device_node *node,
251 const struct clk_hw_omap_ops *hw_ops)
253 struct clk_hw_omap *gate;
256 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
260 if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg))
263 of_property_read_u32(node, "ti,bit-shift", &val);
265 gate->enable_bit = val;
268 if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
276 of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
278 _of_ti_composite_gate_clk_setup(node, NULL);
280 CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
281 of_ti_composite_no_wait_gate_clk_setup);
283 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
284 static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
286 _of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
288 CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
289 of_ti_composite_interface_clk_setup);
292 static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
294 _of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
296 CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
297 of_ti_composite_gate_clk_setup);
300 static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
302 _of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
304 CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
305 of_ti_clkdm_gate_clk_setup);
307 static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
309 _of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
312 CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
313 of_ti_hsdiv_gate_clk_setup);
315 static void __init of_ti_gate_clk_setup(struct device_node *node)
317 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
319 CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);
321 static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
323 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
325 CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
326 of_ti_wait_gate_clk_setup);
328 #ifdef CONFIG_ARCH_OMAP3
329 static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
331 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
332 &clkhwops_am35xx_ipss_module_wait);
334 CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
335 of_ti_am35xx_gate_clk_setup);
337 static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
339 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
340 &clkhwops_omap3430es2_dss_usbhost_wait);
342 CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
343 of_ti_dss_gate_clk_setup);