1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
5 #include <linux/delay.h>
8 #include <linux/math64.h>
10 #include <linux/of_address.h>
11 #include <linux/clk/ti.h>
15 /* FAPLL Control Register PLL_CTRL */
16 #define FAPLL_MAIN_MULT_N_SHIFT 16
17 #define FAPLL_MAIN_DIV_P_SHIFT 8
18 #define FAPLL_MAIN_LOCK BIT(7)
19 #define FAPLL_MAIN_PLLEN BIT(3)
20 #define FAPLL_MAIN_BP BIT(2)
21 #define FAPLL_MAIN_LOC_CTL BIT(0)
23 #define FAPLL_MAIN_MAX_MULT_N 0xffff
24 #define FAPLL_MAIN_MAX_DIV_P 0xff
25 #define FAPLL_MAIN_CLEAR_MASK \
26 ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \
27 (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \
30 /* FAPLL powerdown register PWD */
31 #define FAPLL_PWD_OFFSET 4
33 #define MAX_FAPLL_OUTPUTS 7
34 #define FAPLL_MAX_RETRIES 1000
36 #define to_fapll(_hw) container_of(_hw, struct fapll_data, hw)
37 #define to_synth(_hw) container_of(_hw, struct fapll_synth, hw)
39 /* The bypass bit is inverted on the ddr_pll.. */
40 #define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440)
43 * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
44 * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output.
46 #define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c)
47 #define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8)
49 /* Synthesizer divider register */
50 #define SYNTH_LDMDIV1 BIT(8)
52 /* Synthesizer frequency register */
53 #define SYNTH_LDFREQ BIT(31)
55 #define SYNTH_PHASE_K 8
56 #define SYNTH_MAX_INT_DIV 0xf
57 #define SYNTH_MAX_DIV_M 0xff
64 struct clk *clk_bypass;
65 struct clk_onecell_data outputs;
66 bool bypass_bit_inverted;
71 struct fapll_data *fd;
79 static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
81 u32 v = readl_relaxed(fd->base);
83 if (fd->bypass_bit_inverted)
84 return !(v & FAPLL_MAIN_BP);
86 return !!(v & FAPLL_MAIN_BP);
89 static void ti_fapll_set_bypass(struct fapll_data *fd)
91 u32 v = readl_relaxed(fd->base);
93 if (fd->bypass_bit_inverted)
97 writel_relaxed(v, fd->base);
100 static void ti_fapll_clear_bypass(struct fapll_data *fd)
102 u32 v = readl_relaxed(fd->base);
104 if (fd->bypass_bit_inverted)
108 writel_relaxed(v, fd->base);
111 static int ti_fapll_wait_lock(struct fapll_data *fd)
113 int retries = FAPLL_MAX_RETRIES;
116 while ((v = readl_relaxed(fd->base))) {
117 if (v & FAPLL_MAIN_LOCK)
126 pr_err("%s failed to lock\n", fd->name);
131 static int ti_fapll_enable(struct clk_hw *hw)
133 struct fapll_data *fd = to_fapll(hw);
134 u32 v = readl_relaxed(fd->base);
136 v |= FAPLL_MAIN_PLLEN;
137 writel_relaxed(v, fd->base);
138 ti_fapll_wait_lock(fd);
143 static void ti_fapll_disable(struct clk_hw *hw)
145 struct fapll_data *fd = to_fapll(hw);
146 u32 v = readl_relaxed(fd->base);
148 v &= ~FAPLL_MAIN_PLLEN;
149 writel_relaxed(v, fd->base);
152 static int ti_fapll_is_enabled(struct clk_hw *hw)
154 struct fapll_data *fd = to_fapll(hw);
155 u32 v = readl_relaxed(fd->base);
157 return v & FAPLL_MAIN_PLLEN;
160 static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
161 unsigned long parent_rate)
163 struct fapll_data *fd = to_fapll(hw);
164 u32 fapll_n, fapll_p, v;
167 if (ti_fapll_clock_is_bypass(fd))
172 /* PLL pre-divider is P and multiplier is N */
173 v = readl_relaxed(fd->base);
174 fapll_p = (v >> 8) & 0xff;
176 do_div(rate, fapll_p);
184 static u8 ti_fapll_get_parent(struct clk_hw *hw)
186 struct fapll_data *fd = to_fapll(hw);
188 if (ti_fapll_clock_is_bypass(fd))
194 static int ti_fapll_set_div_mult(unsigned long rate,
195 unsigned long parent_rate,
196 u32 *pre_div_p, u32 *mult_n)
199 * So far no luck getting decent clock with PLL divider,
200 * PLL does not seem to lock and the signal does not look
201 * right. It seems the divider can only be used together
202 * with the multiplier?
204 if (rate < parent_rate) {
205 pr_warn("FAPLL main divider rates unsupported\n");
209 *mult_n = rate / parent_rate;
210 if (*mult_n > FAPLL_MAIN_MAX_MULT_N)
217 static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
218 unsigned long *parent_rate)
220 u32 pre_div_p, mult_n;
226 error = ti_fapll_set_div_mult(rate, *parent_rate,
227 &pre_div_p, &mult_n);
231 rate = *parent_rate / pre_div_p;
237 static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate,
238 unsigned long parent_rate)
240 struct fapll_data *fd = to_fapll(hw);
241 u32 pre_div_p, mult_n, v;
247 error = ti_fapll_set_div_mult(rate, parent_rate,
248 &pre_div_p, &mult_n);
252 ti_fapll_set_bypass(fd);
253 v = readl_relaxed(fd->base);
254 v &= ~FAPLL_MAIN_CLEAR_MASK;
255 v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT;
256 v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT;
257 writel_relaxed(v, fd->base);
258 if (ti_fapll_is_enabled(hw))
259 ti_fapll_wait_lock(fd);
260 ti_fapll_clear_bypass(fd);
265 static const struct clk_ops ti_fapll_ops = {
266 .enable = ti_fapll_enable,
267 .disable = ti_fapll_disable,
268 .is_enabled = ti_fapll_is_enabled,
269 .recalc_rate = ti_fapll_recalc_rate,
270 .get_parent = ti_fapll_get_parent,
271 .round_rate = ti_fapll_round_rate,
272 .set_rate = ti_fapll_set_rate,
275 static int ti_fapll_synth_enable(struct clk_hw *hw)
277 struct fapll_synth *synth = to_synth(hw);
278 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
280 v &= ~(1 << synth->index);
281 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
286 static void ti_fapll_synth_disable(struct clk_hw *hw)
288 struct fapll_synth *synth = to_synth(hw);
289 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
291 v |= 1 << synth->index;
292 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
295 static int ti_fapll_synth_is_enabled(struct clk_hw *hw)
297 struct fapll_synth *synth = to_synth(hw);
298 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
300 return !(v & (1 << synth->index));
304 * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info
306 static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
307 unsigned long parent_rate)
309 struct fapll_synth *synth = to_synth(hw);
313 /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
318 * PLL in bypass sets the synths in bypass mode too. The PLL rate
319 * can be also be set to 27MHz, so we can't use parent_rate to
320 * check for bypass mode.
322 if (ti_fapll_clock_is_bypass(synth->fd))
328 * Synth frequency integer and fractional divider.
329 * Note that the phase output K is 8, so the result needs
330 * to be multiplied by SYNTH_PHASE_K.
333 u32 v, synth_int_div, synth_frac_div, synth_div_freq;
335 v = readl_relaxed(synth->freq);
336 synth_int_div = (v >> 24) & 0xf;
337 synth_frac_div = v & 0xffffff;
338 synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
340 do_div(rate, synth_div_freq);
341 rate *= SYNTH_PHASE_K;
344 /* Synth post-divider M */
345 synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
347 return DIV_ROUND_UP_ULL(rate, synth_div_m);
350 static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw,
351 unsigned long parent_rate)
353 struct fapll_synth *synth = to_synth(hw);
354 unsigned long current_rate, frac_rate;
357 current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate);
358 post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
359 frac_rate = current_rate * post_div_m;
364 static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
366 unsigned long parent_rate)
368 u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
370 post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate);
371 post_div_m = post_div_m / SYNTH_MAX_INT_DIV;
372 if (post_div_m > SYNTH_MAX_DIV_M)
377 for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
378 synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
382 synth_frac_div = synth_int_div % 10000000;
383 synth_int_div /= 10000000;
385 if (synth_int_div <= SYNTH_MAX_INT_DIV)
389 if (synth_int_div > SYNTH_MAX_INT_DIV)
392 v = readl_relaxed(synth->freq);
394 v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24;
395 v |= (synth_frac_div & 0xffffff);
397 writel_relaxed(v, synth->freq);
402 static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate,
403 unsigned long *parent_rate)
405 struct fapll_synth *synth = to_synth(hw);
406 struct fapll_data *fd = synth->fd;
409 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
412 /* Only post divider m available with no fractional divider? */
414 unsigned long frac_rate;
415 u32 synth_post_div_m;
417 frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate);
418 synth_post_div_m = DIV_ROUND_UP(frac_rate, rate);
419 r = DIV_ROUND_UP(frac_rate, synth_post_div_m);
423 r = *parent_rate * SYNTH_PHASE_K;
427 r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M);
436 static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate,
437 unsigned long parent_rate)
439 struct fapll_synth *synth = to_synth(hw);
440 struct fapll_data *fd = synth->fd;
441 unsigned long frac_rate, post_rate = 0;
442 u32 post_div_m = 0, v;
444 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
447 /* Produce the rate with just post divider M? */
448 frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate);
449 if (frac_rate < rate) {
453 post_div_m = DIV_ROUND_UP(frac_rate, rate);
454 if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M))
455 post_rate = DIV_ROUND_UP(frac_rate, post_div_m);
456 if (!synth->freq && !post_rate)
460 /* Need to recalculate the fractional divider? */
461 if ((post_rate != rate) && synth->freq)
462 post_div_m = ti_fapll_synth_set_frac_rate(synth,
466 v = readl_relaxed(synth->div);
467 v &= ~SYNTH_MAX_DIV_M;
470 writel_relaxed(v, synth->div);
475 static const struct clk_ops ti_fapll_synt_ops = {
476 .enable = ti_fapll_synth_enable,
477 .disable = ti_fapll_synth_disable,
478 .is_enabled = ti_fapll_synth_is_enabled,
479 .recalc_rate = ti_fapll_synth_recalc_rate,
480 .round_rate = ti_fapll_synth_round_rate,
481 .set_rate = ti_fapll_synth_set_rate,
484 static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
492 struct clk_init_data *init;
493 struct fapll_synth *synth;
494 struct clk *clk = ERR_PTR(-ENOMEM);
496 init = kzalloc(sizeof(*init), GFP_KERNEL);
498 return ERR_PTR(-ENOMEM);
500 init->ops = &ti_fapll_synt_ops;
502 init->parent_names = &parent;
503 init->num_parents = 1;
505 synth = kzalloc(sizeof(*synth), GFP_KERNEL);
510 synth->index = index;
514 synth->hw.init = init;
515 synth->clk_pll = pll_clk;
517 clk = clk_register(NULL, &synth->hw);
519 pr_err("failed to register clock\n");
532 static void __init ti_fapll_setup(struct device_node *node)
534 struct fapll_data *fd;
535 struct clk_init_data *init = NULL;
536 const char *parent_name[2];
541 fd = kzalloc(sizeof(*fd), GFP_KERNEL);
545 fd->outputs.clks = kzalloc(sizeof(struct clk *) *
546 MAX_FAPLL_OUTPUTS + 1,
548 if (!fd->outputs.clks)
551 init = kzalloc(sizeof(*init), GFP_KERNEL);
555 init->ops = &ti_fapll_ops;
556 name = ti_dt_clk_name(node);
559 init->num_parents = of_clk_get_parent_count(node);
560 if (init->num_parents != 2) {
561 pr_err("%pOFn must have two parents\n", node);
565 of_clk_parent_fill(node, parent_name, 2);
566 init->parent_names = parent_name;
568 fd->clk_ref = of_clk_get(node, 0);
569 if (IS_ERR(fd->clk_ref)) {
570 pr_err("%pOFn could not get clk_ref\n", node);
574 fd->clk_bypass = of_clk_get(node, 1);
575 if (IS_ERR(fd->clk_bypass)) {
576 pr_err("%pOFn could not get clk_bypass\n", node);
580 fd->base = of_iomap(node, 0);
582 pr_err("%pOFn could not get IO base\n", node);
586 if (fapll_is_ddr_pll(fd->base))
587 fd->bypass_bit_inverted = true;
592 /* Register the parent PLL */
593 pll_clk = clk_register(NULL, &fd->hw);
597 fd->outputs.clks[0] = pll_clk;
598 fd->outputs.clk_num++;
601 * Set up the child synthesizers starting at index 1 as the
602 * PLL output is at index 0. We need to check the clock-indices
603 * for numbering in case there are holes in the synth mapping,
604 * and then probe the synth register to see if it has a FREQ
605 * register available.
607 for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) {
608 const char *output_name;
609 void __iomem *freq, *div;
610 struct clk *synth_clk;
614 if (of_property_read_string_index(node, "clock-output-names",
618 if (of_property_read_u32_index(node, "clock-indices", i,
622 freq = fd->base + (output_instance * 8);
625 /* Check for hardwired audio_pll_clk1 */
626 if (is_audio_pll_clk1(freq)) {
630 /* Does the synthesizer have a FREQ register? */
631 v = readl_relaxed(freq);
635 synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
636 output_name, name, pll_clk);
637 if (IS_ERR(synth_clk))
640 fd->outputs.clks[output_instance] = synth_clk;
641 fd->outputs.clk_num++;
643 clk_register_clkdev(synth_clk, output_name, NULL);
646 /* Register the child synthesizers as the FAPLL outputs */
647 of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs);
648 /* Add clock alias for the outputs */
658 clk_put(fd->clk_bypass);
660 clk_put(fd->clk_ref);
661 kfree(fd->outputs.clks);
666 CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);