4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 #define div_mask(d) ((1 << ((d)->width)) - 1)
31 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
33 unsigned int maxdiv = 0;
34 const struct clk_div_table *clkt;
36 for (clkt = table; clkt->div; clkt++)
37 if (clkt->div > maxdiv)
42 static unsigned int _get_maxdiv(struct clk_omap_divider *divider)
44 if (divider->flags & CLK_DIVIDER_ONE_BASED)
45 return div_mask(divider);
46 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
47 return 1 << div_mask(divider);
49 return _get_table_maxdiv(divider->table);
50 return div_mask(divider) + 1;
53 static unsigned int _get_table_div(const struct clk_div_table *table,
56 const struct clk_div_table *clkt;
58 for (clkt = table; clkt->div; clkt++)
64 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
66 if (divider->flags & CLK_DIVIDER_ONE_BASED)
68 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
71 return _get_table_div(divider->table, val);
75 static unsigned int _get_table_val(const struct clk_div_table *table,
78 const struct clk_div_table *clkt;
80 for (clkt = table; clkt->div; clkt++)
86 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
88 if (divider->flags & CLK_DIVIDER_ONE_BASED)
90 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
93 return _get_table_val(divider->table, div);
97 static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
98 unsigned long parent_rate)
100 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
101 unsigned int div, val;
103 val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
104 val &= div_mask(divider);
106 div = _get_div(divider, val);
108 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
109 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
110 clk_hw_get_name(hw));
114 return DIV_ROUND_UP(parent_rate, div);
118 * The reverse of DIV_ROUND_UP: The maximum number which
121 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
123 static bool _is_valid_table_div(const struct clk_div_table *table,
126 const struct clk_div_table *clkt;
128 for (clkt = table; clkt->div; clkt++)
129 if (clkt->div == div)
134 static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
136 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
137 return is_power_of_2(div);
139 return _is_valid_table_div(divider->table, div);
143 static int _div_round_up(const struct clk_div_table *table,
144 unsigned long parent_rate, unsigned long rate)
146 const struct clk_div_table *clkt;
148 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
150 for (clkt = table; clkt->div; clkt++) {
151 if (clkt->div == div)
153 else if (clkt->div < div)
156 if ((clkt->div - div) < (up - div))
163 static int _div_round(const struct clk_div_table *table,
164 unsigned long parent_rate, unsigned long rate)
167 return DIV_ROUND_UP(parent_rate, rate);
169 return _div_round_up(table, parent_rate, rate);
172 static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
173 unsigned long *best_parent_rate)
175 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
177 unsigned long parent_rate, best = 0, now, maxdiv;
178 unsigned long parent_rate_saved = *best_parent_rate;
183 maxdiv = _get_maxdiv(divider);
185 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
186 parent_rate = *best_parent_rate;
187 bestdiv = _div_round(divider->table, parent_rate, rate);
188 bestdiv = bestdiv == 0 ? 1 : bestdiv;
189 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
194 * The maximum divider we can use without overflowing
195 * unsigned long in rate * i below
197 maxdiv = min(ULONG_MAX / rate, maxdiv);
199 for (i = 1; i <= maxdiv; i++) {
200 if (!_is_valid_div(divider, i))
202 if (rate * i == parent_rate_saved) {
204 * It's the most ideal case if the requested rate can be
205 * divided from parent clock without needing to change
206 * parent rate, so return the divider immediately.
208 *best_parent_rate = parent_rate_saved;
211 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
212 MULT_ROUND_UP(rate, i));
213 now = DIV_ROUND_UP(parent_rate, i);
214 if (now <= rate && now > best) {
217 *best_parent_rate = parent_rate;
222 bestdiv = _get_maxdiv(divider);
224 clk_hw_round_rate(clk_hw_get_parent(hw), 1);
230 static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
231 unsigned long *prate)
234 div = ti_clk_divider_bestdiv(hw, rate, prate);
236 return DIV_ROUND_UP(*prate, div);
239 static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
240 unsigned long parent_rate)
242 struct clk_omap_divider *divider;
243 unsigned int div, value;
249 divider = to_clk_omap_divider(hw);
251 div = DIV_ROUND_UP(parent_rate, rate);
252 value = _get_val(divider, div);
254 if (value > div_mask(divider))
255 value = div_mask(divider);
257 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
258 val = div_mask(divider) << (divider->shift + 16);
260 val = ti_clk_ll_ops->clk_readl(÷r->reg);
261 val &= ~(div_mask(divider) << divider->shift);
263 val |= value << divider->shift;
264 ti_clk_ll_ops->clk_writel(val, ÷r->reg);
269 const struct clk_ops ti_clk_divider_ops = {
270 .recalc_rate = ti_clk_divider_recalc_rate,
271 .round_rate = ti_clk_divider_round_rate,
272 .set_rate = ti_clk_divider_set_rate,
275 static struct clk *_register_divider(struct device *dev, const char *name,
276 const char *parent_name,
278 struct clk_omap_reg *reg,
279 u8 shift, u8 width, u8 clk_divider_flags,
280 const struct clk_div_table *table)
282 struct clk_omap_divider *div;
284 struct clk_init_data init;
286 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
287 if (width + shift > 16) {
288 pr_warn("divider value exceeds LOWORD field\n");
289 return ERR_PTR(-EINVAL);
293 /* allocate the divider */
294 div = kzalloc(sizeof(*div), GFP_KERNEL);
296 pr_err("%s: could not allocate divider clk\n", __func__);
297 return ERR_PTR(-ENOMEM);
301 init.ops = &ti_clk_divider_ops;
302 init.flags = flags | CLK_IS_BASIC;
303 init.parent_names = (parent_name ? &parent_name : NULL);
304 init.num_parents = (parent_name ? 1 : 0);
306 /* struct clk_divider assignments */
307 memcpy(&div->reg, reg, sizeof(*reg));
310 div->flags = clk_divider_flags;
311 div->hw.init = &init;
314 /* register the clock */
315 clk = ti_clk_register(dev, &div->hw, name);
323 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
325 const struct clk_div_table **table)
331 struct clk_div_table *tmp;
334 if (flags & CLKF_INDEX_STARTS_AT_ONE)
341 while (div < max_div) {
342 if (flags & CLKF_INDEX_POWER_OF_TWO)
357 while (!num_dividers || i < num_dividers) {
358 if (div_table[i] == -1)
367 tmp = kzalloc(sizeof(*tmp) * (valid_div + 1), GFP_KERNEL);
374 for (i = 0; i < num_dividers; i++)
375 if (div_table[i] > 0) {
376 tmp[valid_div].div = div_table[i];
377 tmp[valid_div].val = i;
382 *width = fls(*width);
388 static const struct clk_div_table *
389 _get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
391 const struct clk_div_table *table = NULL;
393 ti_clk_parse_divider_data(setup->dividers, setup->num_dividers,
394 setup->max_div, setup->flags, width,
400 struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
402 struct clk_omap_divider *div;
403 struct clk_omap_reg *reg;
408 div = kzalloc(sizeof(*div), GFP_KERNEL);
410 return ERR_PTR(-ENOMEM);
412 reg = (struct clk_omap_reg *)&div->reg;
413 reg->index = setup->module;
414 reg->offset = setup->reg;
416 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
417 div->flags |= CLK_DIVIDER_ONE_BASED;
419 if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
420 div->flags |= CLK_DIVIDER_POWER_OF_TWO;
422 div->table = _get_div_table_from_setup(setup, &div->width);
424 div->shift = setup->bit_shift;
429 struct clk *ti_clk_register_divider(struct ti_clk *setup)
431 struct ti_clk_divider *div = setup->data;
432 struct clk_omap_reg reg = {
433 .index = div->module,
439 const struct clk_div_table *table;
442 if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
443 div_flags |= CLK_DIVIDER_ONE_BASED;
445 if (div->flags & CLKF_INDEX_POWER_OF_TWO)
446 div_flags |= CLK_DIVIDER_POWER_OF_TWO;
448 if (div->flags & CLKF_SET_RATE_PARENT)
449 flags |= CLK_SET_RATE_PARENT;
451 table = _get_div_table_from_setup(div, &width);
453 return (struct clk *)table;
455 clk = _register_divider(NULL, setup->name, div->parent,
456 flags, ®, div->bit_shift,
457 width, div_flags, table);
465 static struct clk_div_table *
466 __init ti_clk_get_div_table(struct device_node *node)
468 struct clk_div_table *table;
469 const __be32 *divspec;
475 divspec = of_get_property(node, "ti,dividers", &num_div);
484 /* Determine required size for divider table */
485 for (i = 0; i < num_div; i++) {
486 of_property_read_u32_index(node, "ti,dividers", i, &val);
492 pr_err("no valid dividers for %s table\n", node->name);
493 return ERR_PTR(-EINVAL);
496 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
499 return ERR_PTR(-ENOMEM);
503 for (i = 0; i < num_div; i++) {
504 of_property_read_u32_index(node, "ti,dividers", i, &val);
506 table[valid_div].div = val;
507 table[valid_div].val = i;
515 static int _get_divider_width(struct device_node *node,
516 const struct clk_div_table *table,
525 /* Clk divider table not provided, determine min/max divs */
526 if (of_property_read_u32(node, "ti,min-div", &min_div))
529 if (of_property_read_u32(node, "ti,max-div", &max_div)) {
530 pr_err("no max-div for %s!\n", node->name);
534 /* Determine bit width for the field */
535 if (flags & CLK_DIVIDER_ONE_BASED)
540 while (div < max_div) {
541 if (flags & CLK_DIVIDER_POWER_OF_TWO)
550 while (table[div].div) {
551 val = table[div].val;
559 static int __init ti_clk_divider_populate(struct device_node *node,
560 struct clk_omap_reg *reg, const struct clk_div_table **table,
561 u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
566 ret = ti_clk_get_reg_addr(node, 0, reg);
570 if (!of_property_read_u32(node, "ti,bit-shift", &val))
578 if (of_property_read_bool(node, "ti,index-starts-at-one"))
579 *div_flags |= CLK_DIVIDER_ONE_BASED;
581 if (of_property_read_bool(node, "ti,index-power-of-two"))
582 *div_flags |= CLK_DIVIDER_POWER_OF_TWO;
584 if (of_property_read_bool(node, "ti,set-rate-parent"))
585 *flags |= CLK_SET_RATE_PARENT;
587 *table = ti_clk_get_div_table(node);
590 return PTR_ERR(*table);
592 *width = _get_divider_width(node, *table, *div_flags);
598 * of_ti_divider_clk_setup - Setup function for simple div rate clock
599 * @node: device node for this clock
601 * Sets up a basic divider clock.
603 static void __init of_ti_divider_clk_setup(struct device_node *node)
606 const char *parent_name;
607 struct clk_omap_reg reg;
608 u8 clk_divider_flags = 0;
611 const struct clk_div_table *table = NULL;
614 parent_name = of_clk_get_parent_name(node, 0);
616 if (ti_clk_divider_populate(node, ®, &table, &flags,
617 &clk_divider_flags, &width, &shift))
620 clk = _register_divider(NULL, node->name, parent_name, flags, ®,
621 shift, width, clk_divider_flags, table);
624 of_clk_add_provider(node, of_clk_src_simple_get, clk);
625 of_ti_clk_autoidle_setup(node);
632 CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
634 static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
636 struct clk_omap_divider *div;
639 div = kzalloc(sizeof(*div), GFP_KERNEL);
643 if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
644 &div->flags, &div->width, &div->shift) < 0)
647 if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
654 CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
655 of_ti_composite_divider_clk_setup);