4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 static unsigned int _get_table_div(const struct clk_div_table *table,
32 const struct clk_div_table *clkt;
34 for (clkt = table; clkt->div; clkt++)
40 static void _setup_mask(struct clk_omap_divider *divider)
44 const struct clk_div_table *clkt;
49 for (clkt = divider->table; clkt->div; clkt++)
50 if (clkt->val > max_val)
53 max_val = divider->max;
55 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) &&
56 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO))
60 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
61 mask = fls(max_val) - 1;
65 divider->mask = (1 << fls(mask)) - 1;
68 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
70 if (divider->flags & CLK_DIVIDER_ONE_BASED)
72 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
75 return _get_table_div(divider->table, val);
79 static unsigned int _get_table_val(const struct clk_div_table *table,
82 const struct clk_div_table *clkt;
84 for (clkt = table; clkt->div; clkt++)
90 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
92 if (divider->flags & CLK_DIVIDER_ONE_BASED)
94 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
97 return _get_table_val(divider->table, div);
101 static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
102 unsigned long parent_rate)
104 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
105 unsigned int div, val;
107 val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
108 val &= divider->mask;
110 div = _get_div(divider, val);
112 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
113 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
114 clk_hw_get_name(hw));
118 return DIV_ROUND_UP(parent_rate, div);
122 * The reverse of DIV_ROUND_UP: The maximum number which
125 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
127 static bool _is_valid_table_div(const struct clk_div_table *table,
130 const struct clk_div_table *clkt;
132 for (clkt = table; clkt->div; clkt++)
133 if (clkt->div == div)
138 static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
140 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
141 return is_power_of_2(div);
143 return _is_valid_table_div(divider->table, div);
147 static int _div_round_up(const struct clk_div_table *table,
148 unsigned long parent_rate, unsigned long rate)
150 const struct clk_div_table *clkt;
152 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
154 for (clkt = table; clkt->div; clkt++) {
155 if (clkt->div == div)
157 else if (clkt->div < div)
160 if ((clkt->div - div) < (up - div))
167 static int _div_round(const struct clk_div_table *table,
168 unsigned long parent_rate, unsigned long rate)
171 return DIV_ROUND_UP(parent_rate, rate);
173 return _div_round_up(table, parent_rate, rate);
176 static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
177 unsigned long *best_parent_rate)
179 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
181 unsigned long parent_rate, best = 0, now, maxdiv;
182 unsigned long parent_rate_saved = *best_parent_rate;
187 maxdiv = divider->max;
189 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
190 parent_rate = *best_parent_rate;
191 bestdiv = _div_round(divider->table, parent_rate, rate);
192 bestdiv = bestdiv == 0 ? 1 : bestdiv;
193 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
198 * The maximum divider we can use without overflowing
199 * unsigned long in rate * i below
201 maxdiv = min(ULONG_MAX / rate, maxdiv);
203 for (i = 1; i <= maxdiv; i++) {
204 if (!_is_valid_div(divider, i))
206 if (rate * i == parent_rate_saved) {
208 * It's the most ideal case if the requested rate can be
209 * divided from parent clock without needing to change
210 * parent rate, so return the divider immediately.
212 *best_parent_rate = parent_rate_saved;
215 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
216 MULT_ROUND_UP(rate, i));
217 now = DIV_ROUND_UP(parent_rate, i);
218 if (now <= rate && now > best) {
221 *best_parent_rate = parent_rate;
226 bestdiv = divider->max;
228 clk_hw_round_rate(clk_hw_get_parent(hw), 1);
234 static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
235 unsigned long *prate)
238 div = ti_clk_divider_bestdiv(hw, rate, prate);
240 return DIV_ROUND_UP(*prate, div);
243 static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
244 unsigned long parent_rate)
246 struct clk_omap_divider *divider;
247 unsigned int div, value;
253 divider = to_clk_omap_divider(hw);
255 div = DIV_ROUND_UP(parent_rate, rate);
257 if (div > divider->max)
259 if (div < divider->min)
262 value = _get_val(divider, div);
264 val = ti_clk_ll_ops->clk_readl(÷r->reg);
265 val &= ~(divider->mask << divider->shift);
266 val |= value << divider->shift;
267 ti_clk_ll_ops->clk_writel(val, ÷r->reg);
269 ti_clk_latch(÷r->reg, divider->latch);
275 * clk_divider_save_context - Save the divider value
276 * @hw: pointer struct clk_hw
278 * Save the divider value
280 static int clk_divider_save_context(struct clk_hw *hw)
282 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
285 val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
286 divider->context = val & divider->mask;
292 * clk_divider_restore_context - restore the saved the divider value
293 * @hw: pointer struct clk_hw
295 * Restore the saved the divider value
297 static void clk_divider_restore_context(struct clk_hw *hw)
299 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
302 val = ti_clk_ll_ops->clk_readl(÷r->reg);
303 val &= ~(divider->mask << divider->shift);
304 val |= divider->context << divider->shift;
305 ti_clk_ll_ops->clk_writel(val, ÷r->reg);
308 const struct clk_ops ti_clk_divider_ops = {
309 .recalc_rate = ti_clk_divider_recalc_rate,
310 .round_rate = ti_clk_divider_round_rate,
311 .set_rate = ti_clk_divider_set_rate,
312 .save_context = clk_divider_save_context,
313 .restore_context = clk_divider_restore_context,
316 static struct clk *_register_divider(struct device_node *node,
318 struct clk_omap_divider *div)
320 struct clk_init_data init;
321 const char *parent_name;
324 parent_name = of_clk_get_parent_name(node, 0);
326 name = ti_dt_clk_name(node);
328 init.ops = &ti_clk_divider_ops;
330 init.parent_names = (parent_name ? &parent_name : NULL);
331 init.num_parents = (parent_name ? 1 : 0);
333 div->hw.init = &init;
335 /* register the clock */
336 return of_ti_clk_register(node, &div->hw, name);
339 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
340 u8 flags, struct clk_omap_divider *divider)
344 struct clk_div_table *tmp;
349 divider->max = max_div;
350 _setup_mask(divider);
356 while (!num_dividers || i < num_dividers) {
357 if (div_table[i] == -1)
366 tmp = kcalloc(valid_div + 1, sizeof(*tmp), GFP_KERNEL);
372 for (i = 0; i < num_dividers; i++)
373 if (div_table[i] > 0) {
374 tmp[valid_div].div = div_table[i];
375 tmp[valid_div].val = i;
377 if (div_table[i] > max_div)
378 max_div = div_table[i];
379 if (!min_div || div_table[i] < min_div)
380 min_div = div_table[i];
383 divider->min = min_div;
384 divider->max = max_div;
385 divider->table = tmp;
386 _setup_mask(divider);
391 static int __init ti_clk_get_div_table(struct device_node *node,
392 struct clk_omap_divider *div)
394 struct clk_div_table *table;
395 const __be32 *divspec;
401 divspec = of_get_property(node, "ti,dividers", &num_div);
410 /* Determine required size for divider table */
411 for (i = 0; i < num_div; i++) {
412 of_property_read_u32_index(node, "ti,dividers", i, &val);
418 pr_err("no valid dividers for %pOFn table\n", node);
422 table = kcalloc(valid_div + 1, sizeof(*table), GFP_KERNEL);
428 for (i = 0; i < num_div; i++) {
429 of_property_read_u32_index(node, "ti,dividers", i, &val);
431 table[valid_div].div = val;
432 table[valid_div].val = i;
442 static int _populate_divider_min_max(struct device_node *node,
443 struct clk_omap_divider *divider)
448 const struct clk_div_table *clkt;
450 if (!divider->table) {
451 /* Clk divider table not provided, determine min/max divs */
452 if (of_property_read_u32(node, "ti,min-div", &min_div))
455 if (of_property_read_u32(node, "ti,max-div", &max_div)) {
456 pr_err("no max-div for %pOFn!\n", node);
461 for (clkt = divider->table; clkt->div; clkt++) {
465 if (!min_div || val < min_div)
470 divider->min = min_div;
471 divider->max = max_div;
472 _setup_mask(divider);
477 static int __init ti_clk_divider_populate(struct device_node *node,
478 struct clk_omap_divider *div,
484 ret = ti_clk_get_reg_addr(node, 0, &div->reg);
488 if (!of_property_read_u32(node, "ti,bit-shift", &val))
493 if (!of_property_read_u32(node, "ti,latch-bit", &val))
496 div->latch = -EINVAL;
501 if (of_property_read_bool(node, "ti,index-starts-at-one"))
502 div->flags |= CLK_DIVIDER_ONE_BASED;
504 if (of_property_read_bool(node, "ti,index-power-of-two"))
505 div->flags |= CLK_DIVIDER_POWER_OF_TWO;
507 if (of_property_read_bool(node, "ti,set-rate-parent"))
508 *flags |= CLK_SET_RATE_PARENT;
510 ret = ti_clk_get_div_table(node, div);
514 return _populate_divider_min_max(node, div);
518 * of_ti_divider_clk_setup - Setup function for simple div rate clock
519 * @node: device node for this clock
521 * Sets up a basic divider clock.
523 static void __init of_ti_divider_clk_setup(struct device_node *node)
527 struct clk_omap_divider *div;
529 div = kzalloc(sizeof(*div), GFP_KERNEL);
533 if (ti_clk_divider_populate(node, div, &flags))
536 clk = _register_divider(node, flags, div);
538 of_clk_add_provider(node, of_clk_src_simple_get, clk);
539 of_ti_clk_autoidle_setup(node);
547 CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
549 static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
551 struct clk_omap_divider *div;
554 div = kzalloc(sizeof(*div), GFP_KERNEL);
558 if (ti_clk_divider_populate(node, div, &tmp))
561 if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
568 CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
569 of_ti_composite_divider_clk_setup);