4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 #define div_mask(d) ((1 << ((d)->width)) - 1)
31 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
33 unsigned int maxdiv = 0;
34 const struct clk_div_table *clkt;
36 for (clkt = table; clkt->div; clkt++)
37 if (clkt->div > maxdiv)
42 static unsigned int _get_maxdiv(struct clk_divider *divider)
44 if (divider->flags & CLK_DIVIDER_ONE_BASED)
45 return div_mask(divider);
46 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
47 return 1 << div_mask(divider);
49 return _get_table_maxdiv(divider->table);
50 return div_mask(divider) + 1;
53 static unsigned int _get_table_div(const struct clk_div_table *table,
56 const struct clk_div_table *clkt;
58 for (clkt = table; clkt->div; clkt++)
64 static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
66 if (divider->flags & CLK_DIVIDER_ONE_BASED)
68 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
71 return _get_table_div(divider->table, val);
75 static unsigned int _get_table_val(const struct clk_div_table *table,
78 const struct clk_div_table *clkt;
80 for (clkt = table; clkt->div; clkt++)
86 static unsigned int _get_val(struct clk_divider *divider, u8 div)
88 if (divider->flags & CLK_DIVIDER_ONE_BASED)
90 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
93 return _get_table_val(divider->table, div);
97 static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
98 unsigned long parent_rate)
100 struct clk_divider *divider = to_clk_divider(hw);
101 unsigned int div, val;
103 val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;
104 val &= div_mask(divider);
106 div = _get_div(divider, val);
108 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
109 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
110 clk_hw_get_name(hw));
114 return DIV_ROUND_UP(parent_rate, div);
118 * The reverse of DIV_ROUND_UP: The maximum number which
121 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
123 static bool _is_valid_table_div(const struct clk_div_table *table,
126 const struct clk_div_table *clkt;
128 for (clkt = table; clkt->div; clkt++)
129 if (clkt->div == div)
134 static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
136 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
137 return is_power_of_2(div);
139 return _is_valid_table_div(divider->table, div);
143 static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
144 unsigned long *best_parent_rate)
146 struct clk_divider *divider = to_clk_divider(hw);
148 unsigned long parent_rate, best = 0, now, maxdiv;
149 unsigned long parent_rate_saved = *best_parent_rate;
154 maxdiv = _get_maxdiv(divider);
156 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
157 parent_rate = *best_parent_rate;
158 bestdiv = DIV_ROUND_UP(parent_rate, rate);
159 bestdiv = bestdiv == 0 ? 1 : bestdiv;
160 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
165 * The maximum divider we can use without overflowing
166 * unsigned long in rate * i below
168 maxdiv = min(ULONG_MAX / rate, maxdiv);
170 for (i = 1; i <= maxdiv; i++) {
171 if (!_is_valid_div(divider, i))
173 if (rate * i == parent_rate_saved) {
175 * It's the most ideal case if the requested rate can be
176 * divided from parent clock without needing to change
177 * parent rate, so return the divider immediately.
179 *best_parent_rate = parent_rate_saved;
182 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
183 MULT_ROUND_UP(rate, i));
184 now = DIV_ROUND_UP(parent_rate, i);
185 if (now <= rate && now > best) {
188 *best_parent_rate = parent_rate;
193 bestdiv = _get_maxdiv(divider);
195 clk_hw_round_rate(clk_hw_get_parent(hw), 1);
201 static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
202 unsigned long *prate)
205 div = ti_clk_divider_bestdiv(hw, rate, prate);
207 return DIV_ROUND_UP(*prate, div);
210 static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
211 unsigned long parent_rate)
213 struct clk_divider *divider;
214 unsigned int div, value;
220 divider = to_clk_divider(hw);
222 div = DIV_ROUND_UP(parent_rate, rate);
223 value = _get_val(divider, div);
225 if (value > div_mask(divider))
226 value = div_mask(divider);
228 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
229 val = div_mask(divider) << (divider->shift + 16);
231 val = ti_clk_ll_ops->clk_readl(divider->reg);
232 val &= ~(div_mask(divider) << divider->shift);
234 val |= value << divider->shift;
235 ti_clk_ll_ops->clk_writel(val, divider->reg);
240 const struct clk_ops ti_clk_divider_ops = {
241 .recalc_rate = ti_clk_divider_recalc_rate,
242 .round_rate = ti_clk_divider_round_rate,
243 .set_rate = ti_clk_divider_set_rate,
246 static struct clk *_register_divider(struct device *dev, const char *name,
247 const char *parent_name,
248 unsigned long flags, void __iomem *reg,
249 u8 shift, u8 width, u8 clk_divider_flags,
250 const struct clk_div_table *table)
252 struct clk_divider *div;
254 struct clk_init_data init;
256 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
257 if (width + shift > 16) {
258 pr_warn("divider value exceeds LOWORD field\n");
259 return ERR_PTR(-EINVAL);
263 /* allocate the divider */
264 div = kzalloc(sizeof(*div), GFP_KERNEL);
266 pr_err("%s: could not allocate divider clk\n", __func__);
267 return ERR_PTR(-ENOMEM);
271 init.ops = &ti_clk_divider_ops;
272 init.flags = flags | CLK_IS_BASIC;
273 init.parent_names = (parent_name ? &parent_name : NULL);
274 init.num_parents = (parent_name ? 1 : 0);
276 /* struct clk_divider assignments */
280 div->flags = clk_divider_flags;
281 div->hw.init = &init;
284 /* register the clock */
285 clk = clk_register(dev, &div->hw);
293 static struct clk_div_table *
294 _get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
297 struct clk_div_table *table;
303 if (!setup->num_dividers) {
304 /* Clk divider table not provided, determine min/max divs */
305 flags = setup->flags;
307 if (flags & CLKF_INDEX_STARTS_AT_ONE)
314 while (div < setup->max_div) {
315 if (flags & CLKF_INDEX_POWER_OF_TWO)
327 for (i = 0; i < setup->num_dividers; i++)
328 if (setup->dividers[i])
331 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
333 return ERR_PTR(-ENOMEM);
338 for (i = 0; i < setup->num_dividers; i++)
339 if (setup->dividers[i]) {
340 table[valid_div].div = setup->dividers[i];
341 table[valid_div].val = i;
346 *width = fls(*width);
351 struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
353 struct clk_divider *div;
354 struct clk_omap_reg *reg;
359 div = kzalloc(sizeof(*div), GFP_KERNEL);
361 return ERR_PTR(-ENOMEM);
363 reg = (struct clk_omap_reg *)&div->reg;
364 reg->index = setup->module;
365 reg->offset = setup->reg;
367 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
368 div->flags |= CLK_DIVIDER_ONE_BASED;
370 if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
371 div->flags |= CLK_DIVIDER_POWER_OF_TWO;
373 div->table = _get_div_table_from_setup(setup, &div->width);
375 div->shift = setup->bit_shift;
380 struct clk *ti_clk_register_divider(struct ti_clk *setup)
382 struct ti_clk_divider *div;
383 struct clk_omap_reg *reg_setup;
388 struct clk_div_table *table;
393 reg_setup = (struct clk_omap_reg *)®
395 reg_setup->index = div->module;
396 reg_setup->offset = div->reg;
398 if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
399 div_flags |= CLK_DIVIDER_ONE_BASED;
401 if (div->flags & CLKF_INDEX_POWER_OF_TWO)
402 div_flags |= CLK_DIVIDER_POWER_OF_TWO;
404 if (div->flags & CLKF_SET_RATE_PARENT)
405 flags |= CLK_SET_RATE_PARENT;
407 table = _get_div_table_from_setup(div, &width);
409 return (struct clk *)table;
411 clk = _register_divider(NULL, setup->name, div->parent,
412 flags, (void __iomem *)reg, div->bit_shift,
413 width, div_flags, table);
421 static struct clk_div_table *
422 __init ti_clk_get_div_table(struct device_node *node)
424 struct clk_div_table *table;
425 const __be32 *divspec;
431 divspec = of_get_property(node, "ti,dividers", &num_div);
440 /* Determine required size for divider table */
441 for (i = 0; i < num_div; i++) {
442 of_property_read_u32_index(node, "ti,dividers", i, &val);
448 pr_err("no valid dividers for %s table\n", node->name);
449 return ERR_PTR(-EINVAL);
452 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
455 return ERR_PTR(-ENOMEM);
459 for (i = 0; i < num_div; i++) {
460 of_property_read_u32_index(node, "ti,dividers", i, &val);
462 table[valid_div].div = val;
463 table[valid_div].val = i;
471 static int _get_divider_width(struct device_node *node,
472 const struct clk_div_table *table,
481 /* Clk divider table not provided, determine min/max divs */
482 if (of_property_read_u32(node, "ti,min-div", &min_div))
485 if (of_property_read_u32(node, "ti,max-div", &max_div)) {
486 pr_err("no max-div for %s!\n", node->name);
490 /* Determine bit width for the field */
491 if (flags & CLK_DIVIDER_ONE_BASED)
496 while (div < max_div) {
497 if (flags & CLK_DIVIDER_POWER_OF_TWO)
506 while (table[div].div) {
507 val = table[div].val;
515 static int __init ti_clk_divider_populate(struct device_node *node,
516 void __iomem **reg, const struct clk_div_table **table,
517 u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
521 *reg = ti_clk_get_reg_addr(node, 0);
523 return PTR_ERR(*reg);
525 if (!of_property_read_u32(node, "ti,bit-shift", &val))
533 if (of_property_read_bool(node, "ti,index-starts-at-one"))
534 *div_flags |= CLK_DIVIDER_ONE_BASED;
536 if (of_property_read_bool(node, "ti,index-power-of-two"))
537 *div_flags |= CLK_DIVIDER_POWER_OF_TWO;
539 if (of_property_read_bool(node, "ti,set-rate-parent"))
540 *flags |= CLK_SET_RATE_PARENT;
542 *table = ti_clk_get_div_table(node);
545 return PTR_ERR(*table);
547 *width = _get_divider_width(node, *table, *div_flags);
553 * of_ti_divider_clk_setup - Setup function for simple div rate clock
554 * @node: device node for this clock
556 * Sets up a basic divider clock.
558 static void __init of_ti_divider_clk_setup(struct device_node *node)
561 const char *parent_name;
563 u8 clk_divider_flags = 0;
566 const struct clk_div_table *table = NULL;
569 parent_name = of_clk_get_parent_name(node, 0);
571 if (ti_clk_divider_populate(node, ®, &table, &flags,
572 &clk_divider_flags, &width, &shift))
575 clk = _register_divider(NULL, node->name, parent_name, flags, reg,
576 shift, width, clk_divider_flags, table);
579 of_clk_add_provider(node, of_clk_src_simple_get, clk);
580 of_ti_clk_autoidle_setup(node);
587 CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
589 static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
591 struct clk_divider *div;
594 div = kzalloc(sizeof(*div), GFP_KERNEL);
598 if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
599 &div->flags, &div->width, &div->shift) < 0)
602 if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
609 CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
610 of_ti_composite_divider_clk_setup);