2 * TI Clock driver internal definitions
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 #ifndef __DRIVERS_CLK_TI_CLOCK__
17 #define __DRIVERS_CLK_TI_CLOCK__
19 struct clk_omap_divider {
21 struct clk_omap_reg reg;
28 const struct clk_div_table *table;
32 #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
36 struct clk_omap_reg reg;
45 #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
58 #define CLKF_INDEX_POWER_OF_TWO (1 << 0)
59 #define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
60 #define CLKF_SET_RATE_PARENT (1 << 2)
61 #define CLKF_OMAP3 (1 << 3)
62 #define CLKF_AM35XX (1 << 4)
65 #define CLKF_SET_BIT_TO_DISABLE (1 << 5)
66 #define CLKF_INTERFACE (1 << 6)
67 #define CLKF_SSI (1 << 7)
68 #define CLKF_DSS (1 << 8)
69 #define CLKF_HSOTGUSB (1 << 9)
70 #define CLKF_WAIT (1 << 10)
71 #define CLKF_NO_WAIT (1 << 11)
72 #define CLKF_HSDIV (1 << 12)
73 #define CLKF_CLKDM (1 << 13)
76 #define CLKF_LOW_POWER_STOP (1 << 5)
77 #define CLKF_LOCK (1 << 6)
78 #define CLKF_LOW_POWER_BYPASS (1 << 7)
79 #define CLKF_PER (1 << 8)
80 #define CLKF_CORE (1 << 9)
81 #define CLKF_J_TYPE (1 << 10)
84 #define CLKF_SW_SUP BIT(5)
85 #define CLKF_HW_SUP BIT(6)
86 #define CLKF_NO_IDLEST BIT(7)
88 #define CLKF_SOC_MASK GENMASK(11, 8)
90 #define CLKF_SOC_NONSEC BIT(8)
91 #define CLKF_SOC_DRA72 BIT(9)
92 #define CLKF_SOC_DRA74 BIT(10)
93 #define CLKF_SOC_DRA76 BIT(11)
95 #define CLK(dev, con, ck) \
106 const char *clkdm_name;
109 struct ti_clk *patch;
118 const char * const *parents;
122 struct ti_clk_divider {
141 /* Composite clock component types */
143 CLK_COMPONENT_TYPE_GATE = 0,
144 CLK_COMPONENT_TYPE_DIVIDER,
145 CLK_COMPONENT_TYPE_MUX,
146 CLK_COMPONENT_TYPE_MAX,
150 * struct ti_dt_clk - OMAP DT clock alias declarations
151 * @lk: clock lookup definition
152 * @node_name: clock DT node to map to
155 struct clk_lookup lk;
159 #define DT_CLK(dev, con, name) \
168 /* CLKCTRL type definitions */
169 struct omap_clkctrl_div_data {
175 struct omap_clkctrl_bit_data {
178 const char * const *parents;
182 struct omap_clkctrl_reg_data {
184 const struct omap_clkctrl_bit_data *bit_data;
187 const char *clkdm_name;
190 struct omap_clkctrl_data {
192 const struct omap_clkctrl_reg_data *regs;
195 extern const struct omap_clkctrl_data omap4_clkctrl_data[];
196 extern const struct omap_clkctrl_data omap5_clkctrl_data[];
197 extern const struct omap_clkctrl_data dra7_clkctrl_data[];
198 extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
199 extern struct ti_dt_clk dra7xx_compat_clks[];
200 extern const struct omap_clkctrl_data am3_clkctrl_data[];
201 extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
202 extern struct ti_dt_clk am33xx_compat_clks[];
203 extern const struct omap_clkctrl_data am4_clkctrl_data[];
204 extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
205 extern struct ti_dt_clk am43xx_compat_clks[];
206 extern const struct omap_clkctrl_data am438x_clkctrl_data[];
207 extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
208 extern const struct omap_clkctrl_data dm814_clkctrl_data[];
209 extern const struct omap_clkctrl_data dm816_clkctrl_data[];
211 typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
213 struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw,
215 struct clk *of_ti_clk_register_omap_hw(struct device_node *node,
216 struct clk_hw *hw, const char *con);
217 const char *ti_dt_clk_name(struct device_node *np);
218 int ti_clk_add_alias(struct clk *clk, const char *con);
219 void ti_clk_add_aliases(void);
221 void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
223 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
225 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
226 u8 flags, struct clk_omap_divider *div);
228 int ti_clk_get_reg_addr(struct device_node *node, int index,
229 struct clk_omap_reg *reg);
230 void ti_dt_clocks_register(struct ti_dt_clk *oclks);
231 int ti_clk_retry_init(struct device_node *node, void *user,
232 ti_of_clk_init_cb_t func);
233 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
235 int of_ti_clk_autoidle_setup(struct device_node *node);
236 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
238 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
239 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
240 extern const struct clk_hw_omap_ops clkhwops_wait;
241 extern const struct clk_hw_omap_ops clkhwops_iclk;
242 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
243 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
244 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
245 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
246 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
247 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
248 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
249 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
251 extern const struct clk_ops ti_clk_divider_ops;
252 extern const struct clk_ops ti_clk_mux_ops;
253 extern const struct clk_ops omap_gate_clk_ops;
255 extern struct ti_clk_features ti_clk_features;
257 int omap2_init_clk_clkdm(struct clk_hw *hw);
258 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
259 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
261 int omap2_dflt_clk_enable(struct clk_hw *hw);
262 void omap2_dflt_clk_disable(struct clk_hw *hw);
263 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
264 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
265 struct clk_omap_reg *other_reg,
267 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
268 struct clk_omap_reg *idlest_reg,
269 u8 *idlest_bit, u8 *idlest_val);
271 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
272 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
274 u8 omap2_init_dpll_parent(struct clk_hw *hw);
275 int omap3_noncore_dpll_enable(struct clk_hw *hw);
276 void omap3_noncore_dpll_disable(struct clk_hw *hw);
277 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
278 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
279 unsigned long parent_rate);
280 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
282 unsigned long parent_rate,
284 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
285 struct clk_rate_request *req);
286 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
287 unsigned long *parent_rate);
288 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
289 unsigned long parent_rate);
292 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
293 * that are sourced by DPLL5, and both of these require this clock
294 * to be at 120 MHz for proper operation.
296 #define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000
298 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
299 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
300 unsigned long parent_rate);
301 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
302 unsigned long parent_rate, u8 index);
303 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
304 unsigned long parent_rate);
305 void omap3_clk_lock_dpll5(void);
307 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
308 unsigned long parent_rate);
309 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
310 unsigned long target_rate,
311 unsigned long *parent_rate);
312 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
313 struct clk_rate_request *req);
314 int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw));
316 extern struct ti_clk_ll_ops *ti_clk_ll_ops;