drivers/clk/ti/clkctrl.c

   1 /*
   2  * OMAP clkctrl clock support
   3  *
   4  * Copyright (C) 2017 Texas Instruments, Inc.
   5  *
   6  * Tero Kristo <t-kristo@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk-provider.h>
  19 #include <linux/slab.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/clk/ti.h>
  23 #include <linux/delay.h>
  24 #include <linux/timekeeping.h>
  25 #include "clock.h"
  26
  27 #define NO_IDLEST                       0x1
  28
  29 #define OMAP4_MODULEMODE_MASK           0x3
  30
  31 #define MODULEMODE_HWCTRL               0x1
  32 #define MODULEMODE_SWCTRL               0x2
  33
  34 #define OMAP4_IDLEST_MASK               (0x3 << 16)
  35 #define OMAP4_IDLEST_SHIFT              16
  36
  37 #define CLKCTRL_IDLEST_FUNCTIONAL       0x0
  38 #define CLKCTRL_IDLEST_INTERFACE_IDLE   0x2
  39 #define CLKCTRL_IDLEST_DISABLED         0x3
  40
  41 /* These timeouts are in us */
  42 #define OMAP4_MAX_MODULE_READY_TIME     2000
  43 #define OMAP4_MAX_MODULE_DISABLE_TIME   5000
  44
  45 static bool _early_timeout = true;
  46
  47 struct omap_clkctrl_provider {
  48         void __iomem *base;
  49         struct list_head clocks;
  50         char *clkdm_name;
  51 };
  52
  53 struct omap_clkctrl_clk {
  54         struct clk_hw *clk;
  55         u16 reg_offset;
  56         int bit_offset;
  57         struct list_head node;
  58 };
  59
  60 union omap4_timeout {
  61         u32 cycles;
  62         ktime_t start;
  63 };
  64
  65 static const struct omap_clkctrl_data default_clkctrl_data[] __initconst = {
  66         { 0 },
  67 };
  68
  69 static u32 _omap4_idlest(u32 val)
  70 {
  71         val &= OMAP4_IDLEST_MASK;
  72         val >>= OMAP4_IDLEST_SHIFT;
  73
  74         return val;
  75 }
  76
  77 static bool _omap4_is_idle(u32 val)
  78 {
  79         val = _omap4_idlest(val);
  80
  81         return val == CLKCTRL_IDLEST_DISABLED;
  82 }
  83
  84 static bool _omap4_is_ready(u32 val)
  85 {
  86         val = _omap4_idlest(val);
  87
  88         return val == CLKCTRL_IDLEST_FUNCTIONAL ||
  89                val == CLKCTRL_IDLEST_INTERFACE_IDLE;
  90 }
  91
  92 static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
  93 {
  94         /*
  95          * There are two special cases where ktime_to_ns() can't be
  96          * used to track the timeouts. First one is during early boot
  97          * when the timers haven't been initialized yet. The second
  98          * one is during suspend-resume cycle while timekeeping is
  99          * being suspended / resumed. Clocksource for the system
 100          * can be from a timer that requires pm_runtime access, which
 101          * will eventually bring us here with timekeeping_suspended,
 102          * during both suspend entry and resume paths. This happens
 103          * at least on am43xx platform. Account for flakeyness
 104          * with udelay() by multiplying the timeout value by 2.
 105          */
 106         if (unlikely(_early_timeout || timekeeping_suspended)) {
 107                 if (time->cycles++ < timeout) {
 108                         udelay(1 * 2);
 109                         return false;
 110                 }
 111         } else {
 112                 if (!ktime_to_ns(time->start)) {
 113                         time->start = ktime_get();
 114                         return false;
 115                 }
 116
 117                 if (ktime_us_delta(ktime_get(), time->start) < timeout) {
 118                         cpu_relax();
 119                         return false;
 120                 }
 121         }
 122
 123         return true;
 124 }
 125
 126 static int __init _omap4_disable_early_timeout(void)
 127 {
 128         _early_timeout = false;
 129
 130         return 0;
 131 }
 132 arch_initcall(_omap4_disable_early_timeout);
 133
 134 static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
 135 {
 136         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 137         u32 val;
 138         int ret;
 139         union omap4_timeout timeout = { 0 };
 140
 141         if (clk->clkdm) {
 142                 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
 143                 if (ret) {
 144                         WARN(1,
 145                              "%s: could not enable %s's clockdomain %s: %d\n",
 146                              __func__, clk_hw_get_name(hw),
 147                              clk->clkdm_name, ret);
 148                         return ret;
 149                 }
 150         }
 151
 152         if (!clk->enable_bit)
 153                 return 0;
 154
 155         val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
 156
 157         val &= ~OMAP4_MODULEMODE_MASK;
 158         val |= clk->enable_bit;
 159
 160         ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
 161
 162         if (clk->flags & NO_IDLEST)
 163                 return 0;
 164
 165         /* Wait until module is enabled */
 166         while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
 167                 if (_omap4_is_timeout(&timeout, OMAP4_MAX_MODULE_READY_TIME)) {
 168                         pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
 169                         return -EBUSY;
 170                 }
 171         }
 172
 173         return 0;
 174 }
 175
 176 static void _omap4_clkctrl_clk_disable(struct clk_hw *hw)
 177 {
 178         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 179         u32 val;
 180         union omap4_timeout timeout = { 0 };
 181
 182         if (!clk->enable_bit)
 183                 goto exit;
 184
 185         val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
 186
 187         val &= ~OMAP4_MODULEMODE_MASK;
 188
 189         ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
 190
 191         if (clk->flags & NO_IDLEST)
 192                 goto exit;
 193
 194         /* Wait until module is disabled */
 195         while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
 196                 if (_omap4_is_timeout(&timeout,
 197                                       OMAP4_MAX_MODULE_DISABLE_TIME)) {
 198                         pr_err("%s: failed to disable\n", clk_hw_get_name(hw));
 199                         break;
 200                 }
 201         }
 202
 203 exit:
 204         if (clk->clkdm)
 205                 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
 206 }
 207
 208 static int _omap4_clkctrl_clk_is_enabled(struct clk_hw *hw)
 209 {
 210         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 211         u32 val;
 212
 213         val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
 214
 215         if (val & clk->enable_bit)
 216                 return 1;
 217
 218         return 0;
 219 }
 220
 221 static const struct clk_ops omap4_clkctrl_clk_ops = {
 222         .enable         = _omap4_clkctrl_clk_enable,
 223         .disable        = _omap4_clkctrl_clk_disable,
 224         .is_enabled     = _omap4_clkctrl_clk_is_enabled,
 225         .init           = omap2_init_clk_clkdm,
 226 };
 227
 228 static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
 229                                               void *data)
 230 {
 231         struct omap_clkctrl_provider *provider = data;
 232         struct omap_clkctrl_clk *entry;
 233         bool found = false;
 234
 235         if (clkspec->args_count != 2)
 236                 return ERR_PTR(-EINVAL);
 237
 238         pr_debug("%s: looking for %x:%x\n", __func__,
 239                  clkspec->args[0], clkspec->args[1]);
 240
 241         list_for_each_entry(entry, &provider->clocks, node) {
 242                 if (entry->reg_offset == clkspec->args[0] &&
 243                     entry->bit_offset == clkspec->args[1]) {
 244                         found = true;
 245                         break;
 246                 }
 247         }
 248
 249         if (!found)
 250                 return ERR_PTR(-EINVAL);
 251
 252         return entry->clk;
 253 }
 254
 255 static int __init
 256 _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
 257                          struct device_node *node, struct clk_hw *clk_hw,
 258                          u16 offset, u8 bit, const char * const *parents,
 259                          int num_parents, const struct clk_ops *ops)
 260 {
 261         struct clk_init_data init = { NULL };
 262         struct clk *clk;
 263         struct omap_clkctrl_clk *clkctrl_clk;
 264         int ret = 0;
 265
 266         init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d", node->parent->name,
 267                               node->name, offset, bit);
 268         clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
 269         if (!init.name || !clkctrl_clk) {
 270                 ret = -ENOMEM;
 271                 goto cleanup;
 272         }
 273
 274         clk_hw->init = &init;
 275         init.parent_names = parents;
 276         init.num_parents = num_parents;
 277         init.ops = ops;
 278         init.flags = CLK_IS_BASIC;
 279
 280         clk = ti_clk_register(NULL, clk_hw, init.name);
 281         if (IS_ERR_OR_NULL(clk)) {
 282                 ret = -EINVAL;
 283                 goto cleanup;
 284         }
 285
 286         clkctrl_clk->reg_offset = offset;
 287         clkctrl_clk->bit_offset = bit;
 288         clkctrl_clk->clk = clk_hw;
 289
 290         list_add(&clkctrl_clk->node, &provider->clocks);
 291
 292         return 0;
 293
 294 cleanup:
 295         kfree(init.name);
 296         kfree(clkctrl_clk);
 297         return ret;
 298 }
 299
 300 static void __init
 301 _ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
 302                        struct device_node *node, u16 offset,
 303                        const struct omap_clkctrl_bit_data *data,
 304                        void __iomem *reg)
 305 {
 306         struct clk_hw_omap *clk_hw;
 307
 308         clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
 309         if (!clk_hw)
 310                 return;
 311
 312         clk_hw->enable_bit = data->bit;
 313         clk_hw->enable_reg.ptr = reg;
 314
 315         if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset,
 316                                      data->bit, data->parents, 1,
 317                                      &omap_gate_clk_ops))
 318                 kfree(clk_hw);
 319 }
 320
 321 static void __init
 322 _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
 323                       struct device_node *node, u16 offset,
 324                       const struct omap_clkctrl_bit_data *data,
 325                       void __iomem *reg)
 326 {
 327         struct clk_omap_mux *mux;
 328         int num_parents = 0;
 329         const char * const *pname;
 330
 331         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 332         if (!mux)
 333                 return;
 334
 335         pname = data->parents;
 336         while (*pname) {
 337                 num_parents++;
 338                 pname++;
 339         }
 340
 341         mux->mask = num_parents;
 342         if (!(mux->flags & CLK_MUX_INDEX_ONE))
 343                 mux->mask--;
 344
 345         mux->mask = (1 << fls(mux->mask)) - 1;
 346
 347         mux->shift = data->bit;
 348         mux->reg.ptr = reg;
 349
 350         if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset,
 351                                      data->bit, data->parents, num_parents,
 352                                      &ti_clk_mux_ops))
 353                 kfree(mux);
 354 }
 355
 356 static void __init
 357 _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
 358                       struct device_node *node, u16 offset,
 359                       const struct omap_clkctrl_bit_data *data,
 360                       void __iomem *reg)
 361 {
 362         struct clk_omap_divider *div;
 363         const struct omap_clkctrl_div_data *div_data = data->data;
 364         u8 div_flags = 0;
 365
 366         div = kzalloc(sizeof(*div), GFP_KERNEL);
 367         if (!div)
 368                 return;
 369
 370         div->reg.ptr = reg;
 371         div->shift = data->bit;
 372         div->flags = div_data->flags;
 373
 374         if (div->flags & CLK_DIVIDER_POWER_OF_TWO)
 375                 div_flags |= CLKF_INDEX_POWER_OF_TWO;
 376
 377         if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,
 378                                       div_data->max_div, div_flags,
 379                                       &div->width, &div->table)) {
 380                 pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__,
 381                        node, offset, data->bit);
 382                 kfree(div);
 383                 return;
 384         }
 385
 386         if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset,
 387                                      data->bit, data->parents, 1,
 388                                      &ti_clk_divider_ops))
 389                 kfree(div);
 390 }
 391
 392 static void __init
 393 _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
 394                           struct device_node *node,
 395                           const struct omap_clkctrl_reg_data *data,
 396                           void __iomem *reg)
 397 {
 398         const struct omap_clkctrl_bit_data *bits = data->bit_data;
 399
 400         if (!bits)
 401                 return;
 402
 403         while (bits->bit) {
 404                 switch (bits->type) {
 405                 case TI_CLK_GATE:
 406                         _ti_clkctrl_setup_gate(provider, node, data->offset,
 407                                                bits, reg);
 408                         break;
 409
 410                 case TI_CLK_DIVIDER:
 411                         _ti_clkctrl_setup_div(provider, node, data->offset,
 412                                               bits, reg);
 413                         break;
 414
 415                 case TI_CLK_MUX:
 416                         _ti_clkctrl_setup_mux(provider, node, data->offset,
 417                                               bits, reg);
 418                         break;
 419
 420                 default:
 421                         pr_err("%s: bad subclk type: %d\n", __func__,
 422                                bits->type);
 423                         return;
 424                 }
 425                 bits++;
 426         }
 427 }
 428
 429 static void __init _clkctrl_add_provider(void *data,
 430                                          struct device_node *np)
 431 {
 432         of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data);
 433 }
 434
 435 static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
 436 {
 437         struct omap_clkctrl_provider *provider;
 438         const struct omap_clkctrl_data *data = default_clkctrl_data;
 439         const struct omap_clkctrl_reg_data *reg_data;
 440         struct clk_init_data init = { NULL };
 441         struct clk_hw_omap *hw;
 442         struct clk *clk;
 443         struct omap_clkctrl_clk *clkctrl_clk;
 444         const __be32 *addrp;
 445         u32 addr;
 446         int ret;
 447
 448         addrp = of_get_address(node, 0, NULL, NULL);
 449         addr = (u32)of_translate_address(node, addrp);
 450
 451 #ifdef CONFIG_ARCH_OMAP4
 452         if (of_machine_is_compatible("ti,omap4"))
 453                 data = omap4_clkctrl_data;
 454 #endif
 455 #ifdef CONFIG_SOC_OMAP5
 456         if (of_machine_is_compatible("ti,omap5"))
 457                 data = omap5_clkctrl_data;
 458 #endif
 459 #ifdef CONFIG_SOC_DRA7XX
 460         if (of_machine_is_compatible("ti,dra7"))
 461                 data = dra7_clkctrl_data;
 462 #endif
 463 #ifdef CONFIG_SOC_AM33XX
 464         if (of_machine_is_compatible("ti,am33xx"))
 465                 data = am3_clkctrl_data;
 466 #endif
 467 #ifdef CONFIG_SOC_AM43XX
 468         if (of_machine_is_compatible("ti,am4372"))
 469                 data = am4_clkctrl_data;
 470         if (of_machine_is_compatible("ti,am438x"))
 471                 data = am438x_clkctrl_data;
 472 #endif
 473 #ifdef CONFIG_SOC_TI81XX
 474         if (of_machine_is_compatible("ti,dm814"))
 475                 data = dm814_clkctrl_data;
 476
 477         if (of_machine_is_compatible("ti,dm816"))
 478                 data = dm816_clkctrl_data;
 479 #endif
 480
 481         while (data->addr) {
 482                 if (addr == data->addr)
 483                         break;
 484
 485                 data++;
 486         }
 487
 488         if (!data->addr) {
 489                 pr_err("%pOF not found from clkctrl data.\n", node);
 490                 return;
 491         }
 492
 493         provider = kzalloc(sizeof(*provider), GFP_KERNEL);
 494         if (!provider)
 495                 return;
 496
 497         provider->base = of_iomap(node, 0);
 498
 499         provider->clkdm_name = kmalloc(strlen(node->parent->name) + 3,
 500                                        GFP_KERNEL);
 501         if (!provider->clkdm_name) {
 502                 kfree(provider);
 503                 return;
 504         }
 505
 506         /*
 507          * Create default clkdm name, replace _cm from end of parent node
 508          * name with _clkdm
 509          */
 510         strcpy(provider->clkdm_name, node->parent->name);
 511         provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
 512         strcat(provider->clkdm_name, "clkdm");
 513
 514         INIT_LIST_HEAD(&provider->clocks);
 515
 516         /* Generate clocks */
 517         reg_data = data->regs;
 518
 519         while (reg_data->parent) {
 520                 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
 521                 if (!hw)
 522                         return;
 523
 524                 hw->enable_reg.ptr = provider->base + reg_data->offset;
 525
 526                 _ti_clkctrl_setup_subclks(provider, node, reg_data,
 527                                           hw->enable_reg.ptr);
 528
 529                 if (reg_data->flags & CLKF_SW_SUP)
 530                         hw->enable_bit = MODULEMODE_SWCTRL;
 531                 if (reg_data->flags & CLKF_HW_SUP)
 532                         hw->enable_bit = MODULEMODE_HWCTRL;
 533                 if (reg_data->flags & CLKF_NO_IDLEST)
 534                         hw->flags |= NO_IDLEST;
 535
 536                 if (reg_data->clkdm_name)
 537                         hw->clkdm_name = reg_data->clkdm_name;
 538                 else
 539                         hw->clkdm_name = provider->clkdm_name;
 540
 541                 init.parent_names = &reg_data->parent;
 542                 init.num_parents = 1;
 543                 init.flags = 0;
 544                 if (reg_data->flags & CLKF_SET_RATE_PARENT)
 545                         init.flags |= CLK_SET_RATE_PARENT;
 546                 init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d",
 547                                       node->parent->name, node->name,
 548                                       reg_data->offset, 0);
 549                 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
 550                 if (!init.name || !clkctrl_clk)
 551                         goto cleanup;
 552
 553                 init.ops = &omap4_clkctrl_clk_ops;
 554                 hw->hw.init = &init;
 555
 556                 clk = ti_clk_register(NULL, &hw->hw, init.name);
 557                 if (IS_ERR_OR_NULL(clk))
 558                         goto cleanup;
 559
 560                 clkctrl_clk->reg_offset = reg_data->offset;
 561                 clkctrl_clk->clk = &hw->hw;
 562
 563                 list_add(&clkctrl_clk->node, &provider->clocks);
 564
 565                 reg_data++;
 566         }
 567
 568         ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
 569         if (ret == -EPROBE_DEFER)
 570                 ti_clk_retry_init(node, provider, _clkctrl_add_provider);
 571
 572         return;
 573
 574 cleanup:
 575         kfree(hw);
 576         kfree(init.name);
 577         kfree(clkctrl_clk);
 578 }
 579 CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
 580                _ti_omap4_clkctrl_setup);