2 * DRA7 ATL (Audio Tracking Logic) clock driver
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Peter Ujfalusi <peter.ujfalusi@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/init.h>
19 #include <linux/clk.h>
20 #include <linux/clk-provider.h>
21 #include <linux/slab.h>
24 #include <linux/of_address.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/clk/ti.h>
31 #define DRA7_ATL_INSTANCES 4
33 #define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80))
34 #define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80))
35 #define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80))
36 #define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80))
37 #define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80))
38 #define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80))
39 #define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80))
41 #define DRA7_ATL_SWEN BIT(0)
42 #define DRA7_ATL_DIVIDER_MASK (0x1f)
43 #define DRA7_ATL_PCLKMUX BIT(0)
44 struct dra7_atl_clock_info;
46 struct dra7_atl_desc {
49 struct dra7_atl_clock_info *cinfo;
52 bool probed; /* the driver for the IP has been loaded */
53 bool valid; /* configured */
55 u32 bws; /* Baseband Word Select Mux */
56 u32 aws; /* Audio Word Select Mux */
57 u32 divider; /* Cached divider value */
60 struct dra7_atl_clock_info {
64 struct dra7_atl_desc *cdesc;
67 #define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw)
69 static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg,
72 __raw_writel(val, cinfo->iobase + reg);
75 static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg)
77 return __raw_readl(cinfo->iobase + reg);
80 static int atl_clk_enable(struct clk_hw *hw)
82 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
87 if (unlikely(!cdesc->valid))
88 dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n",
90 pm_runtime_get_sync(cdesc->cinfo->dev);
92 atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id),
94 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN);
97 cdesc->enabled = true;
102 static void atl_clk_disable(struct clk_hw *hw)
104 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
109 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0);
110 pm_runtime_put_sync(cdesc->cinfo->dev);
113 cdesc->enabled = false;
116 static int atl_clk_is_enabled(struct clk_hw *hw)
118 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
120 return cdesc->enabled;
123 static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
124 unsigned long parent_rate)
126 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
128 return parent_rate / cdesc->divider;
131 static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
132 unsigned long *parent_rate)
136 divider = (*parent_rate + rate / 2) / rate;
137 if (divider > DRA7_ATL_DIVIDER_MASK + 1)
138 divider = DRA7_ATL_DIVIDER_MASK + 1;
140 return *parent_rate / divider;
143 static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
144 unsigned long parent_rate)
146 struct dra7_atl_desc *cdesc;
152 cdesc = to_atl_desc(hw);
153 divider = ((parent_rate + rate / 2) / rate) - 1;
154 if (divider > DRA7_ATL_DIVIDER_MASK)
155 divider = DRA7_ATL_DIVIDER_MASK;
157 cdesc->divider = divider + 1;
162 static const struct clk_ops atl_clk_ops = {
163 .enable = atl_clk_enable,
164 .disable = atl_clk_disable,
165 .is_enabled = atl_clk_is_enabled,
166 .recalc_rate = atl_clk_recalc_rate,
167 .round_rate = atl_clk_round_rate,
168 .set_rate = atl_clk_set_rate,
171 static void __init of_dra7_atl_clock_setup(struct device_node *node)
173 struct dra7_atl_desc *clk_hw = NULL;
174 struct clk_init_data init = { NULL };
175 const char **parent_names = NULL;
179 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
181 pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
185 clk_hw->hw.init = &init;
187 name = ti_dt_clk_name(node);
189 init.ops = &atl_clk_ops;
190 init.flags = CLK_IGNORE_UNUSED;
191 init.num_parents = of_clk_get_parent_count(node);
193 if (init.num_parents != 1) {
194 pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__,
199 parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
204 parent_names[0] = of_clk_get_parent_name(node, 0);
206 init.parent_names = parent_names;
208 clk = of_ti_clk_register(node, &clk_hw->hw, name);
211 of_clk_add_provider(node, of_clk_src_simple_get, clk);
219 CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);
221 static int of_dra7_atl_clk_probe(struct platform_device *pdev)
223 struct device_node *node = pdev->dev.of_node;
224 struct dra7_atl_clock_info *cinfo;
231 cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
235 cinfo->iobase = of_iomap(node, 0);
236 cinfo->dev = &pdev->dev;
237 pm_runtime_enable(cinfo->dev);
239 pm_runtime_get_sync(cinfo->dev);
240 atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);
242 for (i = 0; i < DRA7_ATL_INSTANCES; i++) {
243 struct device_node *cfg_node;
245 struct dra7_atl_desc *cdesc;
246 struct of_phandle_args clkspec;
250 rc = of_parse_phandle_with_args(node, "ti,provided-clocks",
254 pr_err("%s: failed to lookup atl clock %d\n", __func__,
260 clk = of_clk_get_from_provider(&clkspec);
262 pr_err("%s: failed to get atl clock %d from provider\n",
268 cdesc = to_atl_desc(__clk_get_hw(clk));
269 cdesc->cinfo = cinfo;
272 /* Get configuration for the ATL instances */
273 snprintf(prop, sizeof(prop), "atl%u", i);
274 cfg_node = of_get_child_by_name(node, prop);
276 ret = of_property_read_u32(cfg_node, "bws",
278 ret |= of_property_read_u32(cfg_node, "aws",
282 atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i),
284 atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i),
287 of_node_put(cfg_node);
290 cdesc->probed = true;
292 * Enable the clock if it has been asked prior to loading the
296 atl_clk_enable(__clk_get_hw(clk));
300 pm_runtime_put_sync(cinfo->dev);
304 static const struct of_device_id of_dra7_atl_clk_match_tbl[] = {
305 { .compatible = "ti,dra7-atl", },
309 static struct platform_driver dra7_atl_clk_driver = {
312 .suppress_bind_attrs = true,
313 .of_match_table = of_dra7_atl_clk_match_tbl,
315 .probe = of_dra7_atl_clk_probe,
317 builtin_platform_driver(dra7_atl_clk_driver);