2 * OMAP3 Legacy clock data
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/clk/ti.h>
24 static struct ti_clk_fixed virt_12m_ck_data = {
25 .frequency = 12000000,
28 static struct ti_clk virt_12m_ck = {
29 .name = "virt_12m_ck",
31 .data = &virt_12m_ck_data,
34 static struct ti_clk_fixed virt_13m_ck_data = {
35 .frequency = 13000000,
38 static struct ti_clk virt_13m_ck = {
39 .name = "virt_13m_ck",
41 .data = &virt_13m_ck_data,
44 static struct ti_clk_fixed virt_19200000_ck_data = {
45 .frequency = 19200000,
48 static struct ti_clk virt_19200000_ck = {
49 .name = "virt_19200000_ck",
51 .data = &virt_19200000_ck_data,
54 static struct ti_clk_fixed virt_26000000_ck_data = {
55 .frequency = 26000000,
58 static struct ti_clk virt_26000000_ck = {
59 .name = "virt_26000000_ck",
61 .data = &virt_26000000_ck_data,
64 static struct ti_clk_fixed virt_38_4m_ck_data = {
65 .frequency = 38400000,
68 static struct ti_clk virt_38_4m_ck = {
69 .name = "virt_38_4m_ck",
71 .data = &virt_38_4m_ck_data,
74 static struct ti_clk_fixed virt_16_8m_ck_data = {
75 .frequency = 16800000,
78 static struct ti_clk virt_16_8m_ck = {
79 .name = "virt_16_8m_ck",
81 .data = &virt_16_8m_ck_data,
84 static const char *osc_sys_ck_parents[] = {
93 static struct ti_clk_mux osc_sys_ck_data = {
94 .num_parents = ARRAY_SIZE(osc_sys_ck_parents),
96 .module = TI_CLKM_PRM,
97 .parents = osc_sys_ck_parents,
100 static struct ti_clk osc_sys_ck = {
101 .name = "osc_sys_ck",
103 .data = &osc_sys_ck_data,
106 static struct ti_clk_divider sys_ck_data = {
107 .parent = "osc_sys_ck",
111 .module = TI_CLKM_PRM,
112 .flags = CLKF_INDEX_STARTS_AT_ONE,
115 static struct ti_clk sys_ck = {
117 .type = TI_CLK_DIVIDER,
118 .data = &sys_ck_data,
121 static const char *dpll3_ck_parents[] = {
126 static struct ti_clk_dpll dpll3_ck_data = {
127 .num_parents = ARRAY_SIZE(dpll3_ck_parents),
128 .control_reg = 0xd00,
130 .mult_div1_reg = 0xd40,
131 .autoidle_reg = 0xd30,
132 .module = TI_CLKM_CM,
133 .parents = dpll3_ck_parents,
135 .freqsel_mask = 0xf0,
138 .auto_recal_bit = 0x3,
142 .max_multiplier = 0x7ff,
144 .mult_mask = 0x7ff0000,
146 .autoidle_mask = 0x7,
149 static struct ti_clk dpll3_ck = {
151 .clkdm_name = "dpll3_clkdm",
153 .data = &dpll3_ck_data,
156 static struct ti_clk_divider dpll3_m2_ck_data = {
157 .parent = "dpll3_ck",
161 .module = TI_CLKM_CM,
162 .flags = CLKF_INDEX_STARTS_AT_ONE,
165 static struct ti_clk dpll3_m2_ck = {
166 .name = "dpll3_m2_ck",
167 .type = TI_CLK_DIVIDER,
168 .data = &dpll3_m2_ck_data,
171 static struct ti_clk_fixed_factor core_ck_data = {
172 .parent = "dpll3_m2_ck",
177 static struct ti_clk core_ck = {
179 .type = TI_CLK_FIXED_FACTOR,
180 .data = &core_ck_data,
183 static struct ti_clk_divider l3_ick_data = {
187 .module = TI_CLKM_CM,
188 .flags = CLKF_INDEX_STARTS_AT_ONE,
191 static struct ti_clk l3_ick = {
193 .type = TI_CLK_DIVIDER,
194 .data = &l3_ick_data,
197 static struct ti_clk_fixed_factor security_l3_ick_data = {
203 static struct ti_clk security_l3_ick = {
204 .name = "security_l3_ick",
205 .type = TI_CLK_FIXED_FACTOR,
206 .data = &security_l3_ick_data,
209 static struct ti_clk_fixed_factor wkup_l4_ick_data = {
215 static struct ti_clk wkup_l4_ick = {
216 .name = "wkup_l4_ick",
217 .type = TI_CLK_FIXED_FACTOR,
218 .data = &wkup_l4_ick_data,
221 static struct ti_clk_gate usim_ick_data = {
222 .parent = "wkup_l4_ick",
225 .module = TI_CLKM_CM,
226 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
229 static struct ti_clk usim_ick = {
231 .clkdm_name = "wkup_clkdm",
233 .data = &usim_ick_data,
236 static struct ti_clk_gate dss2_alwon_fck_data = {
240 .module = TI_CLKM_CM,
243 static struct ti_clk dss2_alwon_fck = {
244 .name = "dss2_alwon_fck",
245 .clkdm_name = "dss_clkdm",
247 .data = &dss2_alwon_fck_data,
250 static struct ti_clk_divider l4_ick_data = {
255 .module = TI_CLKM_CM,
256 .flags = CLKF_INDEX_STARTS_AT_ONE,
259 static struct ti_clk l4_ick = {
261 .type = TI_CLK_DIVIDER,
262 .data = &l4_ick_data,
265 static struct ti_clk_fixed_factor core_l4_ick_data = {
271 static struct ti_clk core_l4_ick = {
272 .name = "core_l4_ick",
273 .type = TI_CLK_FIXED_FACTOR,
274 .data = &core_l4_ick_data,
277 static struct ti_clk_gate mmchs2_ick_data = {
278 .parent = "core_l4_ick",
281 .module = TI_CLKM_CM,
282 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
285 static struct ti_clk mmchs2_ick = {
286 .name = "mmchs2_ick",
287 .clkdm_name = "core_l4_clkdm",
289 .data = &mmchs2_ick_data,
292 static const char *dpll4_ck_parents[] = {
297 static struct ti_clk_dpll dpll4_ck_data = {
298 .num_parents = ARRAY_SIZE(dpll4_ck_parents),
299 .control_reg = 0xd00,
301 .mult_div1_reg = 0xd44,
302 .autoidle_reg = 0xd30,
303 .module = TI_CLKM_CM,
304 .parents = dpll4_ck_parents,
306 .freqsel_mask = 0xf00000,
310 .auto_recal_bit = 0x13,
314 .max_multiplier = 0x7ff,
315 .enable_mask = 0x70000,
316 .mult_mask = 0x7ff00,
318 .autoidle_mask = 0x38,
321 static struct ti_clk dpll4_ck = {
323 .clkdm_name = "dpll4_clkdm",
325 .data = &dpll4_ck_data,
328 static struct ti_clk_divider dpll4_m2_ck_data = {
329 .parent = "dpll4_ck",
332 .module = TI_CLKM_CM,
333 .flags = CLKF_INDEX_STARTS_AT_ONE,
336 static struct ti_clk dpll4_m2_ck = {
337 .name = "dpll4_m2_ck",
338 .type = TI_CLK_DIVIDER,
339 .data = &dpll4_m2_ck_data,
342 static struct ti_clk_fixed_factor dpll4_m2x2_mul_ck_data = {
343 .parent = "dpll4_m2_ck",
348 static struct ti_clk dpll4_m2x2_mul_ck = {
349 .name = "dpll4_m2x2_mul_ck",
350 .type = TI_CLK_FIXED_FACTOR,
351 .data = &dpll4_m2x2_mul_ck_data,
354 static struct ti_clk_gate dpll4_m2x2_ck_data = {
355 .parent = "dpll4_m2x2_mul_ck",
358 .module = TI_CLKM_CM,
359 .flags = CLKF_SET_BIT_TO_DISABLE,
362 static struct ti_clk dpll4_m2x2_ck = {
363 .name = "dpll4_m2x2_ck",
365 .data = &dpll4_m2x2_ck_data,
368 static struct ti_clk_fixed_factor omap_96m_alwon_fck_data = {
369 .parent = "dpll4_m2x2_ck",
374 static struct ti_clk omap_96m_alwon_fck = {
375 .name = "omap_96m_alwon_fck",
376 .type = TI_CLK_FIXED_FACTOR,
377 .data = &omap_96m_alwon_fck_data,
380 static struct ti_clk_fixed_factor cm_96m_fck_data = {
381 .parent = "omap_96m_alwon_fck",
386 static struct ti_clk cm_96m_fck = {
387 .name = "cm_96m_fck",
388 .type = TI_CLK_FIXED_FACTOR,
389 .data = &cm_96m_fck_data,
392 static const char *omap_96m_fck_parents[] = {
397 static struct ti_clk_mux omap_96m_fck_data = {
399 .num_parents = ARRAY_SIZE(omap_96m_fck_parents),
401 .module = TI_CLKM_CM,
402 .parents = omap_96m_fck_parents,
405 static struct ti_clk omap_96m_fck = {
406 .name = "omap_96m_fck",
408 .data = &omap_96m_fck_data,
411 static struct ti_clk_fixed_factor core_96m_fck_data = {
412 .parent = "omap_96m_fck",
417 static struct ti_clk core_96m_fck = {
418 .name = "core_96m_fck",
419 .type = TI_CLK_FIXED_FACTOR,
420 .data = &core_96m_fck_data,
423 static struct ti_clk_gate mspro_fck_data = {
424 .parent = "core_96m_fck",
427 .module = TI_CLKM_CM,
431 static struct ti_clk mspro_fck = {
433 .clkdm_name = "core_l4_clkdm",
435 .data = &mspro_fck_data,
438 static struct ti_clk_gate dss_ick_3430es2_data = {
442 .module = TI_CLKM_CM,
443 .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
446 static struct ti_clk dss_ick_3430es2 = {
448 .clkdm_name = "dss_clkdm",
450 .data = &dss_ick_3430es2_data,
453 static struct ti_clk_gate uart4_ick_am35xx_data = {
454 .parent = "core_l4_ick",
457 .module = TI_CLKM_CM,
458 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
461 static struct ti_clk uart4_ick_am35xx = {
462 .name = "uart4_ick_am35xx",
463 .clkdm_name = "core_l4_clkdm",
465 .data = &uart4_ick_am35xx_data,
468 static struct ti_clk_fixed_factor security_l4_ick2_data = {
474 static struct ti_clk security_l4_ick2 = {
475 .name = "security_l4_ick2",
476 .type = TI_CLK_FIXED_FACTOR,
477 .data = &security_l4_ick2_data,
480 static struct ti_clk_gate aes1_ick_data = {
481 .parent = "security_l4_ick2",
484 .module = TI_CLKM_CM,
485 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
488 static struct ti_clk aes1_ick = {
491 .data = &aes1_ick_data,
494 static const char *dpll5_ck_parents[] = {
499 static struct ti_clk_dpll dpll5_ck_data = {
500 .num_parents = ARRAY_SIZE(dpll5_ck_parents),
501 .control_reg = 0xd04,
503 .mult_div1_reg = 0xd4c,
504 .autoidle_reg = 0xd34,
505 .module = TI_CLKM_CM,
506 .parents = dpll5_ck_parents,
507 .freqsel_mask = 0xf0,
511 .auto_recal_bit = 0x3,
514 .recal_en_bit = 0x19,
515 .max_multiplier = 0x7ff,
517 .mult_mask = 0x7ff00,
518 .recal_st_bit = 0x19,
519 .autoidle_mask = 0x7,
522 static struct ti_clk dpll5_ck = {
524 .clkdm_name = "dpll5_clkdm",
526 .data = &dpll5_ck_data,
529 static struct ti_clk_divider dpll5_m2_ck_data = {
530 .parent = "dpll5_ck",
533 .module = TI_CLKM_CM,
534 .flags = CLKF_INDEX_STARTS_AT_ONE,
537 static struct ti_clk dpll5_m2_ck = {
538 .name = "dpll5_m2_ck",
539 .type = TI_CLK_DIVIDER,
540 .data = &dpll5_m2_ck_data,
543 static struct ti_clk_gate usbhost_120m_fck_data = {
544 .parent = "dpll5_m2_ck",
547 .module = TI_CLKM_CM,
550 static struct ti_clk usbhost_120m_fck = {
551 .name = "usbhost_120m_fck",
552 .clkdm_name = "usbhost_clkdm",
554 .data = &usbhost_120m_fck_data,
557 static struct ti_clk_fixed_factor cm_96m_d2_fck_data = {
558 .parent = "cm_96m_fck",
563 static struct ti_clk cm_96m_d2_fck = {
564 .name = "cm_96m_d2_fck",
565 .type = TI_CLK_FIXED_FACTOR,
566 .data = &cm_96m_d2_fck_data,
569 static struct ti_clk_fixed sys_altclk_data = {
573 static struct ti_clk sys_altclk = {
574 .name = "sys_altclk",
575 .type = TI_CLK_FIXED,
576 .data = &sys_altclk_data,
579 static const char *omap_48m_fck_parents[] = {
584 static struct ti_clk_mux omap_48m_fck_data = {
586 .num_parents = ARRAY_SIZE(omap_48m_fck_parents),
588 .module = TI_CLKM_CM,
589 .parents = omap_48m_fck_parents,
592 static struct ti_clk omap_48m_fck = {
593 .name = "omap_48m_fck",
595 .data = &omap_48m_fck_data,
598 static struct ti_clk_fixed_factor core_48m_fck_data = {
599 .parent = "omap_48m_fck",
604 static struct ti_clk core_48m_fck = {
605 .name = "core_48m_fck",
606 .type = TI_CLK_FIXED_FACTOR,
607 .data = &core_48m_fck_data,
610 static struct ti_clk_fixed mcbsp_clks_data = {
614 static struct ti_clk mcbsp_clks = {
615 .name = "mcbsp_clks",
616 .type = TI_CLK_FIXED,
617 .data = &mcbsp_clks_data,
620 static struct ti_clk_gate mcbsp2_gate_fck_data = {
621 .parent = "mcbsp_clks",
624 .module = TI_CLKM_CM,
627 static struct ti_clk_fixed_factor per_96m_fck_data = {
628 .parent = "omap_96m_alwon_fck",
633 static struct ti_clk per_96m_fck = {
634 .name = "per_96m_fck",
635 .type = TI_CLK_FIXED_FACTOR,
636 .data = &per_96m_fck_data,
639 static const char *mcbsp2_mux_fck_parents[] = {
644 static struct ti_clk_mux mcbsp2_mux_fck_data = {
646 .num_parents = ARRAY_SIZE(mcbsp2_mux_fck_parents),
648 .module = TI_CLKM_SCRM,
649 .parents = mcbsp2_mux_fck_parents,
652 static struct ti_clk_composite mcbsp2_fck_data = {
653 .mux = &mcbsp2_mux_fck_data,
654 .gate = &mcbsp2_gate_fck_data,
657 static struct ti_clk mcbsp2_fck = {
658 .name = "mcbsp2_fck",
659 .type = TI_CLK_COMPOSITE,
660 .data = &mcbsp2_fck_data,
663 static struct ti_clk_fixed_factor dpll3_m2x2_ck_data = {
664 .parent = "dpll3_m2_ck",
669 static struct ti_clk dpll3_m2x2_ck = {
670 .name = "dpll3_m2x2_ck",
671 .type = TI_CLK_FIXED_FACTOR,
672 .data = &dpll3_m2x2_ck_data,
675 static struct ti_clk_fixed_factor corex2_fck_data = {
676 .parent = "dpll3_m2x2_ck",
681 static struct ti_clk corex2_fck = {
682 .name = "corex2_fck",
683 .type = TI_CLK_FIXED_FACTOR,
684 .data = &corex2_fck_data,
687 static struct ti_clk_gate ssi_ssr_gate_fck_3430es1_data = {
688 .parent = "corex2_fck",
691 .module = TI_CLKM_CM,
692 .flags = CLKF_NO_WAIT,
695 static int ssi_ssr_div_fck_3430es1_divs[] = {
707 static struct ti_clk_divider ssi_ssr_div_fck_3430es1_data = {
708 .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es1_divs),
709 .parent = "corex2_fck",
711 .dividers = ssi_ssr_div_fck_3430es1_divs,
713 .module = TI_CLKM_CM,
716 static struct ti_clk_composite ssi_ssr_fck_3430es1_data = {
717 .gate = &ssi_ssr_gate_fck_3430es1_data,
718 .divider = &ssi_ssr_div_fck_3430es1_data,
721 static struct ti_clk ssi_ssr_fck_3430es1 = {
722 .name = "ssi_ssr_fck",
723 .type = TI_CLK_COMPOSITE,
724 .data = &ssi_ssr_fck_3430es1_data,
727 static struct ti_clk_fixed_factor ssi_sst_fck_3430es1_data = {
728 .parent = "ssi_ssr_fck",
733 static struct ti_clk ssi_sst_fck_3430es1 = {
734 .name = "ssi_sst_fck",
735 .type = TI_CLK_FIXED_FACTOR,
736 .data = &ssi_sst_fck_3430es1_data,
739 static struct ti_clk_fixed omap_32k_fck_data = {
743 static struct ti_clk omap_32k_fck = {
744 .name = "omap_32k_fck",
745 .type = TI_CLK_FIXED,
746 .data = &omap_32k_fck_data,
749 static struct ti_clk_fixed_factor per_32k_alwon_fck_data = {
750 .parent = "omap_32k_fck",
755 static struct ti_clk per_32k_alwon_fck = {
756 .name = "per_32k_alwon_fck",
757 .type = TI_CLK_FIXED_FACTOR,
758 .data = &per_32k_alwon_fck_data,
761 static struct ti_clk_gate gpio5_dbck_data = {
762 .parent = "per_32k_alwon_fck",
765 .module = TI_CLKM_CM,
768 static struct ti_clk gpio5_dbck = {
769 .name = "gpio5_dbck",
770 .clkdm_name = "per_clkdm",
772 .data = &gpio5_dbck_data,
775 static struct ti_clk_gate gpt1_ick_data = {
776 .parent = "wkup_l4_ick",
779 .module = TI_CLKM_CM,
780 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
783 static struct ti_clk gpt1_ick = {
785 .clkdm_name = "wkup_clkdm",
787 .data = &gpt1_ick_data,
790 static struct ti_clk_gate mcspi3_fck_data = {
791 .parent = "core_48m_fck",
794 .module = TI_CLKM_CM,
798 static struct ti_clk mcspi3_fck = {
799 .name = "mcspi3_fck",
800 .clkdm_name = "core_l4_clkdm",
802 .data = &mcspi3_fck_data,
805 static struct ti_clk_gate gpt2_gate_fck_data = {
809 .module = TI_CLKM_CM,
812 static const char *gpt2_mux_fck_parents[] = {
817 static struct ti_clk_mux gpt2_mux_fck_data = {
818 .num_parents = ARRAY_SIZE(gpt2_mux_fck_parents),
820 .module = TI_CLKM_CM,
821 .parents = gpt2_mux_fck_parents,
824 static struct ti_clk_composite gpt2_fck_data = {
825 .mux = &gpt2_mux_fck_data,
826 .gate = &gpt2_gate_fck_data,
829 static struct ti_clk gpt2_fck = {
831 .type = TI_CLK_COMPOSITE,
832 .data = &gpt2_fck_data,
835 static struct ti_clk_gate gpt10_ick_data = {
836 .parent = "core_l4_ick",
839 .module = TI_CLKM_CM,
840 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
843 static struct ti_clk gpt10_ick = {
845 .clkdm_name = "core_l4_clkdm",
847 .data = &gpt10_ick_data,
850 static struct ti_clk_gate uart2_fck_data = {
851 .parent = "core_48m_fck",
854 .module = TI_CLKM_CM,
858 static struct ti_clk uart2_fck = {
860 .clkdm_name = "core_l4_clkdm",
862 .data = &uart2_fck_data,
865 static struct ti_clk_fixed_factor sr_l4_ick_data = {
871 static struct ti_clk sr_l4_ick = {
873 .type = TI_CLK_FIXED_FACTOR,
874 .data = &sr_l4_ick_data,
877 static struct ti_clk_fixed_factor omap_96m_d8_fck_data = {
878 .parent = "omap_96m_fck",
883 static struct ti_clk omap_96m_d8_fck = {
884 .name = "omap_96m_d8_fck",
885 .type = TI_CLK_FIXED_FACTOR,
886 .data = &omap_96m_d8_fck_data,
889 static struct ti_clk_divider dpll4_m5_ck_data = {
890 .parent = "dpll4_ck",
893 .module = TI_CLKM_CM,
894 .flags = CLKF_INDEX_STARTS_AT_ONE,
897 static struct ti_clk dpll4_m5_ck = {
898 .name = "dpll4_m5_ck",
899 .type = TI_CLK_DIVIDER,
900 .data = &dpll4_m5_ck_data,
903 static struct ti_clk_fixed_factor dpll4_m5x2_mul_ck_data = {
904 .parent = "dpll4_m5_ck",
907 .flags = CLKF_SET_RATE_PARENT,
910 static struct ti_clk dpll4_m5x2_mul_ck = {
911 .name = "dpll4_m5x2_mul_ck",
912 .type = TI_CLK_FIXED_FACTOR,
913 .data = &dpll4_m5x2_mul_ck_data,
916 static struct ti_clk_gate dpll4_m5x2_ck_data = {
917 .parent = "dpll4_m5x2_mul_ck",
920 .module = TI_CLKM_CM,
921 .flags = CLKF_SET_BIT_TO_DISABLE,
924 static struct ti_clk dpll4_m5x2_ck = {
925 .name = "dpll4_m5x2_ck",
927 .data = &dpll4_m5x2_ck_data,
930 static struct ti_clk_gate cam_mclk_data = {
931 .parent = "dpll4_m5x2_ck",
934 .module = TI_CLKM_CM,
935 .flags = CLKF_SET_RATE_PARENT,
938 static struct ti_clk cam_mclk = {
941 .data = &cam_mclk_data,
944 static struct ti_clk_gate mcbsp3_gate_fck_data = {
945 .parent = "mcbsp_clks",
948 .module = TI_CLKM_CM,
951 static const char *mcbsp3_mux_fck_parents[] = {
956 static struct ti_clk_mux mcbsp3_mux_fck_data = {
957 .num_parents = ARRAY_SIZE(mcbsp3_mux_fck_parents),
959 .module = TI_CLKM_SCRM,
960 .parents = mcbsp3_mux_fck_parents,
963 static struct ti_clk_composite mcbsp3_fck_data = {
964 .mux = &mcbsp3_mux_fck_data,
965 .gate = &mcbsp3_gate_fck_data,
968 static struct ti_clk mcbsp3_fck = {
969 .name = "mcbsp3_fck",
970 .type = TI_CLK_COMPOSITE,
971 .data = &mcbsp3_fck_data,
974 static struct ti_clk_gate csi2_96m_fck_data = {
975 .parent = "core_96m_fck",
978 .module = TI_CLKM_CM,
981 static struct ti_clk csi2_96m_fck = {
982 .name = "csi2_96m_fck",
983 .clkdm_name = "cam_clkdm",
985 .data = &csi2_96m_fck_data,
988 static struct ti_clk_gate gpt9_gate_fck_data = {
992 .module = TI_CLKM_CM,
995 static const char *gpt9_mux_fck_parents[] = {
1000 static struct ti_clk_mux gpt9_mux_fck_data = {
1002 .num_parents = ARRAY_SIZE(gpt9_mux_fck_parents),
1004 .module = TI_CLKM_CM,
1005 .parents = gpt9_mux_fck_parents,
1008 static struct ti_clk_composite gpt9_fck_data = {
1009 .mux = &gpt9_mux_fck_data,
1010 .gate = &gpt9_gate_fck_data,
1013 static struct ti_clk gpt9_fck = {
1015 .type = TI_CLK_COMPOSITE,
1016 .data = &gpt9_fck_data,
1019 static struct ti_clk_divider dpll3_m3_ck_data = {
1020 .parent = "dpll3_ck",
1024 .module = TI_CLKM_CM,
1025 .flags = CLKF_INDEX_STARTS_AT_ONE,
1028 static struct ti_clk dpll3_m3_ck = {
1029 .name = "dpll3_m3_ck",
1030 .type = TI_CLK_DIVIDER,
1031 .data = &dpll3_m3_ck_data,
1034 static struct ti_clk_fixed_factor dpll3_m3x2_mul_ck_data = {
1035 .parent = "dpll3_m3_ck",
1040 static struct ti_clk dpll3_m3x2_mul_ck = {
1041 .name = "dpll3_m3x2_mul_ck",
1042 .type = TI_CLK_FIXED_FACTOR,
1043 .data = &dpll3_m3x2_mul_ck_data,
1046 static struct ti_clk_gate sr2_fck_data = {
1050 .module = TI_CLKM_CM,
1054 static struct ti_clk sr2_fck = {
1056 .clkdm_name = "wkup_clkdm",
1057 .type = TI_CLK_GATE,
1058 .data = &sr2_fck_data,
1061 static struct ti_clk_fixed pclk_ck_data = {
1062 .frequency = 27000000,
1065 static struct ti_clk pclk_ck = {
1067 .type = TI_CLK_FIXED,
1068 .data = &pclk_ck_data,
1071 static struct ti_clk_gate wdt2_ick_data = {
1072 .parent = "wkup_l4_ick",
1075 .module = TI_CLKM_CM,
1076 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1079 static struct ti_clk wdt2_ick = {
1081 .clkdm_name = "wkup_clkdm",
1082 .type = TI_CLK_GATE,
1083 .data = &wdt2_ick_data,
1086 static struct ti_clk_fixed_factor core_l3_ick_data = {
1092 static struct ti_clk core_l3_ick = {
1093 .name = "core_l3_ick",
1094 .type = TI_CLK_FIXED_FACTOR,
1095 .data = &core_l3_ick_data,
1098 static struct ti_clk_gate mcspi4_fck_data = {
1099 .parent = "core_48m_fck",
1102 .module = TI_CLKM_CM,
1106 static struct ti_clk mcspi4_fck = {
1107 .name = "mcspi4_fck",
1108 .clkdm_name = "core_l4_clkdm",
1109 .type = TI_CLK_GATE,
1110 .data = &mcspi4_fck_data,
1113 static struct ti_clk_fixed_factor per_48m_fck_data = {
1114 .parent = "omap_48m_fck",
1119 static struct ti_clk per_48m_fck = {
1120 .name = "per_48m_fck",
1121 .type = TI_CLK_FIXED_FACTOR,
1122 .data = &per_48m_fck_data,
1125 static struct ti_clk_gate uart4_fck_data = {
1126 .parent = "per_48m_fck",
1129 .module = TI_CLKM_CM,
1133 static struct ti_clk uart4_fck = {
1134 .name = "uart4_fck",
1135 .clkdm_name = "per_clkdm",
1136 .type = TI_CLK_GATE,
1137 .data = &uart4_fck_data,
1140 static struct ti_clk_fixed_factor omap_96m_d10_fck_data = {
1141 .parent = "omap_96m_fck",
1146 static struct ti_clk omap_96m_d10_fck = {
1147 .name = "omap_96m_d10_fck",
1148 .type = TI_CLK_FIXED_FACTOR,
1149 .data = &omap_96m_d10_fck_data,
1152 static struct ti_clk_gate usim_gate_fck_data = {
1153 .parent = "omap_96m_fck",
1156 .module = TI_CLKM_CM,
1159 static struct ti_clk_fixed_factor per_l4_ick_data = {
1165 static struct ti_clk per_l4_ick = {
1166 .name = "per_l4_ick",
1167 .type = TI_CLK_FIXED_FACTOR,
1168 .data = &per_l4_ick_data,
1171 static struct ti_clk_gate gpt5_ick_data = {
1172 .parent = "per_l4_ick",
1175 .module = TI_CLKM_CM,
1176 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1179 static struct ti_clk gpt5_ick = {
1181 .clkdm_name = "per_clkdm",
1182 .type = TI_CLK_GATE,
1183 .data = &gpt5_ick_data,
1186 static struct ti_clk_gate mcspi2_ick_data = {
1187 .parent = "core_l4_ick",
1190 .module = TI_CLKM_CM,
1191 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1194 static struct ti_clk mcspi2_ick = {
1195 .name = "mcspi2_ick",
1196 .clkdm_name = "core_l4_clkdm",
1197 .type = TI_CLK_GATE,
1198 .data = &mcspi2_ick_data,
1201 static struct ti_clk_fixed_factor ssi_l4_ick_data = {
1207 static struct ti_clk ssi_l4_ick = {
1208 .name = "ssi_l4_ick",
1209 .clkdm_name = "core_l4_clkdm",
1210 .type = TI_CLK_FIXED_FACTOR,
1211 .data = &ssi_l4_ick_data,
1214 static struct ti_clk_gate ssi_ick_3430es1_data = {
1215 .parent = "ssi_l4_ick",
1218 .module = TI_CLKM_CM,
1219 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1222 static struct ti_clk ssi_ick_3430es1 = {
1224 .clkdm_name = "core_l4_clkdm",
1225 .type = TI_CLK_GATE,
1226 .data = &ssi_ick_3430es1_data,
1229 static struct ti_clk_gate i2c2_fck_data = {
1230 .parent = "core_96m_fck",
1233 .module = TI_CLKM_CM,
1237 static struct ti_clk i2c2_fck = {
1239 .clkdm_name = "core_l4_clkdm",
1240 .type = TI_CLK_GATE,
1241 .data = &i2c2_fck_data,
1244 static struct ti_clk_divider dpll1_fck_data = {
1245 .parent = "core_ck",
1249 .module = TI_CLKM_CM,
1250 .flags = CLKF_INDEX_STARTS_AT_ONE,
1253 static struct ti_clk dpll1_fck = {
1254 .name = "dpll1_fck",
1255 .type = TI_CLK_DIVIDER,
1256 .data = &dpll1_fck_data,
1259 static const char *dpll1_ck_parents[] = {
1264 static struct ti_clk_dpll dpll1_ck_data = {
1265 .num_parents = ARRAY_SIZE(dpll1_ck_parents),
1266 .control_reg = 0x904,
1267 .idlest_reg = 0x924,
1268 .mult_div1_reg = 0x940,
1269 .autoidle_reg = 0x934,
1270 .module = TI_CLKM_CM,
1271 .parents = dpll1_ck_parents,
1272 .freqsel_mask = 0xf0,
1276 .auto_recal_bit = 0x3,
1277 .max_divider = 0x80,
1279 .recal_en_bit = 0x7,
1280 .max_multiplier = 0x7ff,
1282 .mult_mask = 0x7ff00,
1283 .recal_st_bit = 0x7,
1284 .autoidle_mask = 0x7,
1287 static struct ti_clk dpll1_ck = {
1289 .clkdm_name = "dpll1_clkdm",
1290 .type = TI_CLK_DPLL,
1291 .data = &dpll1_ck_data,
1294 static struct ti_clk_fixed secure_32k_fck_data = {
1298 static struct ti_clk secure_32k_fck = {
1299 .name = "secure_32k_fck",
1300 .type = TI_CLK_FIXED,
1301 .data = &secure_32k_fck_data,
1304 static struct ti_clk_gate gpio5_ick_data = {
1305 .parent = "per_l4_ick",
1308 .module = TI_CLKM_CM,
1309 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1312 static struct ti_clk gpio5_ick = {
1313 .name = "gpio5_ick",
1314 .clkdm_name = "per_clkdm",
1315 .type = TI_CLK_GATE,
1316 .data = &gpio5_ick_data,
1319 static struct ti_clk_divider dpll4_m4_ck_data = {
1320 .parent = "dpll4_ck",
1323 .module = TI_CLKM_CM,
1324 .flags = CLKF_INDEX_STARTS_AT_ONE,
1327 static struct ti_clk dpll4_m4_ck = {
1328 .name = "dpll4_m4_ck",
1329 .type = TI_CLK_DIVIDER,
1330 .data = &dpll4_m4_ck_data,
1333 static struct ti_clk_fixed_factor dpll4_m4x2_mul_ck_data = {
1334 .parent = "dpll4_m4_ck",
1337 .flags = CLKF_SET_RATE_PARENT,
1340 static struct ti_clk dpll4_m4x2_mul_ck = {
1341 .name = "dpll4_m4x2_mul_ck",
1342 .type = TI_CLK_FIXED_FACTOR,
1343 .data = &dpll4_m4x2_mul_ck_data,
1346 static struct ti_clk_gate dpll4_m4x2_ck_data = {
1347 .parent = "dpll4_m4x2_mul_ck",
1350 .module = TI_CLKM_CM,
1351 .flags = CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
1354 static struct ti_clk dpll4_m4x2_ck = {
1355 .name = "dpll4_m4x2_ck",
1356 .type = TI_CLK_GATE,
1357 .data = &dpll4_m4x2_ck_data,
1360 static struct ti_clk_gate dss1_alwon_fck_3430es2_data = {
1361 .parent = "dpll4_m4x2_ck",
1364 .module = TI_CLKM_CM,
1365 .flags = CLKF_DSS | CLKF_SET_RATE_PARENT,
1368 static struct ti_clk dss1_alwon_fck_3430es2 = {
1369 .name = "dss1_alwon_fck",
1370 .clkdm_name = "dss_clkdm",
1371 .type = TI_CLK_GATE,
1372 .data = &dss1_alwon_fck_3430es2_data,
1375 static struct ti_clk_gate uart3_ick_data = {
1376 .parent = "per_l4_ick",
1379 .module = TI_CLKM_CM,
1380 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1383 static struct ti_clk uart3_ick = {
1384 .name = "uart3_ick",
1385 .clkdm_name = "per_clkdm",
1386 .type = TI_CLK_GATE,
1387 .data = &uart3_ick_data,
1390 static struct ti_clk_divider dpll4_m3_ck_data = {
1391 .parent = "dpll4_ck",
1395 .module = TI_CLKM_CM,
1396 .flags = CLKF_INDEX_STARTS_AT_ONE,
1399 static struct ti_clk dpll4_m3_ck = {
1400 .name = "dpll4_m3_ck",
1401 .type = TI_CLK_DIVIDER,
1402 .data = &dpll4_m3_ck_data,
1405 static struct ti_clk_gate mcbsp3_ick_data = {
1406 .parent = "per_l4_ick",
1409 .module = TI_CLKM_CM,
1410 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1413 static struct ti_clk mcbsp3_ick = {
1414 .name = "mcbsp3_ick",
1415 .clkdm_name = "per_clkdm",
1416 .type = TI_CLK_GATE,
1417 .data = &mcbsp3_ick_data,
1420 static struct ti_clk_gate gpio3_dbck_data = {
1421 .parent = "per_32k_alwon_fck",
1424 .module = TI_CLKM_CM,
1427 static struct ti_clk gpio3_dbck = {
1428 .name = "gpio3_dbck",
1429 .clkdm_name = "per_clkdm",
1430 .type = TI_CLK_GATE,
1431 .data = &gpio3_dbck_data,
1434 static struct ti_clk_gate fac_ick_data = {
1435 .parent = "core_l4_ick",
1438 .module = TI_CLKM_CM,
1439 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1442 static struct ti_clk fac_ick = {
1444 .clkdm_name = "core_l4_clkdm",
1445 .type = TI_CLK_GATE,
1446 .data = &fac_ick_data,
1449 static struct ti_clk_gate clkout2_src_gate_ck_data = {
1450 .parent = "core_ck",
1453 .module = TI_CLKM_CM,
1454 .flags = CLKF_NO_WAIT,
1457 static struct ti_clk_fixed_factor dpll4_m3x2_mul_ck_data = {
1458 .parent = "dpll4_m3_ck",
1463 static struct ti_clk dpll4_m3x2_mul_ck = {
1464 .name = "dpll4_m3x2_mul_ck",
1465 .type = TI_CLK_FIXED_FACTOR,
1466 .data = &dpll4_m3x2_mul_ck_data,
1469 static struct ti_clk_gate dpll4_m3x2_ck_data = {
1470 .parent = "dpll4_m3x2_mul_ck",
1473 .module = TI_CLKM_CM,
1474 .flags = CLKF_SET_BIT_TO_DISABLE,
1477 static struct ti_clk dpll4_m3x2_ck = {
1478 .name = "dpll4_m3x2_ck",
1479 .type = TI_CLK_GATE,
1480 .data = &dpll4_m3x2_ck_data,
1483 static const char *omap_54m_fck_parents[] = {
1488 static struct ti_clk_mux omap_54m_fck_data = {
1490 .num_parents = ARRAY_SIZE(omap_54m_fck_parents),
1492 .module = TI_CLKM_CM,
1493 .parents = omap_54m_fck_parents,
1496 static struct ti_clk omap_54m_fck = {
1497 .name = "omap_54m_fck",
1499 .data = &omap_54m_fck_data,
1502 static const char *clkout2_src_mux_ck_parents[] = {
1509 static struct ti_clk_mux clkout2_src_mux_ck_data = {
1510 .num_parents = ARRAY_SIZE(clkout2_src_mux_ck_parents),
1512 .module = TI_CLKM_CM,
1513 .parents = clkout2_src_mux_ck_parents,
1516 static struct ti_clk_composite clkout2_src_ck_data = {
1517 .mux = &clkout2_src_mux_ck_data,
1518 .gate = &clkout2_src_gate_ck_data,
1521 static struct ti_clk clkout2_src_ck = {
1522 .name = "clkout2_src_ck",
1523 .type = TI_CLK_COMPOSITE,
1524 .data = &clkout2_src_ck_data,
1527 static struct ti_clk_gate i2c1_fck_data = {
1528 .parent = "core_96m_fck",
1531 .module = TI_CLKM_CM,
1535 static struct ti_clk i2c1_fck = {
1537 .clkdm_name = "core_l4_clkdm",
1538 .type = TI_CLK_GATE,
1539 .data = &i2c1_fck_data,
1542 static struct ti_clk_gate wdt3_fck_data = {
1543 .parent = "per_32k_alwon_fck",
1546 .module = TI_CLKM_CM,
1550 static struct ti_clk wdt3_fck = {
1552 .clkdm_name = "per_clkdm",
1553 .type = TI_CLK_GATE,
1554 .data = &wdt3_fck_data,
1557 static struct ti_clk_gate gpt7_gate_fck_data = {
1561 .module = TI_CLKM_CM,
1564 static const char *gpt7_mux_fck_parents[] = {
1569 static struct ti_clk_mux gpt7_mux_fck_data = {
1571 .num_parents = ARRAY_SIZE(gpt7_mux_fck_parents),
1573 .module = TI_CLKM_CM,
1574 .parents = gpt7_mux_fck_parents,
1577 static struct ti_clk_composite gpt7_fck_data = {
1578 .mux = &gpt7_mux_fck_data,
1579 .gate = &gpt7_gate_fck_data,
1582 static struct ti_clk gpt7_fck = {
1584 .type = TI_CLK_COMPOSITE,
1585 .data = &gpt7_fck_data,
1588 static struct ti_clk_gate usb_l4_gate_ick_data = {
1592 .module = TI_CLKM_CM,
1593 .flags = CLKF_INTERFACE,
1596 static struct ti_clk_divider usb_l4_div_ick_data = {
1601 .module = TI_CLKM_CM,
1602 .flags = CLKF_INDEX_STARTS_AT_ONE,
1605 static struct ti_clk_composite usb_l4_ick_data = {
1606 .gate = &usb_l4_gate_ick_data,
1607 .divider = &usb_l4_div_ick_data,
1610 static struct ti_clk usb_l4_ick = {
1611 .name = "usb_l4_ick",
1612 .type = TI_CLK_COMPOSITE,
1613 .data = &usb_l4_ick_data,
1616 static struct ti_clk_gate uart4_ick_data = {
1617 .parent = "per_l4_ick",
1620 .module = TI_CLKM_CM,
1621 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1624 static struct ti_clk uart4_ick = {
1625 .name = "uart4_ick",
1626 .clkdm_name = "per_clkdm",
1627 .type = TI_CLK_GATE,
1628 .data = &uart4_ick_data,
1631 static struct ti_clk_fixed dummy_ck_data = {
1635 static struct ti_clk dummy_ck = {
1637 .type = TI_CLK_FIXED,
1638 .data = &dummy_ck_data,
1641 static const char *gpt3_mux_fck_parents[] = {
1646 static struct ti_clk_mux gpt3_mux_fck_data = {
1648 .num_parents = ARRAY_SIZE(gpt3_mux_fck_parents),
1650 .module = TI_CLKM_CM,
1651 .parents = gpt3_mux_fck_parents,
1654 static struct ti_clk_gate gpt9_ick_data = {
1655 .parent = "per_l4_ick",
1658 .module = TI_CLKM_CM,
1659 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1662 static struct ti_clk gpt9_ick = {
1664 .clkdm_name = "per_clkdm",
1665 .type = TI_CLK_GATE,
1666 .data = &gpt9_ick_data,
1669 static struct ti_clk_gate gpt10_gate_fck_data = {
1673 .module = TI_CLKM_CM,
1676 static struct ti_clk_gate dss_ick_3430es1_data = {
1680 .module = TI_CLKM_CM,
1681 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1684 static struct ti_clk dss_ick_3430es1 = {
1686 .clkdm_name = "dss_clkdm",
1687 .type = TI_CLK_GATE,
1688 .data = &dss_ick_3430es1_data,
1691 static struct ti_clk_gate gpt11_ick_data = {
1692 .parent = "core_l4_ick",
1695 .module = TI_CLKM_CM,
1696 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1699 static struct ti_clk gpt11_ick = {
1700 .name = "gpt11_ick",
1701 .clkdm_name = "core_l4_clkdm",
1702 .type = TI_CLK_GATE,
1703 .data = &gpt11_ick_data,
1706 static struct ti_clk_divider dpll2_fck_data = {
1707 .parent = "core_ck",
1711 .module = TI_CLKM_CM,
1712 .flags = CLKF_INDEX_STARTS_AT_ONE,
1715 static struct ti_clk dpll2_fck = {
1716 .name = "dpll2_fck",
1717 .type = TI_CLK_DIVIDER,
1718 .data = &dpll2_fck_data,
1721 static struct ti_clk_gate uart1_fck_data = {
1722 .parent = "core_48m_fck",
1725 .module = TI_CLKM_CM,
1729 static struct ti_clk uart1_fck = {
1730 .name = "uart1_fck",
1731 .clkdm_name = "core_l4_clkdm",
1732 .type = TI_CLK_GATE,
1733 .data = &uart1_fck_data,
1736 static struct ti_clk_gate hsotgusb_ick_3430es1_data = {
1737 .parent = "core_l3_ick",
1740 .module = TI_CLKM_CM,
1741 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1744 static struct ti_clk hsotgusb_ick_3430es1 = {
1745 .name = "hsotgusb_ick_3430es1",
1746 .clkdm_name = "core_l3_clkdm",
1747 .type = TI_CLK_GATE,
1748 .data = &hsotgusb_ick_3430es1_data,
1751 static struct ti_clk_gate gpio2_ick_data = {
1752 .parent = "per_l4_ick",
1755 .module = TI_CLKM_CM,
1756 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1759 static struct ti_clk gpio2_ick = {
1760 .name = "gpio2_ick",
1761 .clkdm_name = "per_clkdm",
1762 .type = TI_CLK_GATE,
1763 .data = &gpio2_ick_data,
1766 static struct ti_clk_gate mmchs1_ick_data = {
1767 .parent = "core_l4_ick",
1770 .module = TI_CLKM_CM,
1771 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1774 static struct ti_clk mmchs1_ick = {
1775 .name = "mmchs1_ick",
1776 .clkdm_name = "core_l4_clkdm",
1777 .type = TI_CLK_GATE,
1778 .data = &mmchs1_ick_data,
1781 static struct ti_clk_gate modem_fck_data = {
1785 .module = TI_CLKM_CM,
1786 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1789 static struct ti_clk modem_fck = {
1790 .name = "modem_fck",
1791 .clkdm_name = "d2d_clkdm",
1792 .type = TI_CLK_GATE,
1793 .data = &modem_fck_data,
1796 static struct ti_clk_gate mcbsp4_ick_data = {
1797 .parent = "per_l4_ick",
1800 .module = TI_CLKM_CM,
1801 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1804 static struct ti_clk mcbsp4_ick = {
1805 .name = "mcbsp4_ick",
1806 .clkdm_name = "per_clkdm",
1807 .type = TI_CLK_GATE,
1808 .data = &mcbsp4_ick_data,
1811 static struct ti_clk_gate gpio1_ick_data = {
1812 .parent = "wkup_l4_ick",
1815 .module = TI_CLKM_CM,
1816 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1819 static struct ti_clk gpio1_ick = {
1820 .name = "gpio1_ick",
1821 .clkdm_name = "wkup_clkdm",
1822 .type = TI_CLK_GATE,
1823 .data = &gpio1_ick_data,
1826 static const char *gpt6_mux_fck_parents[] = {
1831 static struct ti_clk_mux gpt6_mux_fck_data = {
1833 .num_parents = ARRAY_SIZE(gpt6_mux_fck_parents),
1835 .module = TI_CLKM_CM,
1836 .parents = gpt6_mux_fck_parents,
1839 static struct ti_clk_fixed_factor dpll1_x2_ck_data = {
1840 .parent = "dpll1_ck",
1845 static struct ti_clk dpll1_x2_ck = {
1846 .name = "dpll1_x2_ck",
1847 .type = TI_CLK_FIXED_FACTOR,
1848 .data = &dpll1_x2_ck_data,
1851 static struct ti_clk_divider dpll1_x2m2_ck_data = {
1852 .parent = "dpll1_x2_ck",
1855 .module = TI_CLKM_CM,
1856 .flags = CLKF_INDEX_STARTS_AT_ONE,
1859 static struct ti_clk dpll1_x2m2_ck = {
1860 .name = "dpll1_x2m2_ck",
1861 .type = TI_CLK_DIVIDER,
1862 .data = &dpll1_x2m2_ck_data,
1865 static struct ti_clk_fixed_factor mpu_ck_data = {
1866 .parent = "dpll1_x2m2_ck",
1871 static struct ti_clk mpu_ck = {
1873 .type = TI_CLK_FIXED_FACTOR,
1874 .data = &mpu_ck_data,
1877 static struct ti_clk_divider arm_fck_data = {
1881 .module = TI_CLKM_CM,
1884 static struct ti_clk arm_fck = {
1886 .type = TI_CLK_DIVIDER,
1887 .data = &arm_fck_data,
1890 static struct ti_clk_fixed_factor core_d3_ck_data = {
1891 .parent = "core_ck",
1896 static struct ti_clk core_d3_ck = {
1897 .name = "core_d3_ck",
1898 .type = TI_CLK_FIXED_FACTOR,
1899 .data = &core_d3_ck_data,
1902 static struct ti_clk_gate gpt11_gate_fck_data = {
1906 .module = TI_CLKM_CM,
1909 static const char *gpt11_mux_fck_parents[] = {
1914 static struct ti_clk_mux gpt11_mux_fck_data = {
1916 .num_parents = ARRAY_SIZE(gpt11_mux_fck_parents),
1918 .module = TI_CLKM_CM,
1919 .parents = gpt11_mux_fck_parents,
1922 static struct ti_clk_composite gpt11_fck_data = {
1923 .mux = &gpt11_mux_fck_data,
1924 .gate = &gpt11_gate_fck_data,
1927 static struct ti_clk gpt11_fck = {
1928 .name = "gpt11_fck",
1929 .type = TI_CLK_COMPOSITE,
1930 .data = &gpt11_fck_data,
1933 static struct ti_clk_fixed_factor core_d6_ck_data = {
1934 .parent = "core_ck",
1939 static struct ti_clk core_d6_ck = {
1940 .name = "core_d6_ck",
1941 .type = TI_CLK_FIXED_FACTOR,
1942 .data = &core_d6_ck_data,
1945 static struct ti_clk_gate uart4_fck_am35xx_data = {
1946 .parent = "core_48m_fck",
1949 .module = TI_CLKM_CM,
1953 static struct ti_clk uart4_fck_am35xx = {
1954 .name = "uart4_fck_am35xx",
1955 .clkdm_name = "core_l4_clkdm",
1956 .type = TI_CLK_GATE,
1957 .data = &uart4_fck_am35xx_data,
1960 static struct ti_clk_gate dpll3_m3x2_ck_data = {
1961 .parent = "dpll3_m3x2_mul_ck",
1964 .module = TI_CLKM_CM,
1965 .flags = CLKF_SET_BIT_TO_DISABLE,
1968 static struct ti_clk dpll3_m3x2_ck = {
1969 .name = "dpll3_m3x2_ck",
1970 .type = TI_CLK_GATE,
1971 .data = &dpll3_m3x2_ck_data,
1974 static struct ti_clk_fixed_factor emu_core_alwon_ck_data = {
1975 .parent = "dpll3_m3x2_ck",
1980 static struct ti_clk emu_core_alwon_ck = {
1981 .name = "emu_core_alwon_ck",
1982 .type = TI_CLK_FIXED_FACTOR,
1983 .data = &emu_core_alwon_ck_data,
1986 static struct ti_clk_divider dpll4_m6_ck_data = {
1987 .parent = "dpll4_ck",
1991 .module = TI_CLKM_CM,
1992 .flags = CLKF_INDEX_STARTS_AT_ONE,
1995 static struct ti_clk dpll4_m6_ck = {
1996 .name = "dpll4_m6_ck",
1997 .type = TI_CLK_DIVIDER,
1998 .data = &dpll4_m6_ck_data,
2001 static struct ti_clk_fixed_factor dpll4_m6x2_mul_ck_data = {
2002 .parent = "dpll4_m6_ck",
2007 static struct ti_clk dpll4_m6x2_mul_ck = {
2008 .name = "dpll4_m6x2_mul_ck",
2009 .type = TI_CLK_FIXED_FACTOR,
2010 .data = &dpll4_m6x2_mul_ck_data,
2013 static struct ti_clk_gate dpll4_m6x2_ck_data = {
2014 .parent = "dpll4_m6x2_mul_ck",
2017 .module = TI_CLKM_CM,
2018 .flags = CLKF_SET_BIT_TO_DISABLE,
2021 static struct ti_clk dpll4_m6x2_ck = {
2022 .name = "dpll4_m6x2_ck",
2023 .type = TI_CLK_GATE,
2024 .data = &dpll4_m6x2_ck_data,
2027 static struct ti_clk_fixed_factor emu_per_alwon_ck_data = {
2028 .parent = "dpll4_m6x2_ck",
2033 static struct ti_clk emu_per_alwon_ck = {
2034 .name = "emu_per_alwon_ck",
2035 .type = TI_CLK_FIXED_FACTOR,
2036 .data = &emu_per_alwon_ck_data,
2039 static struct ti_clk_fixed_factor emu_mpu_alwon_ck_data = {
2045 static struct ti_clk emu_mpu_alwon_ck = {
2046 .name = "emu_mpu_alwon_ck",
2047 .type = TI_CLK_FIXED_FACTOR,
2048 .data = &emu_mpu_alwon_ck_data,
2051 static const char *emu_src_mux_ck_parents[] = {
2053 "emu_core_alwon_ck",
2058 static struct ti_clk_mux emu_src_mux_ck_data = {
2059 .num_parents = ARRAY_SIZE(emu_src_mux_ck_parents),
2061 .module = TI_CLKM_CM,
2062 .parents = emu_src_mux_ck_parents,
2065 static struct ti_clk emu_src_mux_ck = {
2066 .name = "emu_src_mux_ck",
2068 .data = &emu_src_mux_ck_data,
2071 static struct ti_clk_gate emu_src_ck_data = {
2072 .parent = "emu_src_mux_ck",
2073 .flags = CLKF_CLKDM,
2076 static struct ti_clk emu_src_ck = {
2077 .name = "emu_src_ck",
2078 .clkdm_name = "emu_clkdm",
2079 .type = TI_CLK_GATE,
2080 .data = &emu_src_ck_data,
2083 static struct ti_clk_divider atclk_fck_data = {
2084 .parent = "emu_src_ck",
2088 .module = TI_CLKM_CM,
2089 .flags = CLKF_INDEX_STARTS_AT_ONE,
2092 static struct ti_clk atclk_fck = {
2093 .name = "atclk_fck",
2094 .type = TI_CLK_DIVIDER,
2095 .data = &atclk_fck_data,
2098 static struct ti_clk_gate ipss_ick_data = {
2099 .parent = "core_l3_ick",
2102 .module = TI_CLKM_CM,
2103 .flags = CLKF_AM35XX | CLKF_INTERFACE,
2106 static struct ti_clk ipss_ick = {
2108 .clkdm_name = "core_l3_clkdm",
2109 .type = TI_CLK_GATE,
2110 .data = &ipss_ick_data,
2113 static struct ti_clk_gate emac_ick_data = {
2114 .parent = "ipss_ick",
2117 .module = TI_CLKM_SCRM,
2118 .flags = CLKF_AM35XX,
2121 static struct ti_clk emac_ick = {
2123 .clkdm_name = "core_l3_clkdm",
2124 .type = TI_CLK_GATE,
2125 .data = &emac_ick_data,
2128 static struct ti_clk_gate vpfe_ick_data = {
2129 .parent = "ipss_ick",
2132 .module = TI_CLKM_SCRM,
2133 .flags = CLKF_AM35XX,
2136 static struct ti_clk vpfe_ick = {
2138 .clkdm_name = "core_l3_clkdm",
2139 .type = TI_CLK_GATE,
2140 .data = &vpfe_ick_data,
2143 static const char *dpll2_ck_parents[] = {
2148 static struct ti_clk_dpll dpll2_ck_data = {
2149 .num_parents = ARRAY_SIZE(dpll2_ck_parents),
2152 .mult_div1_reg = 0x40,
2153 .autoidle_reg = 0x34,
2154 .module = TI_CLKM_CM,
2155 .parents = dpll2_ck_parents,
2156 .freqsel_mask = 0xf0,
2160 .auto_recal_bit = 0x3,
2161 .max_divider = 0x80,
2163 .recal_en_bit = 0x8,
2164 .max_multiplier = 0x7ff,
2166 .mult_mask = 0x7ff00,
2167 .recal_st_bit = 0x8,
2168 .autoidle_mask = 0x7,
2171 static struct ti_clk dpll2_ck = {
2173 .clkdm_name = "dpll2_clkdm",
2174 .type = TI_CLK_DPLL,
2175 .data = &dpll2_ck_data,
2178 static struct ti_clk_divider dpll2_m2_ck_data = {
2179 .parent = "dpll2_ck",
2182 .module = TI_CLKM_CM,
2183 .flags = CLKF_INDEX_STARTS_AT_ONE,
2186 static struct ti_clk dpll2_m2_ck = {
2187 .name = "dpll2_m2_ck",
2188 .type = TI_CLK_DIVIDER,
2189 .data = &dpll2_m2_ck_data,
2192 static const char *mcbsp4_mux_fck_parents[] = {
2197 static struct ti_clk_mux mcbsp4_mux_fck_data = {
2199 .num_parents = ARRAY_SIZE(mcbsp4_mux_fck_parents),
2201 .module = TI_CLKM_SCRM,
2202 .parents = mcbsp4_mux_fck_parents,
2205 static const char *mcbsp1_mux_fck_parents[] = {
2210 static struct ti_clk_mux mcbsp1_mux_fck_data = {
2212 .num_parents = ARRAY_SIZE(mcbsp1_mux_fck_parents),
2214 .module = TI_CLKM_SCRM,
2215 .parents = mcbsp1_mux_fck_parents,
2218 static struct ti_clk_gate gpt8_gate_fck_data = {
2222 .module = TI_CLKM_CM,
2225 static struct ti_clk_gate gpt8_ick_data = {
2226 .parent = "per_l4_ick",
2229 .module = TI_CLKM_CM,
2230 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2233 static struct ti_clk gpt8_ick = {
2235 .clkdm_name = "per_clkdm",
2236 .type = TI_CLK_GATE,
2237 .data = &gpt8_ick_data,
2240 static const char *gpt10_mux_fck_parents[] = {
2245 static struct ti_clk_mux gpt10_mux_fck_data = {
2247 .num_parents = ARRAY_SIZE(gpt10_mux_fck_parents),
2249 .module = TI_CLKM_CM,
2250 .parents = gpt10_mux_fck_parents,
2253 static struct ti_clk_gate mmchs3_ick_data = {
2254 .parent = "core_l4_ick",
2257 .module = TI_CLKM_CM,
2258 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2261 static struct ti_clk mmchs3_ick = {
2262 .name = "mmchs3_ick",
2263 .clkdm_name = "core_l4_clkdm",
2264 .type = TI_CLK_GATE,
2265 .data = &mmchs3_ick_data,
2268 static struct ti_clk_gate gpio3_ick_data = {
2269 .parent = "per_l4_ick",
2272 .module = TI_CLKM_CM,
2273 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2276 static struct ti_clk gpio3_ick = {
2277 .name = "gpio3_ick",
2278 .clkdm_name = "per_clkdm",
2279 .type = TI_CLK_GATE,
2280 .data = &gpio3_ick_data,
2283 static const char *traceclk_src_fck_parents[] = {
2285 "emu_core_alwon_ck",
2290 static struct ti_clk_mux traceclk_src_fck_data = {
2292 .num_parents = ARRAY_SIZE(traceclk_src_fck_parents),
2294 .module = TI_CLKM_CM,
2295 .parents = traceclk_src_fck_parents,
2298 static struct ti_clk traceclk_src_fck = {
2299 .name = "traceclk_src_fck",
2301 .data = &traceclk_src_fck_data,
2304 static struct ti_clk_divider traceclk_fck_data = {
2305 .parent = "traceclk_src_fck",
2309 .module = TI_CLKM_CM,
2310 .flags = CLKF_INDEX_STARTS_AT_ONE,
2313 static struct ti_clk traceclk_fck = {
2314 .name = "traceclk_fck",
2315 .type = TI_CLK_DIVIDER,
2316 .data = &traceclk_fck_data,
2319 static struct ti_clk_gate mcbsp5_gate_fck_data = {
2320 .parent = "mcbsp_clks",
2323 .module = TI_CLKM_CM,
2326 static struct ti_clk_gate sad2d_ick_data = {
2330 .module = TI_CLKM_CM,
2331 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2334 static struct ti_clk sad2d_ick = {
2335 .name = "sad2d_ick",
2336 .clkdm_name = "d2d_clkdm",
2337 .type = TI_CLK_GATE,
2338 .data = &sad2d_ick_data,
2341 static const char *gpt1_mux_fck_parents[] = {
2346 static struct ti_clk_mux gpt1_mux_fck_data = {
2347 .num_parents = ARRAY_SIZE(gpt1_mux_fck_parents),
2349 .module = TI_CLKM_CM,
2350 .parents = gpt1_mux_fck_parents,
2353 static struct ti_clk_gate hecc_ck_data = {
2357 .module = TI_CLKM_SCRM,
2358 .flags = CLKF_AM35XX,
2361 static struct ti_clk hecc_ck = {
2363 .clkdm_name = "core_l3_clkdm",
2364 .type = TI_CLK_GATE,
2365 .data = &hecc_ck_data,
2368 static struct ti_clk_gate gpt1_gate_fck_data = {
2372 .module = TI_CLKM_CM,
2375 static struct ti_clk_composite gpt1_fck_data = {
2376 .mux = &gpt1_mux_fck_data,
2377 .gate = &gpt1_gate_fck_data,
2380 static struct ti_clk gpt1_fck = {
2382 .type = TI_CLK_COMPOSITE,
2383 .data = &gpt1_fck_data,
2386 static struct ti_clk_gate dpll4_m2x2_ck_omap36xx_data = {
2387 .parent = "dpll4_m2x2_mul_ck",
2390 .module = TI_CLKM_CM,
2391 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
2394 static struct ti_clk dpll4_m2x2_ck_omap36xx = {
2395 .name = "dpll4_m2x2_ck",
2396 .type = TI_CLK_GATE,
2397 .data = &dpll4_m2x2_ck_omap36xx_data,
2398 .patch = &dpll4_m2x2_ck,
2401 static struct ti_clk_divider gfx_l3_fck_data = {
2405 .module = TI_CLKM_CM,
2406 .flags = CLKF_INDEX_STARTS_AT_ONE,
2409 static struct ti_clk gfx_l3_fck = {
2410 .name = "gfx_l3_fck",
2411 .type = TI_CLK_DIVIDER,
2412 .data = &gfx_l3_fck_data,
2415 static struct ti_clk_gate gfx_cg1_ck_data = {
2416 .parent = "gfx_l3_fck",
2419 .module = TI_CLKM_CM,
2423 static struct ti_clk gfx_cg1_ck = {
2424 .name = "gfx_cg1_ck",
2425 .clkdm_name = "gfx_3430es1_clkdm",
2426 .type = TI_CLK_GATE,
2427 .data = &gfx_cg1_ck_data,
2430 static struct ti_clk_gate mailboxes_ick_data = {
2431 .parent = "core_l4_ick",
2434 .module = TI_CLKM_CM,
2435 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2438 static struct ti_clk mailboxes_ick = {
2439 .name = "mailboxes_ick",
2440 .clkdm_name = "core_l4_clkdm",
2441 .type = TI_CLK_GATE,
2442 .data = &mailboxes_ick_data,
2445 static struct ti_clk_gate sha11_ick_data = {
2446 .parent = "security_l4_ick2",
2449 .module = TI_CLKM_CM,
2450 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2453 static struct ti_clk sha11_ick = {
2454 .name = "sha11_ick",
2455 .type = TI_CLK_GATE,
2456 .data = &sha11_ick_data,
2459 static struct ti_clk_gate hsotgusb_ick_am35xx_data = {
2460 .parent = "ipss_ick",
2463 .module = TI_CLKM_SCRM,
2464 .flags = CLKF_AM35XX,
2467 static struct ti_clk hsotgusb_ick_am35xx = {
2468 .name = "hsotgusb_ick_am35xx",
2469 .clkdm_name = "core_l3_clkdm",
2470 .type = TI_CLK_GATE,
2471 .data = &hsotgusb_ick_am35xx_data,
2474 static struct ti_clk_gate mmchs3_fck_data = {
2475 .parent = "core_96m_fck",
2478 .module = TI_CLKM_CM,
2482 static struct ti_clk mmchs3_fck = {
2483 .name = "mmchs3_fck",
2484 .clkdm_name = "core_l4_clkdm",
2485 .type = TI_CLK_GATE,
2486 .data = &mmchs3_fck_data,
2489 static struct ti_clk_divider pclk_fck_data = {
2490 .parent = "emu_src_ck",
2494 .module = TI_CLKM_CM,
2495 .flags = CLKF_INDEX_STARTS_AT_ONE,
2498 static struct ti_clk pclk_fck = {
2500 .type = TI_CLK_DIVIDER,
2501 .data = &pclk_fck_data,
2504 static const char *dpll4_ck_omap36xx_parents[] = {
2509 static struct ti_clk_dpll dpll4_ck_omap36xx_data = {
2510 .num_parents = ARRAY_SIZE(dpll4_ck_omap36xx_parents),
2511 .control_reg = 0xd00,
2512 .idlest_reg = 0xd20,
2513 .mult_div1_reg = 0xd44,
2514 .autoidle_reg = 0xd30,
2515 .module = TI_CLKM_CM,
2516 .parents = dpll4_ck_omap36xx_parents,
2520 .auto_recal_bit = 0x13,
2521 .max_divider = 0x80,
2523 .recal_en_bit = 0x6,
2524 .max_multiplier = 0xfff,
2525 .enable_mask = 0x70000,
2526 .mult_mask = 0xfff00,
2527 .recal_st_bit = 0x6,
2528 .autoidle_mask = 0x38,
2529 .sddiv_mask = 0xff000000,
2530 .dco_mask = 0xe00000,
2531 .flags = CLKF_PER | CLKF_J_TYPE,
2534 static struct ti_clk dpll4_ck_omap36xx = {
2536 .type = TI_CLK_DPLL,
2537 .data = &dpll4_ck_omap36xx_data,
2541 static struct ti_clk_gate uart3_fck_data = {
2542 .parent = "per_48m_fck",
2545 .module = TI_CLKM_CM,
2549 static struct ti_clk uart3_fck = {
2550 .name = "uart3_fck",
2551 .clkdm_name = "per_clkdm",
2552 .type = TI_CLK_GATE,
2553 .data = &uart3_fck_data,
2556 static struct ti_clk_fixed_factor wkup_32k_fck_data = {
2557 .parent = "omap_32k_fck",
2562 static struct ti_clk wkup_32k_fck = {
2563 .name = "wkup_32k_fck",
2564 .type = TI_CLK_FIXED_FACTOR,
2565 .data = &wkup_32k_fck_data,
2568 static struct ti_clk_gate sys_clkout1_data = {
2569 .parent = "osc_sys_ck",
2572 .module = TI_CLKM_PRM,
2575 static struct ti_clk sys_clkout1 = {
2576 .name = "sys_clkout1",
2577 .type = TI_CLK_GATE,
2578 .data = &sys_clkout1_data,
2581 static struct ti_clk_fixed_factor gpmc_fck_data = {
2582 .parent = "core_l3_ick",
2587 static struct ti_clk gpmc_fck = {
2589 .type = TI_CLK_FIXED_FACTOR,
2590 .data = &gpmc_fck_data,
2593 static struct ti_clk_fixed_factor dpll5_m2_d20_ck_data = {
2594 .parent = "dpll5_m2_ck",
2599 static struct ti_clk dpll5_m2_d20_ck = {
2600 .name = "dpll5_m2_d20_ck",
2601 .type = TI_CLK_FIXED_FACTOR,
2602 .data = &dpll5_m2_d20_ck_data,
2605 static struct ti_clk_gate dpll4_m5x2_ck_omap36xx_data = {
2606 .parent = "dpll4_m5x2_mul_ck",
2609 .module = TI_CLKM_CM,
2610 .flags = CLKF_HSDIV | CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
2613 static struct ti_clk dpll4_m5x2_ck_omap36xx = {
2614 .name = "dpll4_m5x2_ck",
2615 .type = TI_CLK_GATE,
2616 .data = &dpll4_m5x2_ck_omap36xx_data,
2617 .patch = &dpll4_m5x2_ck,
2620 static struct ti_clk_gate ssi_ssr_gate_fck_3430es2_data = {
2621 .parent = "corex2_fck",
2624 .module = TI_CLKM_CM,
2625 .flags = CLKF_NO_WAIT,
2628 static struct ti_clk_gate uart1_ick_data = {
2629 .parent = "core_l4_ick",
2632 .module = TI_CLKM_CM,
2633 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2636 static struct ti_clk uart1_ick = {
2637 .name = "uart1_ick",
2638 .clkdm_name = "core_l4_clkdm",
2639 .type = TI_CLK_GATE,
2640 .data = &uart1_ick_data,
2643 static struct ti_clk_gate iva2_ck_data = {
2644 .parent = "dpll2_m2_ck",
2647 .module = TI_CLKM_CM,
2651 static struct ti_clk iva2_ck = {
2653 .clkdm_name = "iva2_clkdm",
2654 .type = TI_CLK_GATE,
2655 .data = &iva2_ck_data,
2658 static struct ti_clk_gate pka_ick_data = {
2659 .parent = "security_l3_ick",
2662 .module = TI_CLKM_CM,
2663 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2666 static struct ti_clk pka_ick = {
2668 .type = TI_CLK_GATE,
2669 .data = &pka_ick_data,
2672 static struct ti_clk_gate gpt12_ick_data = {
2673 .parent = "wkup_l4_ick",
2676 .module = TI_CLKM_CM,
2677 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2680 static struct ti_clk gpt12_ick = {
2681 .name = "gpt12_ick",
2682 .clkdm_name = "wkup_clkdm",
2683 .type = TI_CLK_GATE,
2684 .data = &gpt12_ick_data,
2687 static const char *mcbsp5_mux_fck_parents[] = {
2692 static struct ti_clk_mux mcbsp5_mux_fck_data = {
2694 .num_parents = ARRAY_SIZE(mcbsp5_mux_fck_parents),
2696 .module = TI_CLKM_SCRM,
2697 .parents = mcbsp5_mux_fck_parents,
2700 static struct ti_clk_composite mcbsp5_fck_data = {
2701 .mux = &mcbsp5_mux_fck_data,
2702 .gate = &mcbsp5_gate_fck_data,
2705 static struct ti_clk mcbsp5_fck = {
2706 .name = "mcbsp5_fck",
2707 .type = TI_CLK_COMPOSITE,
2708 .data = &mcbsp5_fck_data,
2711 static struct ti_clk_gate usbhost_48m_fck_data = {
2712 .parent = "omap_48m_fck",
2715 .module = TI_CLKM_CM,
2719 static struct ti_clk usbhost_48m_fck = {
2720 .name = "usbhost_48m_fck",
2721 .clkdm_name = "usbhost_clkdm",
2722 .type = TI_CLK_GATE,
2723 .data = &usbhost_48m_fck_data,
2726 static struct ti_clk_gate des1_ick_data = {
2727 .parent = "security_l4_ick2",
2730 .module = TI_CLKM_CM,
2731 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2734 static struct ti_clk des1_ick = {
2736 .type = TI_CLK_GATE,
2737 .data = &des1_ick_data,
2740 static struct ti_clk_gate sgx_gate_fck_data = {
2741 .parent = "core_ck",
2744 .module = TI_CLKM_CM,
2747 static struct ti_clk_fixed_factor core_d4_ck_data = {
2748 .parent = "core_ck",
2753 static struct ti_clk core_d4_ck = {
2754 .name = "core_d4_ck",
2755 .type = TI_CLK_FIXED_FACTOR,
2756 .data = &core_d4_ck_data,
2759 static struct ti_clk_fixed_factor omap_192m_alwon_fck_data = {
2760 .parent = "dpll4_m2x2_ck",
2765 static struct ti_clk omap_192m_alwon_fck = {
2766 .name = "omap_192m_alwon_fck",
2767 .type = TI_CLK_FIXED_FACTOR,
2768 .data = &omap_192m_alwon_fck_data,
2771 static struct ti_clk_fixed_factor core_d2_ck_data = {
2772 .parent = "core_ck",
2777 static struct ti_clk core_d2_ck = {
2778 .name = "core_d2_ck",
2779 .type = TI_CLK_FIXED_FACTOR,
2780 .data = &core_d2_ck_data,
2783 static struct ti_clk_fixed_factor corex2_d3_fck_data = {
2784 .parent = "corex2_fck",
2789 static struct ti_clk corex2_d3_fck = {
2790 .name = "corex2_d3_fck",
2791 .type = TI_CLK_FIXED_FACTOR,
2792 .data = &corex2_d3_fck_data,
2795 static struct ti_clk_fixed_factor corex2_d5_fck_data = {
2796 .parent = "corex2_fck",
2801 static struct ti_clk corex2_d5_fck = {
2802 .name = "corex2_d5_fck",
2803 .type = TI_CLK_FIXED_FACTOR,
2804 .data = &corex2_d5_fck_data,
2807 static const char *sgx_mux_fck_parents[] = {
2812 "omap_192m_alwon_fck",
2818 static struct ti_clk_mux sgx_mux_fck_data = {
2819 .num_parents = ARRAY_SIZE(sgx_mux_fck_parents),
2821 .module = TI_CLKM_CM,
2822 .parents = sgx_mux_fck_parents,
2825 static struct ti_clk_composite sgx_fck_data = {
2826 .mux = &sgx_mux_fck_data,
2827 .gate = &sgx_gate_fck_data,
2830 static struct ti_clk sgx_fck = {
2832 .type = TI_CLK_COMPOSITE,
2833 .data = &sgx_fck_data,
2836 static struct ti_clk_gate mcspi1_fck_data = {
2837 .parent = "core_48m_fck",
2840 .module = TI_CLKM_CM,
2844 static struct ti_clk mcspi1_fck = {
2845 .name = "mcspi1_fck",
2846 .clkdm_name = "core_l4_clkdm",
2847 .type = TI_CLK_GATE,
2848 .data = &mcspi1_fck_data,
2851 static struct ti_clk_gate mmchs2_fck_data = {
2852 .parent = "core_96m_fck",
2855 .module = TI_CLKM_CM,
2859 static struct ti_clk mmchs2_fck = {
2860 .name = "mmchs2_fck",
2861 .clkdm_name = "core_l4_clkdm",
2862 .type = TI_CLK_GATE,
2863 .data = &mmchs2_fck_data,
2866 static struct ti_clk_gate mcspi2_fck_data = {
2867 .parent = "core_48m_fck",
2870 .module = TI_CLKM_CM,
2874 static struct ti_clk mcspi2_fck = {
2875 .name = "mcspi2_fck",
2876 .clkdm_name = "core_l4_clkdm",
2877 .type = TI_CLK_GATE,
2878 .data = &mcspi2_fck_data,
2881 static struct ti_clk_gate vpfe_fck_data = {
2882 .parent = "pclk_ck",
2885 .module = TI_CLKM_SCRM,
2888 static struct ti_clk vpfe_fck = {
2890 .type = TI_CLK_GATE,
2891 .data = &vpfe_fck_data,
2894 static struct ti_clk_gate gpt4_gate_fck_data = {
2898 .module = TI_CLKM_CM,
2901 static struct ti_clk_gate mcbsp1_gate_fck_data = {
2902 .parent = "mcbsp_clks",
2905 .module = TI_CLKM_CM,
2908 static struct ti_clk_gate gpt5_gate_fck_data = {
2912 .module = TI_CLKM_CM,
2915 static const char *gpt5_mux_fck_parents[] = {
2920 static struct ti_clk_mux gpt5_mux_fck_data = {
2922 .num_parents = ARRAY_SIZE(gpt5_mux_fck_parents),
2924 .module = TI_CLKM_CM,
2925 .parents = gpt5_mux_fck_parents,
2928 static struct ti_clk_composite gpt5_fck_data = {
2929 .mux = &gpt5_mux_fck_data,
2930 .gate = &gpt5_gate_fck_data,
2933 static struct ti_clk gpt5_fck = {
2935 .type = TI_CLK_COMPOSITE,
2936 .data = &gpt5_fck_data,
2939 static struct ti_clk_gate ts_fck_data = {
2940 .parent = "omap_32k_fck",
2943 .module = TI_CLKM_CM,
2946 static struct ti_clk ts_fck = {
2948 .clkdm_name = "core_l4_clkdm",
2949 .type = TI_CLK_GATE,
2950 .data = &ts_fck_data,
2953 static struct ti_clk_fixed_factor wdt1_fck_data = {
2954 .parent = "secure_32k_fck",
2959 static struct ti_clk wdt1_fck = {
2961 .type = TI_CLK_FIXED_FACTOR,
2962 .data = &wdt1_fck_data,
2965 static struct ti_clk_gate dpll4_m6x2_ck_omap36xx_data = {
2966 .parent = "dpll4_m6x2_mul_ck",
2969 .module = TI_CLKM_CM,
2970 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
2973 static struct ti_clk dpll4_m6x2_ck_omap36xx = {
2974 .name = "dpll4_m6x2_ck",
2975 .type = TI_CLK_GATE,
2976 .data = &dpll4_m6x2_ck_omap36xx_data,
2977 .patch = &dpll4_m6x2_ck,
2980 static const char *gpt4_mux_fck_parents[] = {
2985 static struct ti_clk_mux gpt4_mux_fck_data = {
2987 .num_parents = ARRAY_SIZE(gpt4_mux_fck_parents),
2989 .module = TI_CLKM_CM,
2990 .parents = gpt4_mux_fck_parents,
2993 static struct ti_clk_gate usbhost_ick_data = {
2997 .module = TI_CLKM_CM,
2998 .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
3001 static struct ti_clk usbhost_ick = {
3002 .name = "usbhost_ick",
3003 .clkdm_name = "usbhost_clkdm",
3004 .type = TI_CLK_GATE,
3005 .data = &usbhost_ick_data,
3008 static struct ti_clk_gate mcbsp2_ick_data = {
3009 .parent = "per_l4_ick",
3012 .module = TI_CLKM_CM,
3013 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3016 static struct ti_clk mcbsp2_ick = {
3017 .name = "mcbsp2_ick",
3018 .clkdm_name = "per_clkdm",
3019 .type = TI_CLK_GATE,
3020 .data = &mcbsp2_ick_data,
3023 static struct ti_clk_gate omapctrl_ick_data = {
3024 .parent = "core_l4_ick",
3027 .module = TI_CLKM_CM,
3028 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3031 static struct ti_clk omapctrl_ick = {
3032 .name = "omapctrl_ick",
3033 .clkdm_name = "core_l4_clkdm",
3034 .type = TI_CLK_GATE,
3035 .data = &omapctrl_ick_data,
3038 static struct ti_clk_fixed_factor omap_96m_d4_fck_data = {
3039 .parent = "omap_96m_fck",
3044 static struct ti_clk omap_96m_d4_fck = {
3045 .name = "omap_96m_d4_fck",
3046 .type = TI_CLK_FIXED_FACTOR,
3047 .data = &omap_96m_d4_fck_data,
3050 static struct ti_clk_gate gpt6_ick_data = {
3051 .parent = "per_l4_ick",
3054 .module = TI_CLKM_CM,
3055 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3058 static struct ti_clk gpt6_ick = {
3060 .clkdm_name = "per_clkdm",
3061 .type = TI_CLK_GATE,
3062 .data = &gpt6_ick_data,
3065 static struct ti_clk_gate dpll3_m3x2_ck_omap36xx_data = {
3066 .parent = "dpll3_m3x2_mul_ck",
3069 .module = TI_CLKM_CM,
3070 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
3073 static struct ti_clk dpll3_m3x2_ck_omap36xx = {
3074 .name = "dpll3_m3x2_ck",
3075 .type = TI_CLK_GATE,
3076 .data = &dpll3_m3x2_ck_omap36xx_data,
3077 .patch = &dpll3_m3x2_ck,
3080 static struct ti_clk_gate i2c3_ick_data = {
3081 .parent = "core_l4_ick",
3084 .module = TI_CLKM_CM,
3085 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3088 static struct ti_clk i2c3_ick = {
3090 .clkdm_name = "core_l4_clkdm",
3091 .type = TI_CLK_GATE,
3092 .data = &i2c3_ick_data,
3095 static struct ti_clk_gate gpio6_ick_data = {
3096 .parent = "per_l4_ick",
3099 .module = TI_CLKM_CM,
3100 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3103 static struct ti_clk gpio6_ick = {
3104 .name = "gpio6_ick",
3105 .clkdm_name = "per_clkdm",
3106 .type = TI_CLK_GATE,
3107 .data = &gpio6_ick_data,
3110 static struct ti_clk_gate mspro_ick_data = {
3111 .parent = "core_l4_ick",
3114 .module = TI_CLKM_CM,
3115 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3118 static struct ti_clk mspro_ick = {
3119 .name = "mspro_ick",
3120 .clkdm_name = "core_l4_clkdm",
3121 .type = TI_CLK_GATE,
3122 .data = &mspro_ick_data,
3125 static struct ti_clk_composite mcbsp1_fck_data = {
3126 .mux = &mcbsp1_mux_fck_data,
3127 .gate = &mcbsp1_gate_fck_data,
3130 static struct ti_clk mcbsp1_fck = {
3131 .name = "mcbsp1_fck",
3132 .type = TI_CLK_COMPOSITE,
3133 .data = &mcbsp1_fck_data,
3136 static struct ti_clk_gate gpt3_gate_fck_data = {
3140 .module = TI_CLKM_CM,
3143 static struct ti_clk_fixed rmii_ck_data = {
3144 .frequency = 50000000,
3147 static struct ti_clk rmii_ck = {
3149 .type = TI_CLK_FIXED,
3150 .data = &rmii_ck_data,
3153 static struct ti_clk_gate gpt6_gate_fck_data = {
3157 .module = TI_CLKM_CM,
3160 static struct ti_clk_composite gpt6_fck_data = {
3161 .mux = &gpt6_mux_fck_data,
3162 .gate = &gpt6_gate_fck_data,
3165 static struct ti_clk gpt6_fck = {
3167 .type = TI_CLK_COMPOSITE,
3168 .data = &gpt6_fck_data,
3171 static struct ti_clk_fixed_factor dpll5_m2_d4_ck_data = {
3172 .parent = "dpll5_m2_ck",
3177 static struct ti_clk dpll5_m2_d4_ck = {
3178 .name = "dpll5_m2_d4_ck",
3179 .type = TI_CLK_FIXED_FACTOR,
3180 .data = &dpll5_m2_d4_ck_data,
3183 static struct ti_clk_fixed_factor sys_d2_ck_data = {
3189 static struct ti_clk sys_d2_ck = {
3190 .name = "sys_d2_ck",
3191 .type = TI_CLK_FIXED_FACTOR,
3192 .data = &sys_d2_ck_data,
3195 static struct ti_clk_fixed_factor omap_96m_d2_fck_data = {
3196 .parent = "omap_96m_fck",
3201 static struct ti_clk omap_96m_d2_fck = {
3202 .name = "omap_96m_d2_fck",
3203 .type = TI_CLK_FIXED_FACTOR,
3204 .data = &omap_96m_d2_fck_data,
3207 static struct ti_clk_fixed_factor dpll5_m2_d8_ck_data = {
3208 .parent = "dpll5_m2_ck",
3213 static struct ti_clk dpll5_m2_d8_ck = {
3214 .name = "dpll5_m2_d8_ck",
3215 .type = TI_CLK_FIXED_FACTOR,
3216 .data = &dpll5_m2_d8_ck_data,
3219 static struct ti_clk_fixed_factor dpll5_m2_d16_ck_data = {
3220 .parent = "dpll5_m2_ck",
3225 static struct ti_clk dpll5_m2_d16_ck = {
3226 .name = "dpll5_m2_d16_ck",
3227 .type = TI_CLK_FIXED_FACTOR,
3228 .data = &dpll5_m2_d16_ck_data,
3231 static const char *usim_mux_fck_parents[] = {
3244 static struct ti_clk_mux usim_mux_fck_data = {
3246 .num_parents = ARRAY_SIZE(usim_mux_fck_parents),
3248 .module = TI_CLKM_CM,
3249 .parents = usim_mux_fck_parents,
3250 .flags = CLKF_INDEX_STARTS_AT_ONE,
3253 static struct ti_clk_composite usim_fck_data = {
3254 .mux = &usim_mux_fck_data,
3255 .gate = &usim_gate_fck_data,
3258 static struct ti_clk usim_fck = {
3260 .type = TI_CLK_COMPOSITE,
3261 .data = &usim_fck_data,
3264 static int ssi_ssr_div_fck_3430es2_divs[] = {
3276 static struct ti_clk_divider ssi_ssr_div_fck_3430es2_data = {
3277 .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es2_divs),
3278 .parent = "corex2_fck",
3280 .dividers = ssi_ssr_div_fck_3430es2_divs,
3282 .module = TI_CLKM_CM,
3285 static struct ti_clk_composite ssi_ssr_fck_3430es2_data = {
3286 .gate = &ssi_ssr_gate_fck_3430es2_data,
3287 .divider = &ssi_ssr_div_fck_3430es2_data,
3290 static struct ti_clk ssi_ssr_fck_3430es2 = {
3291 .name = "ssi_ssr_fck",
3292 .type = TI_CLK_COMPOSITE,
3293 .data = &ssi_ssr_fck_3430es2_data,
3296 static struct ti_clk_gate dss1_alwon_fck_3430es1_data = {
3297 .parent = "dpll4_m4x2_ck",
3300 .module = TI_CLKM_CM,
3301 .flags = CLKF_SET_RATE_PARENT,
3304 static struct ti_clk dss1_alwon_fck_3430es1 = {
3305 .name = "dss1_alwon_fck",
3306 .clkdm_name = "dss_clkdm",
3307 .type = TI_CLK_GATE,
3308 .data = &dss1_alwon_fck_3430es1_data,
3311 static struct ti_clk_gate gpt3_ick_data = {
3312 .parent = "per_l4_ick",
3315 .module = TI_CLKM_CM,
3316 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3319 static struct ti_clk gpt3_ick = {
3321 .clkdm_name = "per_clkdm",
3322 .type = TI_CLK_GATE,
3323 .data = &gpt3_ick_data,
3326 static struct ti_clk_fixed_factor omap_12m_fck_data = {
3327 .parent = "omap_48m_fck",
3332 static struct ti_clk omap_12m_fck = {
3333 .name = "omap_12m_fck",
3334 .type = TI_CLK_FIXED_FACTOR,
3335 .data = &omap_12m_fck_data,
3338 static struct ti_clk_fixed_factor core_12m_fck_data = {
3339 .parent = "omap_12m_fck",
3344 static struct ti_clk core_12m_fck = {
3345 .name = "core_12m_fck",
3346 .type = TI_CLK_FIXED_FACTOR,
3347 .data = &core_12m_fck_data,
3350 static struct ti_clk_gate hdq_fck_data = {
3351 .parent = "core_12m_fck",
3354 .module = TI_CLKM_CM,
3358 static struct ti_clk hdq_fck = {
3360 .clkdm_name = "core_l4_clkdm",
3361 .type = TI_CLK_GATE,
3362 .data = &hdq_fck_data,
3365 static struct ti_clk_gate usbtll_fck_data = {
3366 .parent = "dpll5_m2_ck",
3369 .module = TI_CLKM_CM,
3373 static struct ti_clk usbtll_fck = {
3374 .name = "usbtll_fck",
3375 .clkdm_name = "core_l4_clkdm",
3376 .type = TI_CLK_GATE,
3377 .data = &usbtll_fck_data,
3380 static struct ti_clk_gate hsotgusb_fck_am35xx_data = {
3384 .module = TI_CLKM_SCRM,
3387 static struct ti_clk hsotgusb_fck_am35xx = {
3388 .name = "hsotgusb_fck_am35xx",
3389 .clkdm_name = "core_l3_clkdm",
3390 .type = TI_CLK_GATE,
3391 .data = &hsotgusb_fck_am35xx_data,
3394 static struct ti_clk_gate hsotgusb_ick_3430es2_data = {
3395 .parent = "core_l3_ick",
3398 .module = TI_CLKM_CM,
3399 .flags = CLKF_HSOTGUSB | CLKF_OMAP3 | CLKF_INTERFACE,
3402 static struct ti_clk hsotgusb_ick_3430es2 = {
3403 .name = "hsotgusb_ick_3430es2",
3404 .clkdm_name = "core_l3_clkdm",
3405 .type = TI_CLK_GATE,
3406 .data = &hsotgusb_ick_3430es2_data,
3409 static struct ti_clk_gate gfx_l3_ck_data = {
3413 .module = TI_CLKM_CM,
3417 static struct ti_clk gfx_l3_ck = {
3418 .name = "gfx_l3_ck",
3419 .clkdm_name = "gfx_3430es1_clkdm",
3420 .type = TI_CLK_GATE,
3421 .data = &gfx_l3_ck_data,
3424 static struct ti_clk_fixed_factor gfx_l3_ick_data = {
3425 .parent = "gfx_l3_ck",
3430 static struct ti_clk gfx_l3_ick = {
3431 .name = "gfx_l3_ick",
3432 .type = TI_CLK_FIXED_FACTOR,
3433 .data = &gfx_l3_ick_data,
3436 static struct ti_clk_gate mcbsp1_ick_data = {
3437 .parent = "core_l4_ick",
3440 .module = TI_CLKM_CM,
3441 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3444 static struct ti_clk mcbsp1_ick = {
3445 .name = "mcbsp1_ick",
3446 .clkdm_name = "core_l4_clkdm",
3447 .type = TI_CLK_GATE,
3448 .data = &mcbsp1_ick_data,
3451 static struct ti_clk_fixed_factor gpt12_fck_data = {
3452 .parent = "secure_32k_fck",
3457 static struct ti_clk gpt12_fck = {
3458 .name = "gpt12_fck",
3459 .type = TI_CLK_FIXED_FACTOR,
3460 .data = &gpt12_fck_data,
3463 static struct ti_clk_gate gfx_cg2_ck_data = {
3464 .parent = "gfx_l3_fck",
3467 .module = TI_CLKM_CM,
3471 static struct ti_clk gfx_cg2_ck = {
3472 .name = "gfx_cg2_ck",
3473 .clkdm_name = "gfx_3430es1_clkdm",
3474 .type = TI_CLK_GATE,
3475 .data = &gfx_cg2_ck_data,
3478 static struct ti_clk_gate i2c2_ick_data = {
3479 .parent = "core_l4_ick",
3482 .module = TI_CLKM_CM,
3483 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3486 static struct ti_clk i2c2_ick = {
3488 .clkdm_name = "core_l4_clkdm",
3489 .type = TI_CLK_GATE,
3490 .data = &i2c2_ick_data,
3493 static struct ti_clk_gate gpio4_dbck_data = {
3494 .parent = "per_32k_alwon_fck",
3497 .module = TI_CLKM_CM,
3500 static struct ti_clk gpio4_dbck = {
3501 .name = "gpio4_dbck",
3502 .clkdm_name = "per_clkdm",
3503 .type = TI_CLK_GATE,
3504 .data = &gpio4_dbck_data,
3507 static struct ti_clk_gate i2c3_fck_data = {
3508 .parent = "core_96m_fck",
3511 .module = TI_CLKM_CM,
3515 static struct ti_clk i2c3_fck = {
3517 .clkdm_name = "core_l4_clkdm",
3518 .type = TI_CLK_GATE,
3519 .data = &i2c3_fck_data,
3522 static struct ti_clk_composite gpt3_fck_data = {
3523 .mux = &gpt3_mux_fck_data,
3524 .gate = &gpt3_gate_fck_data,
3527 static struct ti_clk gpt3_fck = {
3529 .type = TI_CLK_COMPOSITE,
3530 .data = &gpt3_fck_data,
3533 static struct ti_clk_gate i2c1_ick_data = {
3534 .parent = "core_l4_ick",
3537 .module = TI_CLKM_CM,
3538 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3541 static struct ti_clk i2c1_ick = {
3543 .clkdm_name = "core_l4_clkdm",
3544 .type = TI_CLK_GATE,
3545 .data = &i2c1_ick_data,
3548 static struct ti_clk_gate omap_32ksync_ick_data = {
3549 .parent = "wkup_l4_ick",
3552 .module = TI_CLKM_CM,
3553 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3556 static struct ti_clk omap_32ksync_ick = {
3557 .name = "omap_32ksync_ick",
3558 .clkdm_name = "wkup_clkdm",
3559 .type = TI_CLK_GATE,
3560 .data = &omap_32ksync_ick_data,
3563 static struct ti_clk_gate aes2_ick_data = {
3564 .parent = "core_l4_ick",
3567 .module = TI_CLKM_CM,
3568 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3571 static struct ti_clk aes2_ick = {
3573 .clkdm_name = "core_l4_clkdm",
3574 .type = TI_CLK_GATE,
3575 .data = &aes2_ick_data,
3578 static const char *gpt8_mux_fck_parents[] = {
3583 static struct ti_clk_mux gpt8_mux_fck_data = {
3585 .num_parents = ARRAY_SIZE(gpt8_mux_fck_parents),
3587 .module = TI_CLKM_CM,
3588 .parents = gpt8_mux_fck_parents,
3591 static struct ti_clk_composite gpt8_fck_data = {
3592 .mux = &gpt8_mux_fck_data,
3593 .gate = &gpt8_gate_fck_data,
3596 static struct ti_clk gpt8_fck = {
3598 .type = TI_CLK_COMPOSITE,
3599 .data = &gpt8_fck_data,
3602 static struct ti_clk_gate mcbsp4_gate_fck_data = {
3603 .parent = "mcbsp_clks",
3606 .module = TI_CLKM_CM,
3609 static struct ti_clk_composite mcbsp4_fck_data = {
3610 .mux = &mcbsp4_mux_fck_data,
3611 .gate = &mcbsp4_gate_fck_data,
3614 static struct ti_clk mcbsp4_fck = {
3615 .name = "mcbsp4_fck",
3616 .type = TI_CLK_COMPOSITE,
3617 .data = &mcbsp4_fck_data,
3620 static struct ti_clk_gate gpio2_dbck_data = {
3621 .parent = "per_32k_alwon_fck",
3624 .module = TI_CLKM_CM,
3627 static struct ti_clk gpio2_dbck = {
3628 .name = "gpio2_dbck",
3629 .clkdm_name = "per_clkdm",
3630 .type = TI_CLK_GATE,
3631 .data = &gpio2_dbck_data,
3634 static struct ti_clk_gate usbtll_ick_data = {
3635 .parent = "core_l4_ick",
3638 .module = TI_CLKM_CM,
3639 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3642 static struct ti_clk usbtll_ick = {
3643 .name = "usbtll_ick",
3644 .clkdm_name = "core_l4_clkdm",
3645 .type = TI_CLK_GATE,
3646 .data = &usbtll_ick_data,
3649 static struct ti_clk_gate mcspi4_ick_data = {
3650 .parent = "core_l4_ick",
3653 .module = TI_CLKM_CM,
3654 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3657 static struct ti_clk mcspi4_ick = {
3658 .name = "mcspi4_ick",
3659 .clkdm_name = "core_l4_clkdm",
3660 .type = TI_CLK_GATE,
3661 .data = &mcspi4_ick_data,
3664 static struct ti_clk_gate dss_96m_fck_data = {
3665 .parent = "omap_96m_fck",
3668 .module = TI_CLKM_CM,
3671 static struct ti_clk dss_96m_fck = {
3672 .name = "dss_96m_fck",
3673 .clkdm_name = "dss_clkdm",
3674 .type = TI_CLK_GATE,
3675 .data = &dss_96m_fck_data,
3678 static struct ti_clk_divider rm_ick_data = {
3683 .module = TI_CLKM_CM,
3684 .flags = CLKF_INDEX_STARTS_AT_ONE,
3687 static struct ti_clk rm_ick = {
3689 .type = TI_CLK_DIVIDER,
3690 .data = &rm_ick_data,
3693 static struct ti_clk_gate hdq_ick_data = {
3694 .parent = "core_l4_ick",
3697 .module = TI_CLKM_CM,
3698 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3701 static struct ti_clk hdq_ick = {
3703 .clkdm_name = "core_l4_clkdm",
3704 .type = TI_CLK_GATE,
3705 .data = &hdq_ick_data,
3708 static struct ti_clk_fixed_factor dpll3_x2_ck_data = {
3709 .parent = "dpll3_ck",
3714 static struct ti_clk dpll3_x2_ck = {
3715 .name = "dpll3_x2_ck",
3716 .type = TI_CLK_FIXED_FACTOR,
3717 .data = &dpll3_x2_ck_data,
3720 static struct ti_clk_gate mad2d_ick_data = {
3724 .module = TI_CLKM_CM,
3725 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3728 static struct ti_clk mad2d_ick = {
3729 .name = "mad2d_ick",
3730 .clkdm_name = "d2d_clkdm",
3731 .type = TI_CLK_GATE,
3732 .data = &mad2d_ick_data,
3735 static struct ti_clk_gate fshostusb_fck_data = {
3736 .parent = "core_48m_fck",
3739 .module = TI_CLKM_CM,
3743 static struct ti_clk fshostusb_fck = {
3744 .name = "fshostusb_fck",
3745 .clkdm_name = "core_l4_clkdm",
3746 .type = TI_CLK_GATE,
3747 .data = &fshostusb_fck_data,
3750 static struct ti_clk_gate sr1_fck_data = {
3754 .module = TI_CLKM_CM,
3758 static struct ti_clk sr1_fck = {
3760 .clkdm_name = "wkup_clkdm",
3761 .type = TI_CLK_GATE,
3762 .data = &sr1_fck_data,
3765 static struct ti_clk_gate des2_ick_data = {
3766 .parent = "core_l4_ick",
3769 .module = TI_CLKM_CM,
3770 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3773 static struct ti_clk des2_ick = {
3775 .clkdm_name = "core_l4_clkdm",
3776 .type = TI_CLK_GATE,
3777 .data = &des2_ick_data,
3780 static struct ti_clk_gate sdrc_ick_data = {
3781 .parent = "core_l3_ick",
3784 .module = TI_CLKM_CM,
3788 static struct ti_clk sdrc_ick = {
3790 .clkdm_name = "core_l3_clkdm",
3791 .type = TI_CLK_GATE,
3792 .data = &sdrc_ick_data,
3795 static struct ti_clk_composite gpt4_fck_data = {
3796 .mux = &gpt4_mux_fck_data,
3797 .gate = &gpt4_gate_fck_data,
3800 static struct ti_clk gpt4_fck = {
3802 .type = TI_CLK_COMPOSITE,
3803 .data = &gpt4_fck_data,
3806 static struct ti_clk_gate dpll4_m3x2_ck_omap36xx_data = {
3807 .parent = "dpll4_m3x2_mul_ck",
3810 .module = TI_CLKM_CM,
3811 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
3814 static struct ti_clk dpll4_m3x2_ck_omap36xx = {
3815 .name = "dpll4_m3x2_ck",
3816 .type = TI_CLK_GATE,
3817 .data = &dpll4_m3x2_ck_omap36xx_data,
3818 .patch = &dpll4_m3x2_ck,
3821 static struct ti_clk_gate cpefuse_fck_data = {
3825 .module = TI_CLKM_CM,
3828 static struct ti_clk cpefuse_fck = {
3829 .name = "cpefuse_fck",
3830 .clkdm_name = "core_l4_clkdm",
3831 .type = TI_CLK_GATE,
3832 .data = &cpefuse_fck_data,
3835 static struct ti_clk_gate mcspi3_ick_data = {
3836 .parent = "core_l4_ick",
3839 .module = TI_CLKM_CM,
3840 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3843 static struct ti_clk mcspi3_ick = {
3844 .name = "mcspi3_ick",
3845 .clkdm_name = "core_l4_clkdm",
3846 .type = TI_CLK_GATE,
3847 .data = &mcspi3_ick_data,
3850 static struct ti_clk_fixed_factor ssi_sst_fck_3430es2_data = {
3851 .parent = "ssi_ssr_fck",
3856 static struct ti_clk ssi_sst_fck_3430es2 = {
3857 .name = "ssi_sst_fck",
3858 .type = TI_CLK_FIXED_FACTOR,
3859 .data = &ssi_sst_fck_3430es2_data,
3862 static struct ti_clk_gate gpio1_dbck_data = {
3863 .parent = "wkup_32k_fck",
3866 .module = TI_CLKM_CM,
3869 static struct ti_clk gpio1_dbck = {
3870 .name = "gpio1_dbck",
3871 .clkdm_name = "wkup_clkdm",
3872 .type = TI_CLK_GATE,
3873 .data = &gpio1_dbck_data,
3876 static struct ti_clk_gate gpt4_ick_data = {
3877 .parent = "per_l4_ick",
3880 .module = TI_CLKM_CM,
3881 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3884 static struct ti_clk gpt4_ick = {
3886 .clkdm_name = "per_clkdm",
3887 .type = TI_CLK_GATE,
3888 .data = &gpt4_ick_data,
3891 static struct ti_clk_gate gpt2_ick_data = {
3892 .parent = "per_l4_ick",
3895 .module = TI_CLKM_CM,
3896 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3899 static struct ti_clk gpt2_ick = {
3901 .clkdm_name = "per_clkdm",
3902 .type = TI_CLK_GATE,
3903 .data = &gpt2_ick_data,
3906 static struct ti_clk_gate mmchs1_fck_data = {
3907 .parent = "core_96m_fck",
3910 .module = TI_CLKM_CM,
3914 static struct ti_clk mmchs1_fck = {
3915 .name = "mmchs1_fck",
3916 .clkdm_name = "core_l4_clkdm",
3917 .type = TI_CLK_GATE,
3918 .data = &mmchs1_fck_data,
3921 static struct ti_clk_fixed dummy_apb_pclk_data = {
3925 static struct ti_clk dummy_apb_pclk = {
3926 .name = "dummy_apb_pclk",
3927 .type = TI_CLK_FIXED,
3928 .data = &dummy_apb_pclk_data,
3931 static struct ti_clk_gate gpio6_dbck_data = {
3932 .parent = "per_32k_alwon_fck",
3935 .module = TI_CLKM_CM,
3938 static struct ti_clk gpio6_dbck = {
3939 .name = "gpio6_dbck",
3940 .clkdm_name = "per_clkdm",
3941 .type = TI_CLK_GATE,
3942 .data = &gpio6_dbck_data,
3945 static struct ti_clk_gate uart2_ick_data = {
3946 .parent = "core_l4_ick",
3949 .module = TI_CLKM_CM,
3950 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3953 static struct ti_clk uart2_ick = {
3954 .name = "uart2_ick",
3955 .clkdm_name = "core_l4_clkdm",
3956 .type = TI_CLK_GATE,
3957 .data = &uart2_ick_data,
3960 static struct ti_clk_fixed_factor dpll4_x2_ck_data = {
3961 .parent = "dpll4_ck",
3966 static struct ti_clk dpll4_x2_ck = {
3967 .name = "dpll4_x2_ck",
3968 .type = TI_CLK_FIXED_FACTOR,
3969 .data = &dpll4_x2_ck_data,
3972 static struct ti_clk_gate gpt7_ick_data = {
3973 .parent = "per_l4_ick",
3976 .module = TI_CLKM_CM,
3977 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3980 static struct ti_clk gpt7_ick = {
3982 .clkdm_name = "per_clkdm",
3983 .type = TI_CLK_GATE,
3984 .data = &gpt7_ick_data,
3987 static struct ti_clk_gate dss_tv_fck_data = {
3988 .parent = "omap_54m_fck",
3991 .module = TI_CLKM_CM,
3994 static struct ti_clk dss_tv_fck = {
3995 .name = "dss_tv_fck",
3996 .clkdm_name = "dss_clkdm",
3997 .type = TI_CLK_GATE,
3998 .data = &dss_tv_fck_data,
4001 static struct ti_clk_gate mcbsp5_ick_data = {
4002 .parent = "core_l4_ick",
4005 .module = TI_CLKM_CM,
4006 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4009 static struct ti_clk mcbsp5_ick = {
4010 .name = "mcbsp5_ick",
4011 .clkdm_name = "core_l4_clkdm",
4012 .type = TI_CLK_GATE,
4013 .data = &mcbsp5_ick_data,
4016 static struct ti_clk_gate mcspi1_ick_data = {
4017 .parent = "core_l4_ick",
4020 .module = TI_CLKM_CM,
4021 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4024 static struct ti_clk mcspi1_ick = {
4025 .name = "mcspi1_ick",
4026 .clkdm_name = "core_l4_clkdm",
4027 .type = TI_CLK_GATE,
4028 .data = &mcspi1_ick_data,
4031 static struct ti_clk_gate d2d_26m_fck_data = {
4035 .module = TI_CLKM_CM,
4039 static struct ti_clk d2d_26m_fck = {
4040 .name = "d2d_26m_fck",
4041 .clkdm_name = "d2d_clkdm",
4042 .type = TI_CLK_GATE,
4043 .data = &d2d_26m_fck_data,
4046 static struct ti_clk_gate wdt3_ick_data = {
4047 .parent = "per_l4_ick",
4050 .module = TI_CLKM_CM,
4051 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4054 static struct ti_clk wdt3_ick = {
4056 .clkdm_name = "per_clkdm",
4057 .type = TI_CLK_GATE,
4058 .data = &wdt3_ick_data,
4061 static struct ti_clk_divider pclkx2_fck_data = {
4062 .parent = "emu_src_ck",
4066 .module = TI_CLKM_CM,
4067 .flags = CLKF_INDEX_STARTS_AT_ONE,
4070 static struct ti_clk pclkx2_fck = {
4071 .name = "pclkx2_fck",
4072 .type = TI_CLK_DIVIDER,
4073 .data = &pclkx2_fck_data,
4076 static struct ti_clk_gate sha12_ick_data = {
4077 .parent = "core_l4_ick",
4080 .module = TI_CLKM_CM,
4081 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4084 static struct ti_clk sha12_ick = {
4085 .name = "sha12_ick",
4086 .clkdm_name = "core_l4_clkdm",
4087 .type = TI_CLK_GATE,
4088 .data = &sha12_ick_data,
4091 static struct ti_clk_gate emac_fck_data = {
4092 .parent = "rmii_ck",
4095 .module = TI_CLKM_SCRM,
4098 static struct ti_clk emac_fck = {
4100 .type = TI_CLK_GATE,
4101 .data = &emac_fck_data,
4104 static struct ti_clk_composite gpt10_fck_data = {
4105 .mux = &gpt10_mux_fck_data,
4106 .gate = &gpt10_gate_fck_data,
4109 static struct ti_clk gpt10_fck = {
4110 .name = "gpt10_fck",
4111 .type = TI_CLK_COMPOSITE,
4112 .data = &gpt10_fck_data,
4115 static struct ti_clk_gate wdt2_fck_data = {
4116 .parent = "wkup_32k_fck",
4119 .module = TI_CLKM_CM,
4123 static struct ti_clk wdt2_fck = {
4125 .clkdm_name = "wkup_clkdm",
4126 .type = TI_CLK_GATE,
4127 .data = &wdt2_fck_data,
4130 static struct ti_clk_gate cam_ick_data = {
4134 .module = TI_CLKM_CM,
4135 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
4138 static struct ti_clk cam_ick = {
4140 .clkdm_name = "cam_clkdm",
4141 .type = TI_CLK_GATE,
4142 .data = &cam_ick_data,
4145 static struct ti_clk_gate ssi_ick_3430es2_data = {
4146 .parent = "ssi_l4_ick",
4149 .module = TI_CLKM_CM,
4150 .flags = CLKF_SSI | CLKF_OMAP3 | CLKF_INTERFACE,
4153 static struct ti_clk ssi_ick_3430es2 = {
4155 .clkdm_name = "core_l4_clkdm",
4156 .type = TI_CLK_GATE,
4157 .data = &ssi_ick_3430es2_data,
4160 static struct ti_clk_gate gpio4_ick_data = {
4161 .parent = "per_l4_ick",
4164 .module = TI_CLKM_CM,
4165 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4168 static struct ti_clk gpio4_ick = {
4169 .name = "gpio4_ick",
4170 .clkdm_name = "per_clkdm",
4171 .type = TI_CLK_GATE,
4172 .data = &gpio4_ick_data,
4175 static struct ti_clk_gate wdt1_ick_data = {
4176 .parent = "wkup_l4_ick",
4179 .module = TI_CLKM_CM,
4180 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4183 static struct ti_clk wdt1_ick = {
4185 .clkdm_name = "wkup_clkdm",
4186 .type = TI_CLK_GATE,
4187 .data = &wdt1_ick_data,
4190 static struct ti_clk_gate rng_ick_data = {
4191 .parent = "security_l4_ick2",
4194 .module = TI_CLKM_CM,
4195 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4198 static struct ti_clk rng_ick = {
4200 .type = TI_CLK_GATE,
4201 .data = &rng_ick_data,
4204 static struct ti_clk_gate icr_ick_data = {
4205 .parent = "core_l4_ick",
4208 .module = TI_CLKM_CM,
4209 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4212 static struct ti_clk icr_ick = {
4214 .clkdm_name = "core_l4_clkdm",
4215 .type = TI_CLK_GATE,
4216 .data = &icr_ick_data,
4219 static struct ti_clk_gate sgx_ick_data = {
4223 .module = TI_CLKM_CM,
4227 static struct ti_clk sgx_ick = {
4229 .clkdm_name = "sgx_clkdm",
4230 .type = TI_CLK_GATE,
4231 .data = &sgx_ick_data,
4234 static struct ti_clk_divider sys_clkout2_data = {
4235 .parent = "clkout2_src_ck",
4239 .module = TI_CLKM_CM,
4240 .flags = CLKF_INDEX_POWER_OF_TWO,
4243 static struct ti_clk sys_clkout2 = {
4244 .name = "sys_clkout2",
4245 .type = TI_CLK_DIVIDER,
4246 .data = &sys_clkout2_data,
4249 static struct ti_clk_alias omap34xx_omap36xx_clks[] = {
4250 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
4251 CLK(NULL, "aes1_ick", &aes1_ick),
4252 CLK("omap_rng", "ick", &rng_ick),
4253 CLK("omap3-rom-rng", "ick", &rng_ick),
4254 CLK(NULL, "sha11_ick", &sha11_ick),
4255 CLK(NULL, "des1_ick", &des1_ick),
4256 CLK(NULL, "cam_mclk", &cam_mclk),
4257 CLK(NULL, "cam_ick", &cam_ick),
4258 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
4259 CLK(NULL, "security_l3_ick", &security_l3_ick),
4260 CLK(NULL, "pka_ick", &pka_ick),
4261 CLK(NULL, "icr_ick", &icr_ick),
4262 CLK(NULL, "des2_ick", &des2_ick),
4263 CLK(NULL, "mspro_ick", &mspro_ick),
4264 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
4265 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
4266 CLK(NULL, "sr1_fck", &sr1_fck),
4267 CLK(NULL, "sr2_fck", &sr2_fck),
4268 CLK(NULL, "sr_l4_ick", &sr_l4_ick),
4269 CLK(NULL, "dpll2_fck", &dpll2_fck),
4270 CLK(NULL, "dpll2_ck", &dpll2_ck),
4271 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
4272 CLK(NULL, "iva2_ck", &iva2_ck),
4273 CLK(NULL, "modem_fck", &modem_fck),
4274 CLK(NULL, "sad2d_ick", &sad2d_ick),
4275 CLK(NULL, "mad2d_ick", &mad2d_ick),
4276 CLK(NULL, "mspro_fck", &mspro_fck),
4280 static struct ti_clk_alias omap36xx_omap3430es2plus_clks[] = {
4281 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
4282 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
4283 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
4284 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
4285 CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
4286 CLK(NULL, "sys_d2_ck", &sys_d2_ck),
4287 CLK(NULL, "omap_96m_d2_fck", &omap_96m_d2_fck),
4288 CLK(NULL, "omap_96m_d4_fck", &omap_96m_d4_fck),
4289 CLK(NULL, "omap_96m_d8_fck", &omap_96m_d8_fck),
4290 CLK(NULL, "omap_96m_d10_fck", &omap_96m_d10_fck),
4291 CLK(NULL, "dpll5_m2_d4_ck", &dpll5_m2_d4_ck),
4292 CLK(NULL, "dpll5_m2_d8_ck", &dpll5_m2_d8_ck),
4293 CLK(NULL, "dpll5_m2_d16_ck", &dpll5_m2_d16_ck),
4294 CLK(NULL, "dpll5_m2_d20_ck", &dpll5_m2_d20_ck),
4295 CLK(NULL, "usim_fck", &usim_fck),
4296 CLK(NULL, "usim_ick", &usim_ick),
4300 static struct ti_clk_alias omap3xxx_clks[] = {
4301 CLK(NULL, "apb_pclk", &dummy_apb_pclk),
4302 CLK(NULL, "omap_32k_fck", &omap_32k_fck),
4303 CLK(NULL, "virt_12m_ck", &virt_12m_ck),
4304 CLK(NULL, "virt_13m_ck", &virt_13m_ck),
4305 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
4306 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
4307 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
4308 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
4309 CLK(NULL, "osc_sys_ck", &osc_sys_ck),
4310 CLK("twl", "fck", &osc_sys_ck),
4311 CLK(NULL, "sys_ck", &sys_ck),
4312 CLK(NULL, "timer_sys_ck", &sys_ck),
4313 CLK(NULL, "dpll4_ck", &dpll4_ck),
4314 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
4315 CLK(NULL, "dpll4_m2x2_mul_ck", &dpll4_m2x2_mul_ck),
4316 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
4317 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
4318 CLK(NULL, "dpll3_ck", &dpll3_ck),
4319 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
4320 CLK(NULL, "dpll3_m3x2_mul_ck", &dpll3_m3x2_mul_ck),
4321 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
4322 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
4323 CLK(NULL, "sys_altclk", &sys_altclk),
4324 CLK(NULL, "sys_clkout1", &sys_clkout1),
4325 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
4326 CLK(NULL, "core_ck", &core_ck),
4327 CLK(NULL, "dpll1_fck", &dpll1_fck),
4328 CLK(NULL, "dpll1_ck", &dpll1_ck),
4329 CLK(NULL, "cpufreq_ck", &dpll1_ck),
4330 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
4331 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
4332 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
4333 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
4334 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
4335 CLK(NULL, "cm_96m_fck", &cm_96m_fck),
4336 CLK(NULL, "omap_96m_fck", &omap_96m_fck),
4337 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
4338 CLK(NULL, "dpll4_m3x2_mul_ck", &dpll4_m3x2_mul_ck),
4339 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
4340 CLK(NULL, "omap_54m_fck", &omap_54m_fck),
4341 CLK(NULL, "cm_96m_d2_fck", &cm_96m_d2_fck),
4342 CLK(NULL, "omap_48m_fck", &omap_48m_fck),
4343 CLK(NULL, "omap_12m_fck", &omap_12m_fck),
4344 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
4345 CLK(NULL, "dpll4_m4x2_mul_ck", &dpll4_m4x2_mul_ck),
4346 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
4347 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
4348 CLK(NULL, "dpll4_m5x2_mul_ck", &dpll4_m5x2_mul_ck),
4349 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
4350 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
4351 CLK(NULL, "dpll4_m6x2_mul_ck", &dpll4_m6x2_mul_ck),
4352 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
4353 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
4354 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
4355 CLK(NULL, "sys_clkout2", &sys_clkout2),
4356 CLK(NULL, "corex2_fck", &corex2_fck),
4357 CLK(NULL, "mpu_ck", &mpu_ck),
4358 CLK(NULL, "arm_fck", &arm_fck),
4359 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
4360 CLK(NULL, "l3_ick", &l3_ick),
4361 CLK(NULL, "l4_ick", &l4_ick),
4362 CLK(NULL, "rm_ick", &rm_ick),
4363 CLK(NULL, "timer_32k_ck", &omap_32k_fck),
4364 CLK(NULL, "gpt10_fck", &gpt10_fck),
4365 CLK(NULL, "gpt11_fck", &gpt11_fck),
4366 CLK(NULL, "core_96m_fck", &core_96m_fck),
4367 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
4368 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
4369 CLK(NULL, "i2c3_fck", &i2c3_fck),
4370 CLK(NULL, "i2c2_fck", &i2c2_fck),
4371 CLK(NULL, "i2c1_fck", &i2c1_fck),
4372 CLK(NULL, "core_48m_fck", &core_48m_fck),
4373 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
4374 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
4375 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
4376 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
4377 CLK(NULL, "uart2_fck", &uart2_fck),
4378 CLK(NULL, "uart1_fck", &uart1_fck),
4379 CLK(NULL, "core_12m_fck", &core_12m_fck),
4380 CLK("omap_hdq.0", "fck", &hdq_fck),
4381 CLK(NULL, "hdq_fck", &hdq_fck),
4382 CLK(NULL, "core_l3_ick", &core_l3_ick),
4383 CLK(NULL, "sdrc_ick", &sdrc_ick),
4384 CLK(NULL, "gpmc_fck", &gpmc_fck),
4385 CLK(NULL, "core_l4_ick", &core_l4_ick),
4386 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
4387 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
4388 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
4389 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
4390 CLK("omap_hdq.0", "ick", &hdq_ick),
4391 CLK(NULL, "hdq_ick", &hdq_ick),
4392 CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
4393 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
4394 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
4395 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
4396 CLK(NULL, "mcspi4_ick", &mcspi4_ick),
4397 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
4398 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
4399 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
4400 CLK("omap_i2c.3", "ick", &i2c3_ick),
4401 CLK("omap_i2c.2", "ick", &i2c2_ick),
4402 CLK("omap_i2c.1", "ick", &i2c1_ick),
4403 CLK(NULL, "i2c3_ick", &i2c3_ick),
4404 CLK(NULL, "i2c2_ick", &i2c2_ick),
4405 CLK(NULL, "i2c1_ick", &i2c1_ick),
4406 CLK(NULL, "uart2_ick", &uart2_ick),
4407 CLK(NULL, "uart1_ick", &uart1_ick),
4408 CLK(NULL, "gpt11_ick", &gpt11_ick),
4409 CLK(NULL, "gpt10_ick", &gpt10_ick),
4410 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
4411 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
4412 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
4413 CLK(NULL, "dss_tv_fck", &dss_tv_fck),
4414 CLK(NULL, "dss_96m_fck", &dss_96m_fck),
4415 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
4416 CLK(NULL, "init_60m_fclk", &dummy_ck),
4417 CLK(NULL, "gpt1_fck", &gpt1_fck),
4418 CLK(NULL, "aes2_ick", &aes2_ick),
4419 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
4420 CLK(NULL, "gpio1_dbck", &gpio1_dbck),
4421 CLK(NULL, "sha12_ick", &sha12_ick),
4422 CLK(NULL, "wdt2_fck", &wdt2_fck),
4423 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
4424 CLK("omap_wdt", "ick", &wdt2_ick),
4425 CLK(NULL, "wdt2_ick", &wdt2_ick),
4426 CLK(NULL, "wdt1_ick", &wdt1_ick),
4427 CLK(NULL, "gpio1_ick", &gpio1_ick),
4428 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
4429 CLK(NULL, "gpt12_ick", &gpt12_ick),
4430 CLK(NULL, "gpt1_ick", &gpt1_ick),
4431 CLK(NULL, "per_96m_fck", &per_96m_fck),
4432 CLK(NULL, "per_48m_fck", &per_48m_fck),
4433 CLK(NULL, "uart3_fck", &uart3_fck),
4434 CLK(NULL, "gpt2_fck", &gpt2_fck),
4435 CLK(NULL, "gpt3_fck", &gpt3_fck),
4436 CLK(NULL, "gpt4_fck", &gpt4_fck),
4437 CLK(NULL, "gpt5_fck", &gpt5_fck),
4438 CLK(NULL, "gpt6_fck", &gpt6_fck),
4439 CLK(NULL, "gpt7_fck", &gpt7_fck),
4440 CLK(NULL, "gpt8_fck", &gpt8_fck),
4441 CLK(NULL, "gpt9_fck", &gpt9_fck),
4442 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
4443 CLK(NULL, "gpio6_dbck", &gpio6_dbck),
4444 CLK(NULL, "gpio5_dbck", &gpio5_dbck),
4445 CLK(NULL, "gpio4_dbck", &gpio4_dbck),
4446 CLK(NULL, "gpio3_dbck", &gpio3_dbck),
4447 CLK(NULL, "gpio2_dbck", &gpio2_dbck),
4448 CLK(NULL, "wdt3_fck", &wdt3_fck),
4449 CLK(NULL, "per_l4_ick", &per_l4_ick),
4450 CLK(NULL, "gpio6_ick", &gpio6_ick),
4451 CLK(NULL, "gpio5_ick", &gpio5_ick),
4452 CLK(NULL, "gpio4_ick", &gpio4_ick),
4453 CLK(NULL, "gpio3_ick", &gpio3_ick),
4454 CLK(NULL, "gpio2_ick", &gpio2_ick),
4455 CLK(NULL, "wdt3_ick", &wdt3_ick),
4456 CLK(NULL, "uart3_ick", &uart3_ick),
4457 CLK(NULL, "uart4_ick", &uart4_ick),
4458 CLK(NULL, "gpt9_ick", &gpt9_ick),
4459 CLK(NULL, "gpt8_ick", &gpt8_ick),
4460 CLK(NULL, "gpt7_ick", &gpt7_ick),
4461 CLK(NULL, "gpt6_ick", &gpt6_ick),
4462 CLK(NULL, "gpt5_ick", &gpt5_ick),
4463 CLK(NULL, "gpt4_ick", &gpt4_ick),
4464 CLK(NULL, "gpt3_ick", &gpt3_ick),
4465 CLK(NULL, "gpt2_ick", &gpt2_ick),
4466 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
4467 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
4468 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
4469 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
4470 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
4471 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
4472 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
4473 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
4474 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
4475 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick),
4476 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
4477 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
4478 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
4479 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
4480 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
4481 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
4482 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
4483 CLK("etb", "emu_src_ck", &emu_src_ck),
4484 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
4485 CLK(NULL, "emu_src_ck", &emu_src_ck),
4486 CLK(NULL, "pclk_fck", &pclk_fck),
4487 CLK(NULL, "pclkx2_fck", &pclkx2_fck),
4488 CLK(NULL, "atclk_fck", &atclk_fck),
4489 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
4490 CLK(NULL, "traceclk_fck", &traceclk_fck),
4491 CLK(NULL, "secure_32k_fck", &secure_32k_fck),
4492 CLK(NULL, "gpt12_fck", &gpt12_fck),
4493 CLK(NULL, "wdt1_fck", &wdt1_fck),
4497 static struct ti_clk_alias omap36xx_am35xx_omap3430es2plus_clks[] = {
4498 CLK(NULL, "dpll5_ck", &dpll5_ck),
4499 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
4500 CLK(NULL, "core_d3_ck", &core_d3_ck),
4501 CLK(NULL, "core_d4_ck", &core_d4_ck),
4502 CLK(NULL, "core_d6_ck", &core_d6_ck),
4503 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
4504 CLK(NULL, "core_d2_ck", &core_d2_ck),
4505 CLK(NULL, "corex2_d3_fck", &corex2_d3_fck),
4506 CLK(NULL, "corex2_d5_fck", &corex2_d5_fck),
4507 CLK(NULL, "sgx_fck", &sgx_fck),
4508 CLK(NULL, "sgx_ick", &sgx_ick),
4509 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
4510 CLK(NULL, "ts_fck", &ts_fck),
4511 CLK(NULL, "usbtll_fck", &usbtll_fck),
4512 CLK(NULL, "usbtll_ick", &usbtll_ick),
4513 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
4514 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
4515 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
4516 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
4517 CLK("omapdss_dss", "ick", &dss_ick_3430es2),
4518 CLK(NULL, "dss_ick", &dss_ick_3430es2),
4519 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
4520 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
4521 CLK(NULL, "usbhost_ick", &usbhost_ick),
4525 static struct ti_clk_alias omap3430es1_clks[] = {
4526 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
4527 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
4528 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
4529 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
4530 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
4531 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
4532 CLK(NULL, "fshostusb_fck", &fshostusb_fck),
4533 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
4534 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
4535 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
4536 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
4537 CLK(NULL, "fac_ick", &fac_ick),
4538 CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
4539 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
4540 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
4541 CLK("omapdss_dss", "ick", &dss_ick_3430es1),
4542 CLK(NULL, "dss_ick", &dss_ick_3430es1),
4546 static struct ti_clk_alias omap36xx_clks[] = {
4547 CLK(NULL, "uart4_fck", &uart4_fck),
4551 static struct ti_clk_alias am35xx_clks[] = {
4552 CLK(NULL, "ipss_ick", &ipss_ick),
4553 CLK(NULL, "rmii_ck", &rmii_ck),
4554 CLK(NULL, "pclk_ck", &pclk_ck),
4555 CLK(NULL, "emac_ick", &emac_ick),
4556 CLK(NULL, "emac_fck", &emac_fck),
4557 CLK("davinci_emac.0", NULL, &emac_ick),
4558 CLK("davinci_mdio.0", NULL, &emac_fck),
4559 CLK("vpfe-capture", "master", &vpfe_ick),
4560 CLK("vpfe-capture", "slave", &vpfe_fck),
4561 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
4562 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
4563 CLK(NULL, "hecc_ck", &hecc_ck),
4564 CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
4565 CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
4569 static struct ti_clk *omap36xx_clk_patches[] = {
4570 &dpll4_m3x2_ck_omap36xx,
4571 &dpll3_m3x2_ck_omap36xx,
4572 &dpll4_m6x2_ck_omap36xx,
4573 &dpll4_m2x2_ck_omap36xx,
4574 &dpll4_m5x2_ck_omap36xx,
4579 static const char *enable_init_clks[] = {
4585 static void __init omap3_clk_legacy_common_init(void)
4587 omap2_clk_disable_autoidle_all();
4589 omap2_clk_enable_init_clocks(enable_init_clks,
4590 ARRAY_SIZE(enable_init_clks));
4592 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
4593 (clk_get_rate(osc_sys_ck.clk) / 1000000),
4594 (clk_get_rate(osc_sys_ck.clk) / 100000) % 10,
4595 (clk_get_rate(core_ck.clk) / 1000000),
4596 (clk_get_rate(arm_fck.clk) / 1000000));
4599 int __init omap3430es1_clk_legacy_init(void)
4603 r = ti_clk_register_legacy_clks(omap3430es1_clks);
4604 r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4605 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4607 omap3_clk_legacy_common_init();
4612 int __init omap3430_clk_legacy_init(void)
4616 r = ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4617 r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
4618 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4619 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4621 omap3_clk_legacy_common_init();
4622 omap3_clk_lock_dpll5();
4627 int __init omap36xx_clk_legacy_init(void)
4631 ti_clk_patch_legacy_clks(omap36xx_clk_patches);
4632 r = ti_clk_register_legacy_clks(omap36xx_clks);
4633 r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
4634 r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4635 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4636 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4638 omap3_clk_legacy_common_init();
4639 omap3_clk_lock_dpll5();
4644 int __init am35xx_clk_legacy_init(void)
4648 r = ti_clk_register_legacy_clks(am35xx_clks);
4649 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4650 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4652 omap3_clk_legacy_common_init();
4653 omap3_clk_lock_dpll5();