2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License as
4 * published by the Free Software Foundation version 2.
6 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
7 * kind, whether express or implied; without even the implied warranty
8 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/math64.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/string.h>
22 #define ADPLL_PLLSS_MMR_LOCK_OFFSET 0x00 /* Managed by MPPULL */
23 #define ADPLL_PLLSS_MMR_LOCK_ENABLED 0x1f125B64
24 #define ADPLL_PLLSS_MMR_UNLOCK_MAGIC 0x1eda4c3d
26 #define ADPLL_PWRCTRL_OFFSET 0x00
27 #define ADPLL_PWRCTRL_PONIN 5
28 #define ADPLL_PWRCTRL_PGOODIN 4
29 #define ADPLL_PWRCTRL_RET 3
30 #define ADPLL_PWRCTRL_ISORET 2
31 #define ADPLL_PWRCTRL_ISOSCAN 1
32 #define ADPLL_PWRCTRL_OFFMODE 0
34 #define ADPLL_CLKCTRL_OFFSET 0x04
35 #define ADPLL_CLKCTRL_CLKDCOLDOEN 29
36 #define ADPLL_CLKCTRL_IDLE 23
37 #define ADPLL_CLKCTRL_CLKOUTEN 20
38 #define ADPLL_CLKINPHIFSEL_ADPLL_S 19 /* REVISIT: which bit? */
39 #define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
40 #define ADPLL_CLKCTRL_ULOWCLKEN 18
41 #define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ 17
42 #define ADPLL_CLKCTRL_M2PWDNZ 16
43 #define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S 15
44 #define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
45 #define ADPLL_CLKCTRL_LPMODE_ADPLL_S 12
46 #define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S 10
47 #define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
48 #define ADPLL_CLKCTRL_TINITZ 0
50 #define ADPLL_TENABLE_OFFSET 0x08
51 #define ADPLL_TENABLEDIV_OFFSET 0x8c
53 #define ADPLL_M2NDIV_OFFSET 0x10
54 #define ADPLL_M2NDIV_M2 16
55 #define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH 5
56 #define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH 7
58 #define ADPLL_MN2DIV_OFFSET 0x14
59 #define ADPLL_MN2DIV_N2 16
61 #define ADPLL_FRACDIV_OFFSET 0x18
62 #define ADPLL_FRACDIV_REGSD 24
63 #define ADPLL_FRACDIV_FRACTIONALM 0
64 #define ADPLL_FRACDIV_FRACTIONALM_MASK 0x3ffff
66 #define ADPLL_BWCTRL_OFFSET 0x1c
67 #define ADPLL_BWCTRL_BWCONTROL 1
68 #define ADPLL_BWCTRL_BW_INCR_DECRZ 0
70 #define ADPLL_RESERVED_OFFSET 0x20
72 #define ADPLL_STATUS_OFFSET 0x24
73 #define ADPLL_STATUS_PONOUT 31
74 #define ADPLL_STATUS_PGOODOUT 30
75 #define ADPLL_STATUS_LDOPWDN 29
76 #define ADPLL_STATUS_RECAL_BSTATUS3 28
77 #define ADPLL_STATUS_RECAL_OPPIN 27
78 #define ADPLL_STATUS_PHASELOCK 10
79 #define ADPLL_STATUS_FREQLOCK 9
80 #define ADPLL_STATUS_BYPASSACK 8
81 #define ADPLL_STATUS_LOSSREF 6
82 #define ADPLL_STATUS_CLKOUTENACK 5
83 #define ADPLL_STATUS_LOCK2 4
84 #define ADPLL_STATUS_M2CHANGEACK 3
85 #define ADPLL_STATUS_HIGHJITTER 1
86 #define ADPLL_STATUS_BYPASS 0
87 #define ADPLL_STATUS_PREPARED_MASK (BIT(ADPLL_STATUS_PHASELOCK) | \
88 BIT(ADPLL_STATUS_FREQLOCK))
90 #define ADPLL_M3DIV_OFFSET 0x28 /* Only on MPUPLL */
91 #define ADPLL_M3DIV_M3 0
92 #define ADPLL_M3DIV_M3_WIDTH 5
93 #define ADPLL_M3DIV_M3_MASK 0x1f
95 #define ADPLL_RAMPCTRL_OFFSET 0x2c /* Only on MPUPLL */
96 #define ADPLL_RAMPCTRL_CLKRAMPLEVEL 19
97 #define ADPLL_RAMPCTRL_CLKRAMPRATE 16
98 #define ADPLL_RAMPCTRL_RELOCK_RAMP_EN 0
100 #define MAX_ADPLL_INPUTS 3
101 #define MAX_ADPLL_OUTPUTS 4
102 #define ADPLL_MAX_RETRIES 5
104 #define to_dco(_hw) container_of(_hw, struct ti_adpll_dco_data, hw)
105 #define to_adpll(_hw) container_of(_hw, struct ti_adpll_data, dco)
106 #define to_clkout(_hw) container_of(_hw, struct ti_adpll_clkout_data, hw)
108 enum ti_adpll_clocks {
122 #define TI_ADPLL_NR_CLOCKS (TI_ADPLL_M3 + 1)
124 enum ti_adpll_inputs {
130 enum ti_adpll_s_outputs {
131 TI_ADPLL_S_DCOCLKLDO,
134 TI_ADPLL_S_CLKOUTHIF,
137 enum ti_adpll_lj_outputs {
138 TI_ADPLL_LJ_CLKDCOLDO,
140 TI_ADPLL_LJ_CLKOUTLDO,
143 struct ti_adpll_platform_data {
144 const bool is_type_s;
145 const int nr_max_inputs;
146 const int nr_max_outputs;
147 const int output_index;
150 struct ti_adpll_clock {
152 struct clk_lookup *cl;
153 void (*unregister)(struct clk *clk);
156 struct ti_adpll_dco_data {
160 struct ti_adpll_clkout_data {
161 struct ti_adpll_data *adpll;
162 struct clk_gate gate;
166 struct ti_adpll_data {
168 const struct ti_adpll_platform_data *c;
169 struct device_node *np;
171 void __iomem *iobase;
173 spinlock_t lock; /* For ADPLL shared register access */
174 const char *parent_names[MAX_ADPLL_INPUTS];
175 struct clk *parent_clocks[MAX_ADPLL_INPUTS];
176 struct ti_adpll_clock *clocks;
177 struct clk_onecell_data outputs;
178 struct ti_adpll_dco_data dco;
181 static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d,
188 if (output_index >= 0) {
189 err = of_property_read_string_index(d->np,
190 "clock-output-names",
196 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s",
203 #define ADPLL_MAX_CON_ID 16 /* See MAX_CON_ID */
205 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
206 int index, int output_index, const char *name,
207 void (*unregister)(struct clk *clk))
209 struct clk_lookup *cl;
210 const char *postfix = NULL;
211 char con_id[ADPLL_MAX_CON_ID];
213 d->clocks[index].clk = clock;
214 d->clocks[index].unregister = unregister;
216 /* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
217 postfix = strrchr(name, '.');
218 if (postfix && strlen(postfix) > 1) {
219 if (strlen(postfix) > ADPLL_MAX_CON_ID)
220 dev_warn(d->dev, "clock %s con_id lookup may fail\n",
222 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1);
223 cl = clkdev_create(clock, con_id, NULL);
226 d->clocks[index].cl = cl;
228 dev_warn(d->dev, "no con_id for clock %s\n", name);
231 if (output_index < 0)
234 d->outputs.clks[output_index] = clock;
235 d->outputs.clk_num++;
240 static int ti_adpll_init_divider(struct ti_adpll_data *d,
241 enum ti_adpll_clocks index,
242 int output_index, char *name,
243 struct clk *parent_clock,
246 u8 clk_divider_flags)
248 const char *child_name;
249 const char *parent_name;
252 child_name = ti_adpll_clk_get_name(d, output_index, name);
256 parent_name = __clk_get_name(parent_clock);
257 clock = clk_register_divider(d->dev, child_name, parent_name, 0,
258 reg, shift, width, clk_divider_flags,
261 dev_err(d->dev, "failed to register divider %s: %li\n",
262 name, PTR_ERR(clock));
263 return PTR_ERR(clock);
266 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
267 clk_unregister_divider);
270 static int ti_adpll_init_mux(struct ti_adpll_data *d,
271 enum ti_adpll_clocks index,
272 char *name, struct clk *clk0,
277 const char *child_name;
278 const char *parents[2];
281 child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
284 parents[0] = __clk_get_name(clk0);
285 parents[1] = __clk_get_name(clk1);
286 clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
287 reg, shift, 1, 0, &d->lock);
289 dev_err(d->dev, "failed to register mux %s: %li\n",
290 name, PTR_ERR(clock));
291 return PTR_ERR(clock);
294 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
298 static int ti_adpll_init_gate(struct ti_adpll_data *d,
299 enum ti_adpll_clocks index,
300 int output_index, char *name,
301 struct clk *parent_clock,
306 const char *child_name;
307 const char *parent_name;
310 child_name = ti_adpll_clk_get_name(d, output_index, name);
314 parent_name = __clk_get_name(parent_clock);
315 clock = clk_register_gate(d->dev, child_name, parent_name, 0,
316 reg, bit_idx, clk_gate_flags,
319 dev_err(d->dev, "failed to register gate %s: %li\n",
320 name, PTR_ERR(clock));
321 return PTR_ERR(clock);
324 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
325 clk_unregister_gate);
328 static int ti_adpll_init_fixed_factor(struct ti_adpll_data *d,
329 enum ti_adpll_clocks index,
331 struct clk *parent_clock,
335 const char *child_name;
336 const char *parent_name;
339 child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
343 parent_name = __clk_get_name(parent_clock);
344 clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
347 return PTR_ERR(clock);
349 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
353 static void ti_adpll_set_idle_bypass(struct ti_adpll_data *d)
358 spin_lock_irqsave(&d->lock, flags);
359 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
360 v |= BIT(ADPLL_CLKCTRL_IDLE);
361 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
362 spin_unlock_irqrestore(&d->lock, flags);
365 static void ti_adpll_clear_idle_bypass(struct ti_adpll_data *d)
370 spin_lock_irqsave(&d->lock, flags);
371 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
372 v &= ~BIT(ADPLL_CLKCTRL_IDLE);
373 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
374 spin_unlock_irqrestore(&d->lock, flags);
377 static bool ti_adpll_clock_is_bypass(struct ti_adpll_data *d)
381 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
383 return v & BIT(ADPLL_STATUS_BYPASS);
387 * Locked and bypass are not actually mutually exclusive: if you only care
388 * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
389 * the PLL, resulting in status (FREQLOCK | PHASELOCK | BYPASS) after lock.
391 static bool ti_adpll_is_locked(struct ti_adpll_data *d)
393 u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
395 return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK;
398 static int ti_adpll_wait_lock(struct ti_adpll_data *d)
400 int retries = ADPLL_MAX_RETRIES;
403 if (ti_adpll_is_locked(d))
405 usleep_range(200, 300);
408 dev_err(d->dev, "pll failed to lock\n");
412 static int ti_adpll_prepare(struct clk_hw *hw)
414 struct ti_adpll_dco_data *dco = to_dco(hw);
415 struct ti_adpll_data *d = to_adpll(dco);
417 ti_adpll_clear_idle_bypass(d);
418 ti_adpll_wait_lock(d);
423 static void ti_adpll_unprepare(struct clk_hw *hw)
425 struct ti_adpll_dco_data *dco = to_dco(hw);
426 struct ti_adpll_data *d = to_adpll(dco);
428 ti_adpll_set_idle_bypass(d);
431 static int ti_adpll_is_prepared(struct clk_hw *hw)
433 struct ti_adpll_dco_data *dco = to_dco(hw);
434 struct ti_adpll_data *d = to_adpll(dco);
436 return ti_adpll_is_locked(d);
440 * Note that the DCO clock is never subject to bypass: if the PLL is off,
443 static unsigned long ti_adpll_recalc_rate(struct clk_hw *hw,
444 unsigned long parent_rate)
446 struct ti_adpll_dco_data *dco = to_dco(hw);
447 struct ti_adpll_data *d = to_adpll(dco);
448 u32 frac_m, divider, v;
452 if (ti_adpll_clock_is_bypass(d))
455 spin_lock_irqsave(&d->lock, flags);
456 frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET);
457 frac_m &= ADPLL_FRACDIV_FRACTIONALM_MASK;
458 rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;
461 divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
462 spin_unlock_irqrestore(&d->lock, flags);
464 do_div(rate, divider);
466 if (d->c->is_type_s) {
467 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
468 if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S))
476 /* PLL parent is always clkinp, bypass only affects the children */
477 static u8 ti_adpll_get_parent(struct clk_hw *hw)
482 static const struct clk_ops ti_adpll_ops = {
483 .prepare = ti_adpll_prepare,
484 .unprepare = ti_adpll_unprepare,
485 .is_prepared = ti_adpll_is_prepared,
486 .recalc_rate = ti_adpll_recalc_rate,
487 .get_parent = ti_adpll_get_parent,
490 static int ti_adpll_init_dco(struct ti_adpll_data *d)
492 struct clk_init_data init;
497 d->outputs.clks = devm_kcalloc(d->dev,
499 sizeof(struct clk *),
501 if (!d->outputs.clks)
504 if (d->c->output_index < 0)
509 init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix);
513 init.parent_names = d->parent_names;
514 init.num_parents = d->c->nr_max_inputs;
515 init.ops = &ti_adpll_ops;
516 init.flags = CLK_GET_RATE_NOCACHE;
517 d->dco.hw.init = &init;
524 /* Internal input clock divider N2 */
525 err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2",
526 d->parent_clocks[TI_ADPLL_CLKINP],
527 d->regs + ADPLL_MN2DIV_OFFSET,
528 ADPLL_MN2DIV_N2, width, 0);
532 clock = devm_clk_register(d->dev, &d->dco.hw);
534 return PTR_ERR(clock);
536 return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
540 static int ti_adpll_clkout_enable(struct clk_hw *hw)
542 struct ti_adpll_clkout_data *co = to_clkout(hw);
543 struct clk_hw *gate_hw = &co->gate.hw;
545 __clk_hw_set_clk(gate_hw, hw);
547 return clk_gate_ops.enable(gate_hw);
550 static void ti_adpll_clkout_disable(struct clk_hw *hw)
552 struct ti_adpll_clkout_data *co = to_clkout(hw);
553 struct clk_hw *gate_hw = &co->gate.hw;
555 __clk_hw_set_clk(gate_hw, hw);
556 clk_gate_ops.disable(gate_hw);
559 static int ti_adpll_clkout_is_enabled(struct clk_hw *hw)
561 struct ti_adpll_clkout_data *co = to_clkout(hw);
562 struct clk_hw *gate_hw = &co->gate.hw;
564 __clk_hw_set_clk(gate_hw, hw);
566 return clk_gate_ops.is_enabled(gate_hw);
569 /* Setting PLL bypass puts clkout and clkoutx2 into bypass */
570 static u8 ti_adpll_clkout_get_parent(struct clk_hw *hw)
572 struct ti_adpll_clkout_data *co = to_clkout(hw);
573 struct ti_adpll_data *d = co->adpll;
575 return ti_adpll_clock_is_bypass(d);
578 static int ti_adpll_init_clkout(struct ti_adpll_data *d,
579 enum ti_adpll_clocks index,
580 int output_index, int gate_bit,
581 char *name, struct clk *clk0,
584 struct ti_adpll_clkout_data *co;
585 struct clk_init_data init;
587 const char *parent_names[2];
588 const char *child_name;
592 co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL);
597 err = of_property_read_string_index(d->np,
598 "clock-output-names",
604 ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL);
608 init.name = child_name;
610 init.flags = CLK_IS_BASIC;
612 parent_names[0] = __clk_get_name(clk0);
613 parent_names[1] = __clk_get_name(clk1);
614 init.parent_names = parent_names;
615 init.num_parents = 2;
617 ops->get_parent = ti_adpll_clkout_get_parent;
618 ops->determine_rate = __clk_mux_determine_rate;
620 co->gate.lock = &d->lock;
621 co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET;
622 co->gate.bit_idx = gate_bit;
623 ops->enable = ti_adpll_clkout_enable;
624 ops->disable = ti_adpll_clkout_disable;
625 ops->is_enabled = ti_adpll_clkout_is_enabled;
628 clock = devm_clk_register(d->dev, &co->hw);
630 dev_err(d->dev, "failed to register output %s: %li\n",
631 name, PTR_ERR(clock));
632 return PTR_ERR(clock);
635 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
639 static int ti_adpll_init_children_adpll_s(struct ti_adpll_data *d)
643 if (!d->c->is_type_s)
646 /* Internal mux, sources from divider N2 or clkinpulow */
647 err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
648 d->clocks[TI_ADPLL_N2].clk,
649 d->parent_clocks[TI_ADPLL_CLKINPULOW],
650 d->regs + ADPLL_CLKCTRL_OFFSET,
651 ADPLL_CLKCTRL_ULOWCLKEN);
655 /* Internal divider M2, sources DCO */
656 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2",
657 d->clocks[TI_ADPLL_DCO].clk,
658 d->regs + ADPLL_M2NDIV_OFFSET,
660 ADPLL_M2NDIV_M2_ADPLL_S_WIDTH,
661 CLK_DIVIDER_ONE_BASED);
665 /* Internal fixed divider, after M2 before clkout */
666 err = ti_adpll_init_fixed_factor(d, TI_ADPLL_DIV2, "div2",
667 d->clocks[TI_ADPLL_M2].clk,
672 /* Output clkout with a mux and gate, sources from div2 or bypass */
673 err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
674 ADPLL_CLKCTRL_CLKOUTEN, "clkout",
675 d->clocks[TI_ADPLL_DIV2].clk,
676 d->clocks[TI_ADPLL_BYPASS].clk);
680 /* Output clkoutx2 with a mux and gate, sources from M2 or bypass */
681 err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT2, TI_ADPLL_S_CLKOUTX2, 0,
682 "clkout2", d->clocks[TI_ADPLL_M2].clk,
683 d->clocks[TI_ADPLL_BYPASS].clk);
687 /* Internal mux, sources from DCO and clkinphif */
688 if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) {
689 err = ti_adpll_init_mux(d, TI_ADPLL_HIF, "hif",
690 d->clocks[TI_ADPLL_DCO].clk,
691 d->parent_clocks[TI_ADPLL_CLKINPHIF],
692 d->regs + ADPLL_CLKCTRL_OFFSET,
693 ADPLL_CLKINPHIFSEL_ADPLL_S);
698 /* Output clkouthif with a divider M3, sources from hif */
699 err = ti_adpll_init_divider(d, TI_ADPLL_M3, TI_ADPLL_S_CLKOUTHIF, "m3",
700 d->clocks[TI_ADPLL_HIF].clk,
701 d->regs + ADPLL_M3DIV_OFFSET,
703 ADPLL_M3DIV_M3_WIDTH,
704 CLK_DIVIDER_ONE_BASED);
708 /* Output clock dcoclkldo is the DCO */
713 static int ti_adpll_init_children_adpll_lj(struct ti_adpll_data *d)
720 /* Output clkdcoldo, gated output of DCO */
721 err = ti_adpll_init_gate(d, TI_ADPLL_DCO_GATE, TI_ADPLL_LJ_CLKDCOLDO,
722 "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk,
723 d->regs + ADPLL_CLKCTRL_OFFSET,
724 ADPLL_CLKCTRL_CLKDCOLDOEN, 0);
728 /* Internal divider M2, sources from DCO */
729 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV,
730 "m2", d->clocks[TI_ADPLL_DCO].clk,
731 d->regs + ADPLL_M2NDIV_OFFSET,
733 ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH,
734 CLK_DIVIDER_ONE_BASED);
738 /* Output clkoutldo, gated output of M2 */
739 err = ti_adpll_init_gate(d, TI_ADPLL_M2_GATE, TI_ADPLL_LJ_CLKOUTLDO,
740 "clkoutldo", d->clocks[TI_ADPLL_M2].clk,
741 d->regs + ADPLL_CLKCTRL_OFFSET,
742 ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ,
747 /* Internal mux, sources from divider N2 or clkinpulow */
748 err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
749 d->clocks[TI_ADPLL_N2].clk,
750 d->parent_clocks[TI_ADPLL_CLKINPULOW],
751 d->regs + ADPLL_CLKCTRL_OFFSET,
752 ADPLL_CLKCTRL_ULOWCLKEN);
756 /* Output clkout, sources M2 or bypass */
757 err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
758 ADPLL_CLKCTRL_CLKOUTEN, "clkout",
759 d->clocks[TI_ADPLL_M2].clk,
760 d->clocks[TI_ADPLL_BYPASS].clk);
767 static void ti_adpll_free_resources(struct ti_adpll_data *d)
771 for (i = TI_ADPLL_M3; i >= 0; i--) {
772 struct ti_adpll_clock *ac = &d->clocks[i];
774 if (!ac || IS_ERR_OR_NULL(ac->clk))
779 ac->unregister(ac->clk);
783 /* MPU PLL manages the lock register for all PLLs */
784 static void ti_adpll_unlock_all(void __iomem *reg)
788 v = readl_relaxed(reg);
789 if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED)
790 writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg);
793 static int ti_adpll_init_registers(struct ti_adpll_data *d)
795 int register_offset = 0;
797 if (d->c->is_type_s) {
799 ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET);
802 d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET;
807 static int ti_adpll_init_inputs(struct ti_adpll_data *d)
809 const char *error = "need at least %i inputs";
813 nr_inputs = of_clk_get_parent_count(d->np);
814 if (nr_inputs < d->c->nr_max_inputs) {
815 dev_err(d->dev, error, nr_inputs);
818 of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
820 clock = devm_clk_get(d->dev, d->parent_names[0]);
822 dev_err(d->dev, "could not get clkinp\n");
823 return PTR_ERR(clock);
825 d->parent_clocks[TI_ADPLL_CLKINP] = clock;
827 clock = devm_clk_get(d->dev, d->parent_names[1]);
829 dev_err(d->dev, "could not get clkinpulow clock\n");
830 return PTR_ERR(clock);
832 d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
834 if (d->c->is_type_s) {
835 clock = devm_clk_get(d->dev, d->parent_names[2]);
837 dev_err(d->dev, "could not get clkinphif clock\n");
838 return PTR_ERR(clock);
840 d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
846 static const struct ti_adpll_platform_data ti_adpll_type_s = {
848 .nr_max_inputs = MAX_ADPLL_INPUTS,
849 .nr_max_outputs = MAX_ADPLL_OUTPUTS,
850 .output_index = TI_ADPLL_S_DCOCLKLDO,
853 static const struct ti_adpll_platform_data ti_adpll_type_lj = {
855 .nr_max_inputs = MAX_ADPLL_INPUTS - 1,
856 .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
857 .output_index = -EINVAL,
860 static const struct of_device_id ti_adpll_match[] = {
861 { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
862 { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
865 MODULE_DEVICE_TABLE(of, ti_adpll_match);
867 static int ti_adpll_probe(struct platform_device *pdev)
869 struct device_node *node = pdev->dev.of_node;
870 struct device *dev = &pdev->dev;
871 const struct of_device_id *match;
872 const struct ti_adpll_platform_data *pdata;
873 struct ti_adpll_data *d;
874 struct resource *res;
877 match = of_match_device(ti_adpll_match, dev);
883 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
889 dev_set_drvdata(d->dev, d);
890 spin_lock_init(&d->lock);
892 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
897 d->iobase = devm_ioremap_resource(dev, res);
898 if (IS_ERR(d->iobase)) {
899 dev_err(dev, "could not get IO base: %li\n",
901 return PTR_ERR(d->iobase);
904 err = ti_adpll_init_registers(d);
908 err = ti_adpll_init_inputs(d);
912 d->clocks = devm_kcalloc(d->dev,
914 sizeof(struct ti_adpll_clock),
919 err = ti_adpll_init_dco(d);
921 dev_err(dev, "could not register dco: %i\n", err);
925 err = ti_adpll_init_children_adpll_s(d);
928 err = ti_adpll_init_children_adpll_lj(d);
932 err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs);
940 ti_adpll_free_resources(d);
945 static int ti_adpll_remove(struct platform_device *pdev)
947 struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev);
949 ti_adpll_free_resources(d);
954 static struct platform_driver ti_adpll_driver = {
957 .of_match_table = ti_adpll_match,
959 .probe = ti_adpll_probe,
960 .remove = ti_adpll_remove,
963 static int __init ti_adpll_init(void)
965 return platform_driver_register(&ti_adpll_driver);
967 core_initcall(ti_adpll_init);
969 static void __exit ti_adpll_exit(void)
971 platform_driver_unregister(&ti_adpll_driver);
973 module_exit(ti_adpll_exit);
975 MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
976 MODULE_ALIAS("platform:dm814-adpll-clock");
977 MODULE_AUTHOR("Tony LIndgren <tony@atomide.com>");
978 MODULE_LICENSE("GPL v2");