2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/clkdev.h>
22 #include <linux/of_address.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/mutex.h>
26 #include <linux/clk/tegra.h>
27 #include <dt-bindings/clock/tegra210-car.h>
28 #include <dt-bindings/reset/tegra210-car.h>
29 #include <linux/iopoll.h>
30 #include <soc/tegra/pmc.h>
36 * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register
37 * banks present in the Tegra210 CAR IP block. The banks are
38 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See
39 * periph_regs[] in drivers/clk/tegra/clk.c
41 #define TEGRA210_CAR_BANK_COUNT 7
43 #define CLK_SOURCE_CSITE 0x1d4
44 #define CLK_SOURCE_EMC 0x19c
45 #define CLK_SOURCE_SOR1 0x410
46 #define CLK_SOURCE_LA 0x1f8
47 #define CLK_SOURCE_SDMMC2 0x154
48 #define CLK_SOURCE_SDMMC4 0x164
50 #define PLLC_BASE 0x80
52 #define PLLC_MISC0 0x88
53 #define PLLC_MISC1 0x8c
54 #define PLLC_MISC2 0x5d0
55 #define PLLC_MISC3 0x5d4
57 #define PLLC2_BASE 0x4e8
58 #define PLLC2_MISC0 0x4ec
59 #define PLLC2_MISC1 0x4f0
60 #define PLLC2_MISC2 0x4f4
61 #define PLLC2_MISC3 0x4f8
63 #define PLLC3_BASE 0x4fc
64 #define PLLC3_MISC0 0x500
65 #define PLLC3_MISC1 0x504
66 #define PLLC3_MISC2 0x508
67 #define PLLC3_MISC3 0x50c
69 #define PLLM_BASE 0x90
70 #define PLLM_MISC1 0x98
71 #define PLLM_MISC2 0x9c
72 #define PLLP_BASE 0xa0
73 #define PLLP_MISC0 0xac
74 #define PLLP_MISC1 0x680
75 #define PLLA_BASE 0xb0
76 #define PLLA_MISC0 0xbc
77 #define PLLA_MISC1 0xb8
78 #define PLLA_MISC2 0x5d8
79 #define PLLD_BASE 0xd0
80 #define PLLD_MISC0 0xdc
81 #define PLLD_MISC1 0xd8
82 #define PLLU_BASE 0xc0
83 #define PLLU_OUTA 0xc4
84 #define PLLU_MISC0 0xcc
85 #define PLLU_MISC1 0xc8
86 #define PLLX_BASE 0xe0
87 #define PLLX_MISC0 0xe4
88 #define PLLX_MISC1 0x510
89 #define PLLX_MISC2 0x514
90 #define PLLX_MISC3 0x518
91 #define PLLX_MISC4 0x5f0
92 #define PLLX_MISC5 0x5f4
93 #define PLLE_BASE 0xe8
94 #define PLLE_MISC0 0xec
95 #define PLLD2_BASE 0x4b8
96 #define PLLD2_MISC0 0x4bc
97 #define PLLD2_MISC1 0x570
98 #define PLLD2_MISC2 0x574
99 #define PLLD2_MISC3 0x578
100 #define PLLE_AUX 0x48c
101 #define PLLRE_BASE 0x4c4
102 #define PLLRE_MISC0 0x4c8
103 #define PLLRE_OUT1 0x4cc
104 #define PLLDP_BASE 0x590
105 #define PLLDP_MISC 0x594
107 #define PLLC4_BASE 0x5a4
108 #define PLLC4_MISC0 0x5a8
109 #define PLLC4_OUT 0x5e4
110 #define PLLMB_BASE 0x5e8
111 #define PLLMB_MISC1 0x5ec
112 #define PLLA1_BASE 0x6a4
113 #define PLLA1_MISC0 0x6a8
114 #define PLLA1_MISC1 0x6ac
115 #define PLLA1_MISC2 0x6b0
116 #define PLLA1_MISC3 0x6b4
118 #define PLLU_IDDQ_BIT 31
119 #define PLLCX_IDDQ_BIT 27
120 #define PLLRE_IDDQ_BIT 24
121 #define PLLA_IDDQ_BIT 25
122 #define PLLD_IDDQ_BIT 20
123 #define PLLSS_IDDQ_BIT 18
124 #define PLLM_IDDQ_BIT 5
125 #define PLLMB_IDDQ_BIT 17
126 #define PLLXP_IDDQ_BIT 3
128 #define PLLCX_RESET_BIT 30
130 #define PLL_BASE_LOCK BIT(27)
131 #define PLLCX_BASE_LOCK BIT(26)
132 #define PLLE_MISC_LOCK BIT(11)
133 #define PLLRE_MISC_LOCK BIT(27)
135 #define PLL_MISC_LOCK_ENABLE 18
136 #define PLLC_MISC_LOCK_ENABLE 24
137 #define PLLDU_MISC_LOCK_ENABLE 22
138 #define PLLU_MISC_LOCK_ENABLE 29
139 #define PLLE_MISC_LOCK_ENABLE 9
140 #define PLLRE_MISC_LOCK_ENABLE 30
141 #define PLLSS_MISC_LOCK_ENABLE 30
142 #define PLLP_MISC_LOCK_ENABLE 18
143 #define PLLM_MISC_LOCK_ENABLE 4
144 #define PLLMB_MISC_LOCK_ENABLE 16
145 #define PLLA_MISC_LOCK_ENABLE 28
146 #define PLLU_MISC_LOCK_ENABLE 29
147 #define PLLD_MISC_LOCK_ENABLE 18
149 #define PLLA_SDM_DIN_MASK 0xffff
150 #define PLLA_SDM_EN_MASK BIT(26)
152 #define PLLD_SDM_EN_MASK BIT(16)
154 #define PLLD2_SDM_EN_MASK BIT(31)
155 #define PLLD2_SSC_EN_MASK 0
157 #define PLLDP_SS_CFG 0x598
158 #define PLLDP_SDM_EN_MASK BIT(31)
159 #define PLLDP_SSC_EN_MASK BIT(30)
160 #define PLLDP_SS_CTRL1 0x59c
161 #define PLLDP_SS_CTRL2 0x5a0
163 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
164 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
166 #define UTMIP_PLL_CFG2 0x488
167 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
168 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
169 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
170 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
171 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
172 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
173 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
174 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
175 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
176 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
178 #define UTMIP_PLL_CFG1 0x484
179 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
180 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
181 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
182 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
183 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
184 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
185 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
187 #define SATA_PLL_CFG0 0x490
188 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
189 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
190 #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4)
191 #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5)
192 #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6)
193 #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7)
195 #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
196 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
198 #define XUSBIO_PLL_CFG0 0x51c
199 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
200 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
201 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
202 #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
203 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
205 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
206 #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31)
207 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
208 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
209 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7)
210 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
211 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
212 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
213 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
214 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
215 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
217 #define PLLU_HW_PWRDN_CFG0 0x530
218 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
219 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
220 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
221 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
222 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
223 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
225 #define XUSB_PLL_CFG0 0x534
226 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
227 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
229 #define SPARE_REG0 0x55c
230 #define CLK_M_DIVISOR_SHIFT 2
231 #define CLK_M_DIVISOR_MASK 0x3
233 #define RST_DFLL_DVCO 0x2f4
234 #define DVFS_DFLL_RESET_SHIFT 0
236 #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
237 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
239 #define LVL2_CLK_GATE_OVRA 0xf8
240 #define LVL2_CLK_GATE_OVRC 0x3a0
241 #define LVL2_CLK_GATE_OVRD 0x3a4
242 #define LVL2_CLK_GATE_OVRE 0x554
244 /* I2S registers to handle during APE MBIST WAR */
245 #define TEGRA210_I2S_BASE 0x1000
246 #define TEGRA210_I2S_SIZE 0x100
247 #define TEGRA210_I2S_CTRLS 5
248 #define TEGRA210_I2S_CG 0x88
249 #define TEGRA210_I2S_CTRL 0xa0
251 /* DISPA registers to handle during MBIST WAR */
252 #define DC_CMD_DISPLAY_COMMAND 0xc8
253 #define DC_COM_DSC_TOP_CTL 0xcf8
255 /* VIC register to handle during MBIST WAR */
256 #define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c
258 /* APE, DISPA and VIC base addesses needed for MBIST WAR */
259 #define TEGRA210_AHUB_BASE 0x702d0000
260 #define TEGRA210_DISPA_BASE 0x54200000
261 #define TEGRA210_VIC_BASE 0x54340000
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
267 * indicate that SDM is disabled.
269 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
271 #define PLL_SDM_COEFF BIT(13)
272 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
273 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
274 /* This macro returns ndiv effective scaled to SDM range */
275 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
276 (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))
278 /* Tegra CPU clock and reset control regs */
279 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
281 #ifdef CONFIG_PM_SLEEP
282 static struct cpu_clk_suspend_context {
284 } tegra210_cpu_clk_sctx;
287 struct tegra210_domain_mbist_war {
288 void (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *mbist);
289 const u32 lvl2_offset;
291 const unsigned int num_clks;
292 const unsigned int *clk_init_data;
293 struct clk_bulk_data *clks;
296 static struct clk **clks;
298 static void __iomem *clk_base;
299 static void __iomem *pmc_base;
300 static void __iomem *ahub_base;
301 static void __iomem *dispa_base;
302 static void __iomem *vic_base;
304 static unsigned long osc_freq;
305 static unsigned long pll_ref_freq;
307 static DEFINE_SPINLOCK(pll_d_lock);
308 static DEFINE_SPINLOCK(pll_e_lock);
309 static DEFINE_SPINLOCK(pll_re_lock);
310 static DEFINE_SPINLOCK(pll_u_lock);
311 static DEFINE_SPINLOCK(sor1_lock);
312 static DEFINE_SPINLOCK(emc_lock);
313 static DEFINE_MUTEX(lvl2_ovr_lock);
315 /* possible OSC frequencies in Hz */
316 static unsigned long tegra210_input_freq[] = {
321 static const char *mux_pllmcp_clkm[] = {
322 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
325 #define mux_pllmcp_clkm_idx NULL
327 #define PLL_ENABLE (1 << 30)
329 #define PLLCX_MISC1_IDDQ (1 << 27)
330 #define PLLCX_MISC0_RESET (1 << 30)
332 #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000
333 #define PLLCX_MISC0_WRITE_MASK 0x400ffffb
334 #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000
335 #define PLLCX_MISC1_WRITE_MASK 0x08003cff
336 #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05
337 #define PLLCX_MISC2_WRITE_MASK 0xffffff17
338 #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4
339 #define PLLCX_MISC3_WRITE_MASK 0x00ffffff
342 #define PLLA_BASE_IDDQ (1 << 25)
343 #define PLLA_BASE_LOCK (1 << 27)
345 #define PLLA_MISC0_LOCK_ENABLE (1 << 28)
346 #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27)
348 #define PLLA_MISC2_EN_SDM (1 << 26)
349 #define PLLA_MISC2_EN_DYNRAMP (1 << 25)
351 #define PLLA_MISC0_DEFAULT_VALUE 0x12000020
352 #define PLLA_MISC0_WRITE_MASK 0x7fffffff
353 #define PLLA_MISC2_DEFAULT_VALUE 0x0
354 #define PLLA_MISC2_WRITE_MASK 0x06ffffff
357 #define PLLD_BASE_CSI_CLKSOURCE (1 << 23)
359 #define PLLD_MISC0_EN_SDM (1 << 16)
360 #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17)
361 #define PLLD_MISC0_LOCK_ENABLE (1 << 18)
362 #define PLLD_MISC0_IDDQ (1 << 20)
363 #define PLLD_MISC0_DSI_CLKENABLE (1 << 21)
365 #define PLLD_MISC0_DEFAULT_VALUE 0x00140000
366 #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff
367 #define PLLD_MISC1_DEFAULT_VALUE 0x20
368 #define PLLD_MISC1_WRITE_MASK 0x00ffffff
370 /* PLLD2 and PLLDP and PLLC4 */
371 #define PLLDSS_BASE_LOCK (1 << 27)
372 #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24)
373 #define PLLDSS_BASE_IDDQ (1 << 18)
374 #define PLLDSS_BASE_REF_SEL_SHIFT 25
375 #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT)
377 #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30)
379 #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31)
380 #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30)
382 #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020
383 #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000
384 #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0
385 #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0
387 #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020
388 #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000
389 #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da
390 #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400
392 #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff
393 #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000
394 #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff
395 #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff
397 #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000
400 #define PLLRE_MISC0_LOCK_ENABLE (1 << 30)
401 #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29)
402 #define PLLRE_MISC0_LOCK (1 << 27)
403 #define PLLRE_MISC0_IDDQ (1 << 24)
405 #define PLLRE_BASE_DEFAULT_VALUE 0x0
406 #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000
408 #define PLLRE_BASE_DEFAULT_MASK 0x1c000000
409 #define PLLRE_MISC0_WRITE_MASK 0x67ffffff
412 #define PLLX_USE_DYN_RAMP 1
413 #define PLLX_BASE_LOCK (1 << 27)
415 #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28)
416 #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18)
418 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
419 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
420 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
421 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
422 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
423 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
424 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
425 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
426 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
428 #define PLLX_MISC3_IDDQ (0x1 << 3)
430 #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE
431 #define PLLX_MISC0_WRITE_MASK 0x10c40000
432 #define PLLX_MISC1_DEFAULT_VALUE 0x20
433 #define PLLX_MISC1_WRITE_MASK 0x00ffffff
434 #define PLLX_MISC2_DEFAULT_VALUE 0x0
435 #define PLLX_MISC2_WRITE_MASK 0xffffff11
436 #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ
437 #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f
438 #define PLLX_MISC4_DEFAULT_VALUE 0x0
439 #define PLLX_MISC4_WRITE_MASK 0x8000ffff
440 #define PLLX_MISC5_DEFAULT_VALUE 0x0
441 #define PLLX_MISC5_WRITE_MASK 0x0000ffff
443 #define PLLX_HW_CTRL_CFG 0x548
444 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
447 #define PLLMB_BASE_LOCK (1 << 27)
449 #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18)
450 #define PLLMB_MISC1_IDDQ (1 << 17)
451 #define PLLMB_MISC1_LOCK_ENABLE (1 << 16)
453 #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000
454 #define PLLMB_MISC1_WRITE_MASK 0x0007ffff
457 #define PLLP_BASE_OVERRIDE (1 << 28)
458 #define PLLP_BASE_LOCK (1 << 27)
460 #define PLLP_MISC0_LOCK_ENABLE (1 << 18)
461 #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17)
462 #define PLLP_MISC0_IDDQ (1 << 3)
464 #define PLLP_MISC1_HSIO_EN_SHIFT 29
465 #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT)
466 #define PLLP_MISC1_XUSB_EN_SHIFT 28
467 #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT)
469 #define PLLP_MISC0_DEFAULT_VALUE 0x00040008
470 #define PLLP_MISC1_DEFAULT_VALUE 0x0
472 #define PLLP_MISC0_WRITE_MASK 0xdc6000f
473 #define PLLP_MISC1_WRITE_MASK 0x70ffffff
476 #define PLLU_BASE_LOCK (1 << 27)
477 #define PLLU_BASE_OVERRIDE (1 << 24)
478 #define PLLU_BASE_CLKENABLE_USB (1 << 21)
479 #define PLLU_BASE_CLKENABLE_HSIC (1 << 22)
480 #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23)
481 #define PLLU_BASE_CLKENABLE_48M (1 << 25)
482 #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\
483 PLLU_BASE_CLKENABLE_HSIC |\
484 PLLU_BASE_CLKENABLE_ICUSB |\
485 PLLU_BASE_CLKENABLE_48M)
487 #define PLLU_MISC0_IDDQ (1 << 31)
488 #define PLLU_MISC0_LOCK_ENABLE (1 << 29)
489 #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0)
491 #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000
492 #define PLLU_MISC1_DEFAULT_VALUE 0x0
494 #define PLLU_MISC0_WRITE_MASK 0xbfffffff
495 #define PLLU_MISC1_WRITE_MASK 0x00000007
497 void tegra210_xusb_pll_hw_control_enable(void)
501 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
502 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
503 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
504 val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
505 XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
506 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
508 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable);
510 void tegra210_xusb_pll_hw_sequence_start(void)
514 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
515 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
516 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
518 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start);
520 void tegra210_sata_pll_hw_control_enable(void)
524 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
525 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
526 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET |
527 SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;
528 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
530 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable);
532 void tegra210_sata_pll_hw_sequence_start(void)
536 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
537 val |= SATA_PLL_CFG0_SEQ_ENABLE;
538 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
540 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start);
542 void tegra210_set_sata_pll_seq_sw(bool state)
546 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
548 val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
549 val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
550 val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
551 val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
553 val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
554 val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
555 val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
556 val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
558 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
560 EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
562 static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist)
566 val = readl_relaxed(clk_base + mbist->lvl2_offset);
567 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset);
568 fence_udelay(1, clk_base);
569 writel_relaxed(val, clk_base + mbist->lvl2_offset);
570 fence_udelay(1, clk_base);
573 static void tegra210_venc_mbist_war(struct tegra210_domain_mbist_war *mbist)
575 u32 csi_src, ovra, ovre;
576 unsigned long flags = 0;
578 spin_lock_irqsave(&pll_d_lock, flags);
580 csi_src = readl_relaxed(clk_base + PLLD_BASE);
581 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);
582 fence_udelay(1, clk_base);
584 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
585 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA);
586 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
587 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE);
588 fence_udelay(1, clk_base);
590 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
591 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
592 writel_relaxed(csi_src, clk_base + PLLD_BASE);
593 fence_udelay(1, clk_base);
595 spin_unlock_irqrestore(&pll_d_lock, flags);
598 static void tegra210_disp_mbist_war(struct tegra210_domain_mbist_war *mbist)
600 u32 ovra, dsc_top_ctrl;
602 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
603 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA);
604 fence_udelay(1, clk_base);
606 dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL);
607 writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL);
608 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
609 writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL);
610 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
612 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
613 fence_udelay(1, clk_base);
616 static void tegra210_vic_mbist_war(struct tegra210_domain_mbist_war *mbist)
620 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
621 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE);
622 fence_udelay(1, clk_base);
624 val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
625 writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24),
626 vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
627 fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
629 writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
630 readl(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
632 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
633 fence_udelay(1, clk_base);
636 static void tegra210_ape_mbist_war(struct tegra210_domain_mbist_war *mbist)
638 void __iomem *i2s_base;
642 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC);
643 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
644 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC);
645 writel_relaxed(ovre | BIT(10) | BIT(11),
646 clk_base + LVL2_CLK_GATE_OVRE);
647 fence_udelay(1, clk_base);
649 i2s_base = ahub_base + TEGRA210_I2S_BASE;
651 for (i = 0; i < TEGRA210_I2S_CTRLS; i++) {
654 i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL);
655 writel_relaxed(i2s_ctrl | BIT(10),
656 i2s_base + TEGRA210_I2S_CTRL);
657 writel_relaxed(0, i2s_base + TEGRA210_I2S_CG);
658 readl(i2s_base + TEGRA210_I2S_CG);
659 writel_relaxed(1, i2s_base + TEGRA210_I2S_CG);
660 writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL);
661 readl(i2s_base + TEGRA210_I2S_CTRL);
663 i2s_base += TEGRA210_I2S_SIZE;
666 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC);
667 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
668 fence_udelay(1, clk_base);
671 static inline void _pll_misc_chk_default(void __iomem *base,
672 struct tegra_clk_pll_params *params,
673 u8 misc_num, u32 default_val, u32 mask)
675 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
679 if (boot_val != default_val) {
680 pr_warn("boot misc%d 0x%x: expected 0x%x\n",
681 misc_num, boot_val, default_val);
682 pr_warn(" (comparison mask = 0x%x)\n", mask);
683 params->defaults_set = false;
688 * PLLCX: PLLC, PLLC2, PLLC3, PLLA1
689 * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition
690 * that changes NDIV only, while PLL is already locked.
692 static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
696 default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET);
697 _pll_misc_chk_default(clk_base, params, 0, default_val,
698 PLLCX_MISC0_WRITE_MASK);
700 default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ);
701 _pll_misc_chk_default(clk_base, params, 1, default_val,
702 PLLCX_MISC1_WRITE_MASK);
704 default_val = PLLCX_MISC2_DEFAULT_VALUE;
705 _pll_misc_chk_default(clk_base, params, 2, default_val,
706 PLLCX_MISC2_WRITE_MASK);
708 default_val = PLLCX_MISC3_DEFAULT_VALUE;
709 _pll_misc_chk_default(clk_base, params, 3, default_val,
710 PLLCX_MISC3_WRITE_MASK);
713 static void tegra210_pllcx_set_defaults(const char *name,
714 struct tegra_clk_pll *pllcx)
716 pllcx->params->defaults_set = true;
718 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
719 /* PLL is ON: only check if defaults already set */
720 pllcx_check_defaults(pllcx->params);
721 if (!pllcx->params->defaults_set)
722 pr_warn("%s already enabled. Postponing set full defaults\n",
727 /* Defaults assert PLL reset, and set IDDQ */
728 writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE,
729 clk_base + pllcx->params->ext_misc_reg[0]);
730 writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE,
731 clk_base + pllcx->params->ext_misc_reg[1]);
732 writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE,
733 clk_base + pllcx->params->ext_misc_reg[2]);
734 writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE,
735 clk_base + pllcx->params->ext_misc_reg[3]);
739 static void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
741 tegra210_pllcx_set_defaults("PLL_C", pllcx);
744 static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
746 tegra210_pllcx_set_defaults("PLL_C2", pllcx);
749 static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
751 tegra210_pllcx_set_defaults("PLL_C3", pllcx);
754 static void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
756 tegra210_pllcx_set_defaults("PLL_A1", pllcx);
761 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
762 * Fractional SDM is allowed to provide exact audio rates.
764 static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
767 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
769 plla->params->defaults_set = true;
771 if (val & PLL_ENABLE) {
773 * PLL is ON: check if defaults already set, then set those
774 * that can be updated in flight.
776 if (val & PLLA_BASE_IDDQ) {
777 pr_warn("PLL_A boot enabled with IDDQ set\n");
778 plla->params->defaults_set = false;
781 pr_warn("PLL_A already enabled. Postponing set full defaults\n");
783 val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */
784 mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE;
785 _pll_misc_chk_default(clk_base, plla->params, 0, val,
786 ~mask & PLLA_MISC0_WRITE_MASK);
788 val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */
789 _pll_misc_chk_default(clk_base, plla->params, 2, val,
790 PLLA_MISC2_EN_DYNRAMP);
792 /* Enable lock detect */
793 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
795 val |= PLLA_MISC0_DEFAULT_VALUE & mask;
796 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
802 /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */
803 val |= PLLA_BASE_IDDQ;
804 writel_relaxed(val, clk_base + plla->params->base_reg);
805 writel_relaxed(PLLA_MISC0_DEFAULT_VALUE,
806 clk_base + plla->params->ext_misc_reg[0]);
807 writel_relaxed(PLLA_MISC2_DEFAULT_VALUE,
808 clk_base + plla->params->ext_misc_reg[2]);
814 * PLL with fractional SDM.
816 static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
821 plld->params->defaults_set = true;
823 if (readl_relaxed(clk_base + plld->params->base_reg) &
827 * PLL is ON: check if defaults already set, then set those
828 * that can be updated in flight.
830 val = PLLD_MISC1_DEFAULT_VALUE;
831 _pll_misc_chk_default(clk_base, plld->params, 1,
832 val, PLLD_MISC1_WRITE_MASK);
834 /* ignore lock, DSI and SDM controls, make sure IDDQ not set */
835 val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ);
836 mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE |
837 PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM;
838 _pll_misc_chk_default(clk_base, plld->params, 0, val,
839 ~mask & PLLD_MISC0_WRITE_MASK);
841 if (!plld->params->defaults_set)
842 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
844 /* Enable lock detect */
845 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
846 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
848 val |= PLLD_MISC0_DEFAULT_VALUE & mask;
849 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
855 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
856 val &= PLLD_MISC0_DSI_CLKENABLE;
857 val |= PLLD_MISC0_DEFAULT_VALUE;
858 /* set IDDQ, enable lock detect, disable SDM */
859 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
860 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
861 plld->params->ext_misc_reg[1]);
867 * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used).
869 static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
870 u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val)
873 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
875 plldss->params->defaults_set = true;
877 if (val & PLL_ENABLE) {
880 * PLL is ON: check if defaults already set, then set those
881 * that can be updated in flight.
883 if (val & PLLDSS_BASE_IDDQ) {
884 pr_warn("plldss boot enabled with IDDQ set\n");
885 plldss->params->defaults_set = false;
888 /* ignore lock enable */
889 default_val = misc0_val;
890 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
891 PLLDSS_MISC0_WRITE_MASK &
892 (~PLLDSS_MISC0_LOCK_ENABLE));
895 * If SSC is used, check all settings, otherwise just confirm
896 * that SSC is not used on boot as well. Do nothing when using
897 * this function for PLLC4 that has only MISC0.
899 if (plldss->params->ssc_ctrl_en_mask) {
900 default_val = misc1_val;
901 _pll_misc_chk_default(clk_base, plldss->params, 1,
902 default_val, PLLDSS_MISC1_CFG_WRITE_MASK);
903 default_val = misc2_val;
904 _pll_misc_chk_default(clk_base, plldss->params, 2,
905 default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK);
906 default_val = misc3_val;
907 _pll_misc_chk_default(clk_base, plldss->params, 3,
908 default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK);
909 } else if (plldss->params->ext_misc_reg[1]) {
910 default_val = misc1_val;
911 _pll_misc_chk_default(clk_base, plldss->params, 1,
912 default_val, PLLDSS_MISC1_CFG_WRITE_MASK &
913 (~PLLDSS_MISC1_CFG_EN_SDM));
916 if (!plldss->params->defaults_set)
917 pr_warn("%s already enabled. Postponing set full defaults\n",
920 /* Enable lock detect */
921 if (val & PLLDSS_BASE_LOCK_OVERRIDE) {
922 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
923 writel_relaxed(val, clk_base +
924 plldss->params->base_reg);
927 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
928 val &= ~PLLDSS_MISC0_LOCK_ENABLE;
929 val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE;
930 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
936 /* set IDDQ, enable lock detect, configure SDM/SSC */
937 val |= PLLDSS_BASE_IDDQ;
938 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
939 writel_relaxed(val, clk_base + plldss->params->base_reg);
941 /* When using this function for PLLC4 exit here */
942 if (!plldss->params->ext_misc_reg[1]) {
943 writel_relaxed(misc0_val, clk_base +
944 plldss->params->ext_misc_reg[0]);
949 writel_relaxed(misc0_val, clk_base +
950 plldss->params->ext_misc_reg[0]);
951 /* if SSC used set by 1st enable */
952 writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC),
953 clk_base + plldss->params->ext_misc_reg[1]);
954 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
955 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
959 static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
961 plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
962 PLLD2_MISC1_CFG_DEFAULT_VALUE,
963 PLLD2_MISC2_CTRL1_DEFAULT_VALUE,
964 PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
967 static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
969 plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
970 PLLDP_MISC1_CFG_DEFAULT_VALUE,
971 PLLDP_MISC2_CTRL1_DEFAULT_VALUE,
972 PLLDP_MISC3_CTRL2_DEFAULT_VALUE);
977 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
978 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
980 static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
982 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
987 * VCO is exposed to the clock tree directly along with post-divider output
989 static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
992 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
994 pllre->params->defaults_set = true;
996 if (val & PLL_ENABLE) {
997 pr_warn("PLL_RE already enabled. Postponing set full defaults\n");
1000 * PLL is ON: check if defaults already set, then set those
1001 * that can be updated in flight.
1003 val &= PLLRE_BASE_DEFAULT_MASK;
1004 if (val != PLLRE_BASE_DEFAULT_VALUE) {
1005 pr_warn("pllre boot base 0x%x : expected 0x%x\n",
1006 val, PLLRE_BASE_DEFAULT_VALUE);
1007 pr_warn("(comparison mask = 0x%x)\n",
1008 PLLRE_BASE_DEFAULT_MASK);
1009 pllre->params->defaults_set = false;
1012 /* Ignore lock enable */
1013 val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ);
1014 mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE;
1015 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
1016 ~mask & PLLRE_MISC0_WRITE_MASK);
1018 /* Enable lock detect */
1019 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
1021 val |= PLLRE_MISC0_DEFAULT_VALUE & mask;
1022 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
1028 /* set IDDQ, enable lock detect */
1029 val &= ~PLLRE_BASE_DEFAULT_MASK;
1030 val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK;
1031 writel_relaxed(val, clk_base + pllre->params->base_reg);
1032 writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE,
1033 clk_base + pllre->params->ext_misc_reg[0]);
1037 static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
1039 unsigned long input_rate;
1042 if (!IS_ERR_OR_NULL(hw->clk))
1043 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1045 input_rate = 38400000;
1047 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
1049 switch (input_rate) {
1065 pr_err("%s: Unexpected reference rate %lu\n",
1066 __func__, input_rate);
1071 static void pllx_check_defaults(struct tegra_clk_pll *pll)
1075 default_val = PLLX_MISC0_DEFAULT_VALUE;
1076 /* ignore lock enable */
1077 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
1078 PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE));
1080 default_val = PLLX_MISC1_DEFAULT_VALUE;
1081 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
1082 PLLX_MISC1_WRITE_MASK);
1084 /* ignore all but control bit */
1085 default_val = PLLX_MISC2_DEFAULT_VALUE;
1086 _pll_misc_chk_default(clk_base, pll->params, 2,
1087 default_val, PLLX_MISC2_EN_DYNRAMP);
1089 default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ);
1090 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
1091 PLLX_MISC3_WRITE_MASK);
1093 default_val = PLLX_MISC4_DEFAULT_VALUE;
1094 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
1095 PLLX_MISC4_WRITE_MASK);
1097 default_val = PLLX_MISC5_DEFAULT_VALUE;
1098 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
1099 PLLX_MISC5_WRITE_MASK);
1102 static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
1107 pllx->params->defaults_set = true;
1109 /* Get ready dyn ramp state machine settings */
1110 pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b);
1111 val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) &
1112 (~PLLX_MISC2_DYNRAMP_STEPB_MASK);
1113 val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
1114 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
1116 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
1119 * PLL is ON: check if defaults already set, then set those
1120 * that can be updated in flight.
1122 pllx_check_defaults(pllx);
1124 if (!pllx->params->defaults_set)
1125 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
1126 /* Configure dyn ramp, disable lock override */
1127 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1129 /* Enable lock detect */
1130 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
1131 val &= ~PLLX_MISC0_LOCK_ENABLE;
1132 val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE;
1133 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
1139 /* Enable lock detect and CPU output */
1140 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
1141 pllx->params->ext_misc_reg[0]);
1144 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
1145 pllx->params->ext_misc_reg[1]);
1147 /* Configure dyn ramp state machine, disable lock override */
1148 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1151 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
1152 pllx->params->ext_misc_reg[3]);
1155 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
1156 pllx->params->ext_misc_reg[4]);
1157 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
1158 pllx->params->ext_misc_reg[5]);
1163 static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
1165 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
1167 pllmb->params->defaults_set = true;
1169 if (val & PLL_ENABLE) {
1172 * PLL is ON: check if defaults already set, then set those
1173 * that can be updated in flight.
1175 val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ);
1176 mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE;
1177 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
1178 ~mask & PLLMB_MISC1_WRITE_MASK);
1180 if (!pllmb->params->defaults_set)
1181 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
1182 /* Enable lock detect */
1183 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
1185 val |= PLLMB_MISC1_DEFAULT_VALUE & mask;
1186 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
1192 /* set IDDQ, enable lock detect */
1193 writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,
1194 clk_base + pllmb->params->ext_misc_reg[0]);
1200 * VCO is exposed to the clock tree directly along with post-divider output.
1201 * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz,
1204 static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
1208 /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */
1209 val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ);
1210 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1212 mask |= PLLP_MISC0_IDDQ;
1213 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1214 ~mask & PLLP_MISC0_WRITE_MASK);
1216 /* Ignore branch controls */
1217 val = PLLP_MISC1_DEFAULT_VALUE;
1218 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1219 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1220 ~mask & PLLP_MISC1_WRITE_MASK);
1223 static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
1226 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
1228 pllp->params->defaults_set = true;
1230 if (val & PLL_ENABLE) {
1233 * PLL is ON: check if defaults already set, then set those
1234 * that can be updated in flight.
1236 pllp_check_defaults(pllp, true);
1237 if (!pllp->params->defaults_set)
1238 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
1240 /* Enable lock detect */
1241 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
1242 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1244 val |= PLLP_MISC0_DEFAULT_VALUE & mask;
1245 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
1251 /* set IDDQ, enable lock detect */
1252 writel_relaxed(PLLP_MISC0_DEFAULT_VALUE,
1253 clk_base + pllp->params->ext_misc_reg[0]);
1255 /* Preserve branch control */
1256 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
1257 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1259 val |= ~mask & PLLP_MISC1_DEFAULT_VALUE;
1260 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1266 * VCO is exposed to the clock tree directly along with post-divider output.
1267 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz,
1270 static void pllu_check_defaults(struct tegra_clk_pll_params *params,
1275 /* Ignore lock enable (will be set) and IDDQ if under h/w control */
1276 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ);
1277 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0);
1278 _pll_misc_chk_default(clk_base, params, 0, val,
1279 ~mask & PLLU_MISC0_WRITE_MASK);
1281 val = PLLU_MISC1_DEFAULT_VALUE;
1282 mask = PLLU_MISC1_LOCK_OVERRIDE;
1283 _pll_misc_chk_default(clk_base, params, 1, val,
1284 ~mask & PLLU_MISC1_WRITE_MASK);
1287 static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu)
1289 u32 val = readl_relaxed(clk_base + pllu->base_reg);
1291 pllu->defaults_set = true;
1293 if (val & PLL_ENABLE) {
1296 * PLL is ON: check if defaults already set, then set those
1297 * that can be updated in flight.
1299 pllu_check_defaults(pllu, false);
1300 if (!pllu->defaults_set)
1301 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1303 /* Enable lock detect */
1304 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);
1305 val &= ~PLLU_MISC0_LOCK_ENABLE;
1306 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE;
1307 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);
1309 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);
1310 val &= ~PLLU_MISC1_LOCK_OVERRIDE;
1311 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE;
1312 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);
1318 /* set IDDQ, enable lock detect */
1319 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,
1320 clk_base + pllu->ext_misc_reg[0]);
1321 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,
1322 clk_base + pllu->ext_misc_reg[1]);
1326 #define mask(w) ((1 << (w)) - 1)
1327 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
1328 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
1329 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1330 mask(p->params->div_nmp->divp_width))
1332 #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1333 #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1334 #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1336 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
1337 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
1338 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1340 #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */
1341 static int tegra210_wait_for_mask(struct tegra_clk_pll *pll,
1347 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
1348 udelay(PLL_LOCKDET_DELAY);
1349 val = readl_relaxed(clk_base + reg);
1350 if ((val & mask) == mask) {
1351 udelay(PLL_LOCKDET_DELAY);
1358 static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx,
1359 struct tegra_clk_pll_freq_table *cfg)
1361 u32 val, base, ndiv_new_mask;
1363 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)
1364 << PLLX_MISC2_NDIV_NEW_SHIFT;
1366 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1367 val &= (~ndiv_new_mask);
1368 val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT;
1369 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1372 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1373 val |= PLLX_MISC2_EN_DYNRAMP;
1374 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1377 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],
1378 PLLX_MISC2_DYNRAMP_DONE);
1380 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1381 (~divn_mask_shifted(pllx));
1382 base |= cfg->n << pllx->params->div_nmp->divn_shift;
1383 writel_relaxed(base, clk_base + pllx->params->base_reg);
1386 val &= ~PLLX_MISC2_EN_DYNRAMP;
1387 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1390 pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n",
1391 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,
1392 cfg->input_rate / cfg->m * cfg->n /
1393 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1399 * Common configuration for PLLs with fixed input divider policy:
1400 * - always set fixed M-value based on the reference rate
1401 * - always set P-value value 1:1 for output rates above VCO minimum, and
1402 * choose minimum necessary P-value for output rates below VCO maximum
1403 * - calculate N-value based on selected M and P
1404 * - calculate SDM_DIN fractional part
1406 static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
1407 struct tegra_clk_pll_freq_table *cfg,
1408 unsigned long rate, unsigned long input_rate)
1410 struct tegra_clk_pll *pll = to_clk_pll(hw);
1411 struct tegra_clk_pll_params *params = pll->params;
1413 unsigned long cf, p_rate;
1419 if (!(params->flags & TEGRA_PLL_VCO_OUT)) {
1420 p = DIV_ROUND_UP(params->vco_min, rate);
1421 p = params->round_p_to_pdiv(p, &pdiv);
1423 p = rate >= params->vco_min ? 1 : -EINVAL;
1429 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);
1432 /* Store P as HW value, as that is what is expected */
1433 cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);
1436 if (p_rate > params->vco_max)
1437 p_rate = params->vco_max;
1438 cf = input_rate / cfg->m;
1439 cfg->n = p_rate / cf;
1442 cfg->output_rate = input_rate;
1443 if (params->sdm_ctrl_reg) {
1444 unsigned long rem = p_rate - cf * cfg->n;
1445 /* If ssc is enabled SDM enabled as well, even for integer n */
1446 if (rem || params->ssc_ctrl_reg) {
1447 u64 s = rem * PLL_SDM_COEFF;
1450 s -= PLL_SDM_COEFF / 2;
1451 cfg->sdm_data = sdin_din_to_data(s);
1453 cfg->output_rate *= sdin_get_n_eff(cfg);
1454 cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;
1456 cfg->output_rate *= cfg->n;
1457 cfg->output_rate /= p * cfg->m;
1460 cfg->input_rate = input_rate;
1466 * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate
1468 * @cfg: struct tegra_clk_pll_freq_table * cfg
1471 * Fvco = Fref * NDIV / MDIV
1473 * For fractional mode:
1474 * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV
1476 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
1478 cfg->n = sdin_get_n_eff(cfg);
1479 cfg->m *= PLL_SDM_COEFF;
1482 static unsigned long
1483 tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
1484 unsigned long parent_rate)
1486 unsigned long vco_min = params->vco_min;
1488 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);
1489 vco_min = min(vco_min, params->vco_min);
1494 static struct div_nmp pllx_nmp = {
1503 * PLL post divider maps - two types: quasi-linear and exponential
1506 #define PLL_QLIN_PDIV_MAX 16
1507 static const struct pdiv_map pll_qlin_pdiv_to_hw[] = {
1508 { .pdiv = 1, .hw_val = 0 },
1509 { .pdiv = 2, .hw_val = 1 },
1510 { .pdiv = 3, .hw_val = 2 },
1511 { .pdiv = 4, .hw_val = 3 },
1512 { .pdiv = 5, .hw_val = 4 },
1513 { .pdiv = 6, .hw_val = 5 },
1514 { .pdiv = 8, .hw_val = 6 },
1515 { .pdiv = 9, .hw_val = 7 },
1516 { .pdiv = 10, .hw_val = 8 },
1517 { .pdiv = 12, .hw_val = 9 },
1518 { .pdiv = 15, .hw_val = 10 },
1519 { .pdiv = 16, .hw_val = 11 },
1520 { .pdiv = 18, .hw_val = 12 },
1521 { .pdiv = 20, .hw_val = 13 },
1522 { .pdiv = 24, .hw_val = 14 },
1523 { .pdiv = 30, .hw_val = 15 },
1524 { .pdiv = 32, .hw_val = 16 },
1527 static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv)
1532 for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) {
1533 if (p <= pll_qlin_pdiv_to_hw[i].pdiv) {
1536 return pll_qlin_pdiv_to_hw[i].pdiv;
1544 #define PLL_EXPO_PDIV_MAX 7
1545 static const struct pdiv_map pll_expo_pdiv_to_hw[] = {
1546 { .pdiv = 1, .hw_val = 0 },
1547 { .pdiv = 2, .hw_val = 1 },
1548 { .pdiv = 4, .hw_val = 2 },
1549 { .pdiv = 8, .hw_val = 3 },
1550 { .pdiv = 16, .hw_val = 4 },
1551 { .pdiv = 32, .hw_val = 5 },
1552 { .pdiv = 64, .hw_val = 6 },
1553 { .pdiv = 128, .hw_val = 7 },
1556 static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
1564 if (i <= PLL_EXPO_PDIV_MAX) {
1573 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
1575 { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */
1576 { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */
1577 { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */
1578 { 0, 0, 0, 0, 0, 0 },
1581 static struct tegra_clk_pll_params pll_x_params = {
1582 .input_min = 12000000,
1583 .input_max = 800000000,
1586 .vco_min = 1350000000,
1587 .vco_max = 3000000000UL,
1588 .base_reg = PLLX_BASE,
1589 .misc_reg = PLLX_MISC0,
1590 .lock_mask = PLL_BASE_LOCK,
1591 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
1593 .ext_misc_reg[0] = PLLX_MISC0,
1594 .ext_misc_reg[1] = PLLX_MISC1,
1595 .ext_misc_reg[2] = PLLX_MISC2,
1596 .ext_misc_reg[3] = PLLX_MISC3,
1597 .ext_misc_reg[4] = PLLX_MISC4,
1598 .ext_misc_reg[5] = PLLX_MISC5,
1599 .iddq_reg = PLLX_MISC3,
1600 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1601 .max_p = PLL_QLIN_PDIV_MAX,
1603 .dyn_ramp_reg = PLLX_MISC2,
1606 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1607 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1608 .div_nmp = &pllx_nmp,
1609 .freq_table = pll_x_freq_table,
1610 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1611 .dyn_ramp = tegra210_pllx_dyn_ramp,
1612 .set_defaults = tegra210_pllx_set_defaults,
1613 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1616 static struct div_nmp pllc_nmp = {
1625 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1626 { 12000000, 510000000, 85, 1, 2, 0 },
1627 { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */
1628 { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */
1629 { 0, 0, 0, 0, 0, 0 },
1632 static struct tegra_clk_pll_params pll_c_params = {
1633 .input_min = 12000000,
1634 .input_max = 700000000,
1637 .vco_min = 600000000,
1638 .vco_max = 1200000000,
1639 .base_reg = PLLC_BASE,
1640 .misc_reg = PLLC_MISC0,
1641 .lock_mask = PLL_BASE_LOCK,
1643 .iddq_reg = PLLC_MISC1,
1644 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1645 .reset_reg = PLLC_MISC0,
1646 .reset_bit_idx = PLLCX_RESET_BIT,
1647 .max_p = PLL_QLIN_PDIV_MAX,
1648 .ext_misc_reg[0] = PLLC_MISC0,
1649 .ext_misc_reg[1] = PLLC_MISC1,
1650 .ext_misc_reg[2] = PLLC_MISC2,
1651 .ext_misc_reg[3] = PLLC_MISC3,
1652 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1653 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1655 .div_nmp = &pllc_nmp,
1656 .freq_table = pll_cx_freq_table,
1657 .flags = TEGRA_PLL_USE_LOCK,
1658 .set_defaults = _pllc_set_defaults,
1659 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1662 static struct div_nmp pllcx_nmp = {
1671 static struct tegra_clk_pll_params pll_c2_params = {
1672 .input_min = 12000000,
1673 .input_max = 700000000,
1676 .vco_min = 600000000,
1677 .vco_max = 1200000000,
1678 .base_reg = PLLC2_BASE,
1679 .misc_reg = PLLC2_MISC0,
1680 .iddq_reg = PLLC2_MISC1,
1681 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1682 .reset_reg = PLLC2_MISC0,
1683 .reset_bit_idx = PLLCX_RESET_BIT,
1684 .lock_mask = PLLCX_BASE_LOCK,
1686 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1687 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1689 .div_nmp = &pllcx_nmp,
1690 .max_p = PLL_QLIN_PDIV_MAX,
1691 .ext_misc_reg[0] = PLLC2_MISC0,
1692 .ext_misc_reg[1] = PLLC2_MISC1,
1693 .ext_misc_reg[2] = PLLC2_MISC2,
1694 .ext_misc_reg[3] = PLLC2_MISC3,
1695 .freq_table = pll_cx_freq_table,
1696 .flags = TEGRA_PLL_USE_LOCK,
1697 .set_defaults = _pllc2_set_defaults,
1698 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1701 static struct tegra_clk_pll_params pll_c3_params = {
1702 .input_min = 12000000,
1703 .input_max = 700000000,
1706 .vco_min = 600000000,
1707 .vco_max = 1200000000,
1708 .base_reg = PLLC3_BASE,
1709 .misc_reg = PLLC3_MISC0,
1710 .lock_mask = PLLCX_BASE_LOCK,
1712 .iddq_reg = PLLC3_MISC1,
1713 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1714 .reset_reg = PLLC3_MISC0,
1715 .reset_bit_idx = PLLCX_RESET_BIT,
1716 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1717 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1719 .div_nmp = &pllcx_nmp,
1720 .max_p = PLL_QLIN_PDIV_MAX,
1721 .ext_misc_reg[0] = PLLC3_MISC0,
1722 .ext_misc_reg[1] = PLLC3_MISC1,
1723 .ext_misc_reg[2] = PLLC3_MISC2,
1724 .ext_misc_reg[3] = PLLC3_MISC3,
1725 .freq_table = pll_cx_freq_table,
1726 .flags = TEGRA_PLL_USE_LOCK,
1727 .set_defaults = _pllc3_set_defaults,
1728 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1731 static struct div_nmp pllss_nmp = {
1740 static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1741 { 12000000, 600000000, 50, 1, 1, 0 },
1742 { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */
1743 { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */
1744 { 0, 0, 0, 0, 0, 0 },
1747 static const struct clk_div_table pll_vco_post_div_table[] = {
1748 { .val = 0, .div = 1 },
1749 { .val = 1, .div = 2 },
1750 { .val = 2, .div = 3 },
1751 { .val = 3, .div = 4 },
1752 { .val = 4, .div = 5 },
1753 { .val = 5, .div = 6 },
1754 { .val = 6, .div = 8 },
1755 { .val = 7, .div = 10 },
1756 { .val = 8, .div = 12 },
1757 { .val = 9, .div = 16 },
1758 { .val = 10, .div = 12 },
1759 { .val = 11, .div = 16 },
1760 { .val = 12, .div = 20 },
1761 { .val = 13, .div = 24 },
1762 { .val = 14, .div = 32 },
1763 { .val = 0, .div = 0 },
1766 static struct tegra_clk_pll_params pll_c4_vco_params = {
1767 .input_min = 9600000,
1768 .input_max = 800000000,
1771 .vco_min = 500000000,
1772 .vco_max = 1080000000,
1773 .base_reg = PLLC4_BASE,
1774 .misc_reg = PLLC4_MISC0,
1775 .lock_mask = PLL_BASE_LOCK,
1777 .max_p = PLL_QLIN_PDIV_MAX,
1778 .ext_misc_reg[0] = PLLC4_MISC0,
1779 .iddq_reg = PLLC4_BASE,
1780 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1781 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1782 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1784 .div_nmp = &pllss_nmp,
1785 .freq_table = pll_c4_vco_freq_table,
1786 .set_defaults = tegra210_pllc4_set_defaults,
1787 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1788 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1791 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1792 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
1793 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
1794 { 38400000, 297600000, 93, 4, 3, 0 },
1795 { 38400000, 400000000, 125, 4, 3, 0 },
1796 { 38400000, 532800000, 111, 4, 2, 0 },
1797 { 38400000, 665600000, 104, 3, 2, 0 },
1798 { 38400000, 800000000, 125, 3, 2, 0 },
1799 { 38400000, 931200000, 97, 4, 1, 0 },
1800 { 38400000, 1065600000, 111, 4, 1, 0 },
1801 { 38400000, 1200000000, 125, 4, 1, 0 },
1802 { 38400000, 1331200000, 104, 3, 1, 0 },
1803 { 38400000, 1459200000, 76, 2, 1, 0 },
1804 { 38400000, 1600000000, 125, 3, 1, 0 },
1805 { 0, 0, 0, 0, 0, 0 },
1808 static struct div_nmp pllm_nmp = {
1811 .override_divm_shift = 0,
1814 .override_divn_shift = 8,
1817 .override_divp_shift = 27,
1820 static struct tegra_clk_pll_params pll_m_params = {
1821 .input_min = 9600000,
1822 .input_max = 500000000,
1825 .vco_min = 800000000,
1826 .vco_max = 1866000000,
1827 .base_reg = PLLM_BASE,
1828 .misc_reg = PLLM_MISC2,
1829 .lock_mask = PLL_BASE_LOCK,
1830 .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,
1832 .iddq_reg = PLLM_MISC2,
1833 .iddq_bit_idx = PLLM_IDDQ_BIT,
1834 .max_p = PLL_QLIN_PDIV_MAX,
1835 .ext_misc_reg[0] = PLLM_MISC2,
1836 .ext_misc_reg[1] = PLLM_MISC1,
1837 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1838 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1839 .div_nmp = &pllm_nmp,
1840 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
1841 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
1842 .freq_table = pll_m_freq_table,
1843 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1844 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1847 static struct tegra_clk_pll_params pll_mb_params = {
1848 .input_min = 9600000,
1849 .input_max = 500000000,
1852 .vco_min = 800000000,
1853 .vco_max = 1866000000,
1854 .base_reg = PLLMB_BASE,
1855 .misc_reg = PLLMB_MISC1,
1856 .lock_mask = PLL_BASE_LOCK,
1858 .iddq_reg = PLLMB_MISC1,
1859 .iddq_bit_idx = PLLMB_IDDQ_BIT,
1860 .max_p = PLL_QLIN_PDIV_MAX,
1861 .ext_misc_reg[0] = PLLMB_MISC1,
1862 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1863 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1864 .div_nmp = &pllm_nmp,
1865 .freq_table = pll_m_freq_table,
1866 .flags = TEGRA_PLL_USE_LOCK,
1867 .set_defaults = tegra210_pllmb_set_defaults,
1868 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1872 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
1873 /* PLLE special case: use cpcon field to store cml divider value */
1874 { 672000000, 100000000, 125, 42, 0, 13 },
1875 { 624000000, 100000000, 125, 39, 0, 13 },
1876 { 336000000, 100000000, 125, 21, 0, 13 },
1877 { 312000000, 100000000, 200, 26, 0, 14 },
1878 { 38400000, 100000000, 125, 2, 0, 14 },
1879 { 12000000, 100000000, 200, 1, 0, 14 },
1880 { 0, 0, 0, 0, 0, 0 },
1883 static struct div_nmp plle_nmp = {
1892 static struct tegra_clk_pll_params pll_e_params = {
1893 .input_min = 12000000,
1894 .input_max = 800000000,
1897 .vco_min = 1600000000,
1898 .vco_max = 2500000000U,
1899 .base_reg = PLLE_BASE,
1900 .misc_reg = PLLE_MISC0,
1901 .aux_reg = PLLE_AUX,
1902 .lock_mask = PLLE_MISC_LOCK,
1903 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
1905 .div_nmp = &plle_nmp,
1906 .freq_table = pll_e_freq_table,
1907 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |
1908 TEGRA_PLL_HAS_LOCK_ENABLE,
1909 .fixed_rate = 100000000,
1910 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1913 static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1914 { 12000000, 672000000, 56, 1, 1, 0 },
1915 { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */
1916 { 38400000, 672000000, 70, 4, 1, 0 },
1917 { 0, 0, 0, 0, 0, 0 },
1920 static struct div_nmp pllre_nmp = {
1929 static struct tegra_clk_pll_params pll_re_vco_params = {
1930 .input_min = 9600000,
1931 .input_max = 800000000,
1934 .vco_min = 350000000,
1935 .vco_max = 700000000,
1936 .base_reg = PLLRE_BASE,
1937 .misc_reg = PLLRE_MISC0,
1938 .lock_mask = PLLRE_MISC_LOCK,
1940 .max_p = PLL_QLIN_PDIV_MAX,
1941 .ext_misc_reg[0] = PLLRE_MISC0,
1942 .iddq_reg = PLLRE_MISC0,
1943 .iddq_bit_idx = PLLRE_IDDQ_BIT,
1944 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1945 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1946 .div_nmp = &pllre_nmp,
1947 .freq_table = pll_re_vco_freq_table,
1948 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT,
1949 .set_defaults = tegra210_pllre_set_defaults,
1950 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1953 static struct div_nmp pllp_nmp = {
1962 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
1963 { 12000000, 408000000, 34, 1, 1, 0 },
1964 { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */
1965 { 0, 0, 0, 0, 0, 0 },
1968 static struct tegra_clk_pll_params pll_p_params = {
1969 .input_min = 9600000,
1970 .input_max = 800000000,
1973 .vco_min = 350000000,
1974 .vco_max = 700000000,
1975 .base_reg = PLLP_BASE,
1976 .misc_reg = PLLP_MISC0,
1977 .lock_mask = PLL_BASE_LOCK,
1979 .iddq_reg = PLLP_MISC0,
1980 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1981 .ext_misc_reg[0] = PLLP_MISC0,
1982 .ext_misc_reg[1] = PLLP_MISC1,
1983 .div_nmp = &pllp_nmp,
1984 .freq_table = pll_p_freq_table,
1985 .fixed_rate = 408000000,
1986 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1987 .set_defaults = tegra210_pllp_set_defaults,
1988 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1991 static struct tegra_clk_pll_params pll_a1_params = {
1992 .input_min = 12000000,
1993 .input_max = 700000000,
1996 .vco_min = 600000000,
1997 .vco_max = 1200000000,
1998 .base_reg = PLLA1_BASE,
1999 .misc_reg = PLLA1_MISC0,
2000 .lock_mask = PLLCX_BASE_LOCK,
2002 .iddq_reg = PLLA1_MISC1,
2003 .iddq_bit_idx = PLLCX_IDDQ_BIT,
2004 .reset_reg = PLLA1_MISC0,
2005 .reset_bit_idx = PLLCX_RESET_BIT,
2006 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2007 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2008 .div_nmp = &pllc_nmp,
2009 .ext_misc_reg[0] = PLLA1_MISC0,
2010 .ext_misc_reg[1] = PLLA1_MISC1,
2011 .ext_misc_reg[2] = PLLA1_MISC2,
2012 .ext_misc_reg[3] = PLLA1_MISC3,
2013 .freq_table = pll_cx_freq_table,
2014 .flags = TEGRA_PLL_USE_LOCK,
2015 .set_defaults = _plla1_set_defaults,
2016 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2019 static struct div_nmp plla_nmp = {
2028 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
2029 { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */
2030 { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */
2031 { 12000000, 240000000, 60, 1, 3, 1, 0 },
2032 { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */
2033 { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */
2034 { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */
2035 { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */
2036 { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */
2037 { 38400000, 240000000, 75, 3, 3, 1, 0 },
2038 { 0, 0, 0, 0, 0, 0, 0 },
2041 static struct tegra_clk_pll_params pll_a_params = {
2042 .input_min = 12000000,
2043 .input_max = 800000000,
2046 .vco_min = 500000000,
2047 .vco_max = 1000000000,
2048 .base_reg = PLLA_BASE,
2049 .misc_reg = PLLA_MISC0,
2050 .lock_mask = PLL_BASE_LOCK,
2052 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2053 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2054 .iddq_reg = PLLA_BASE,
2055 .iddq_bit_idx = PLLA_IDDQ_BIT,
2056 .div_nmp = &plla_nmp,
2057 .sdm_din_reg = PLLA_MISC1,
2058 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2059 .sdm_ctrl_reg = PLLA_MISC2,
2060 .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK,
2061 .ext_misc_reg[0] = PLLA_MISC0,
2062 .ext_misc_reg[1] = PLLA_MISC1,
2063 .ext_misc_reg[2] = PLLA_MISC2,
2064 .freq_table = pll_a_freq_table,
2065 .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW,
2066 .set_defaults = tegra210_plla_set_defaults,
2067 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2068 .set_gain = tegra210_clk_pll_set_gain,
2069 .adjust_vco = tegra210_clk_adjust_vco_min,
2072 static struct div_nmp plld_nmp = {
2081 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
2082 { 12000000, 594000000, 99, 1, 2, 0, 0 },
2083 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2084 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2085 { 0, 0, 0, 0, 0, 0, 0 },
2088 static struct tegra_clk_pll_params pll_d_params = {
2089 .input_min = 12000000,
2090 .input_max = 800000000,
2093 .vco_min = 750000000,
2094 .vco_max = 1500000000,
2095 .base_reg = PLLD_BASE,
2096 .misc_reg = PLLD_MISC0,
2097 .lock_mask = PLL_BASE_LOCK,
2099 .iddq_reg = PLLD_MISC0,
2100 .iddq_bit_idx = PLLD_IDDQ_BIT,
2101 .round_p_to_pdiv = pll_expo_p_to_pdiv,
2102 .pdiv_tohw = pll_expo_pdiv_to_hw,
2103 .div_nmp = &plld_nmp,
2104 .sdm_din_reg = PLLD_MISC0,
2105 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2106 .sdm_ctrl_reg = PLLD_MISC0,
2107 .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK,
2108 .ext_misc_reg[0] = PLLD_MISC0,
2109 .ext_misc_reg[1] = PLLD_MISC1,
2110 .freq_table = pll_d_freq_table,
2111 .flags = TEGRA_PLL_USE_LOCK,
2113 .set_defaults = tegra210_plld_set_defaults,
2114 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2115 .set_gain = tegra210_clk_pll_set_gain,
2116 .adjust_vco = tegra210_clk_adjust_vco_min,
2119 static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
2120 { 12000000, 594000000, 99, 1, 2, 0, 0xf000 },
2121 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2122 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2123 { 0, 0, 0, 0, 0, 0, 0 },
2126 /* s/w policy, always tegra_pll_ref */
2127 static struct tegra_clk_pll_params pll_d2_params = {
2128 .input_min = 12000000,
2129 .input_max = 800000000,
2132 .vco_min = 750000000,
2133 .vco_max = 1500000000,
2134 .base_reg = PLLD2_BASE,
2135 .misc_reg = PLLD2_MISC0,
2136 .lock_mask = PLL_BASE_LOCK,
2138 .iddq_reg = PLLD2_BASE,
2139 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2140 .sdm_din_reg = PLLD2_MISC3,
2141 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2142 .sdm_ctrl_reg = PLLD2_MISC1,
2143 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
2144 /* disable spread-spectrum for pll_d2 */
2146 .ssc_ctrl_en_mask = 0,
2147 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2148 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2149 .div_nmp = &pllss_nmp,
2150 .ext_misc_reg[0] = PLLD2_MISC0,
2151 .ext_misc_reg[1] = PLLD2_MISC1,
2152 .ext_misc_reg[2] = PLLD2_MISC2,
2153 .ext_misc_reg[3] = PLLD2_MISC3,
2154 .max_p = PLL_QLIN_PDIV_MAX,
2156 .freq_table = tegra210_pll_d2_freq_table,
2157 .set_defaults = tegra210_plld2_set_defaults,
2158 .flags = TEGRA_PLL_USE_LOCK,
2159 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2160 .set_gain = tegra210_clk_pll_set_gain,
2161 .adjust_vco = tegra210_clk_adjust_vco_min,
2164 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
2165 { 12000000, 270000000, 90, 1, 4, 0, 0xf000 },
2166 { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */
2167 { 38400000, 270000000, 28, 1, 4, 0, 0xf400 },
2168 { 0, 0, 0, 0, 0, 0, 0 },
2171 static struct tegra_clk_pll_params pll_dp_params = {
2172 .input_min = 12000000,
2173 .input_max = 800000000,
2176 .vco_min = 750000000,
2177 .vco_max = 1500000000,
2178 .base_reg = PLLDP_BASE,
2179 .misc_reg = PLLDP_MISC,
2180 .lock_mask = PLL_BASE_LOCK,
2182 .iddq_reg = PLLDP_BASE,
2183 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2184 .sdm_din_reg = PLLDP_SS_CTRL2,
2185 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2186 .sdm_ctrl_reg = PLLDP_SS_CFG,
2187 .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK,
2188 .ssc_ctrl_reg = PLLDP_SS_CFG,
2189 .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK,
2190 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2191 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2192 .div_nmp = &pllss_nmp,
2193 .ext_misc_reg[0] = PLLDP_MISC,
2194 .ext_misc_reg[1] = PLLDP_SS_CFG,
2195 .ext_misc_reg[2] = PLLDP_SS_CTRL1,
2196 .ext_misc_reg[3] = PLLDP_SS_CTRL2,
2197 .max_p = PLL_QLIN_PDIV_MAX,
2199 .freq_table = pll_dp_freq_table,
2200 .set_defaults = tegra210_plldp_set_defaults,
2201 .flags = TEGRA_PLL_USE_LOCK,
2202 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2203 .set_gain = tegra210_clk_pll_set_gain,
2204 .adjust_vco = tegra210_clk_adjust_vco_min,
2207 static struct div_nmp pllu_nmp = {
2216 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
2217 { 12000000, 480000000, 40, 1, 1, 0 },
2218 { 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */
2219 { 38400000, 480000000, 25, 2, 1, 0 },
2220 { 0, 0, 0, 0, 0, 0 },
2223 static struct tegra_clk_pll_params pll_u_vco_params = {
2224 .input_min = 9600000,
2225 .input_max = 800000000,
2228 .vco_min = 350000000,
2229 .vco_max = 700000000,
2230 .base_reg = PLLU_BASE,
2231 .misc_reg = PLLU_MISC0,
2232 .lock_mask = PLL_BASE_LOCK,
2234 .iddq_reg = PLLU_MISC0,
2235 .iddq_bit_idx = PLLU_IDDQ_BIT,
2236 .ext_misc_reg[0] = PLLU_MISC0,
2237 .ext_misc_reg[1] = PLLU_MISC1,
2238 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2239 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2240 .div_nmp = &pllu_nmp,
2241 .freq_table = pll_u_freq_table,
2242 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
2245 struct utmi_clk_param {
2246 /* Oscillator Frequency in KHz */
2248 /* UTMIP PLL Enable Delay Count */
2249 u8 enable_delay_count;
2250 /* UTMIP PLL Stable count */
2252 /* UTMIP PLL Active delay count */
2253 u8 active_delay_count;
2254 /* UTMIP PLL Xtal frequency count */
2255 u16 xtal_freq_count;
2258 static const struct utmi_clk_param utmi_parameters[] = {
2260 .osc_frequency = 38400000, .enable_delay_count = 0x0,
2261 .stable_count = 0x0, .active_delay_count = 0x6,
2262 .xtal_freq_count = 0x80
2264 .osc_frequency = 13000000, .enable_delay_count = 0x02,
2265 .stable_count = 0x33, .active_delay_count = 0x05,
2266 .xtal_freq_count = 0x7f
2268 .osc_frequency = 19200000, .enable_delay_count = 0x03,
2269 .stable_count = 0x4b, .active_delay_count = 0x06,
2270 .xtal_freq_count = 0xbb
2272 .osc_frequency = 12000000, .enable_delay_count = 0x02,
2273 .stable_count = 0x2f, .active_delay_count = 0x08,
2274 .xtal_freq_count = 0x76
2276 .osc_frequency = 26000000, .enable_delay_count = 0x04,
2277 .stable_count = 0x66, .active_delay_count = 0x09,
2278 .xtal_freq_count = 0xfe
2280 .osc_frequency = 16800000, .enable_delay_count = 0x03,
2281 .stable_count = 0x41, .active_delay_count = 0x0a,
2282 .xtal_freq_count = 0xa4
2286 static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2287 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },
2288 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
2289 [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
2290 [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
2291 [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
2292 [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
2293 [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
2294 [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
2295 [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
2296 [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
2297 [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true },
2298 [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true },
2299 [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true },
2300 [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true },
2301 [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true },
2302 [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true },
2303 [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true },
2304 [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true },
2305 [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true },
2306 [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true },
2307 [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true },
2308 [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true },
2309 [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true },
2310 [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true },
2311 [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true },
2312 [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true },
2313 [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true },
2314 [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true },
2315 [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true },
2316 [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true },
2317 [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true },
2318 [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true },
2319 [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true },
2320 [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true },
2321 [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true },
2322 [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true },
2323 [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true },
2324 [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true },
2325 [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true },
2326 [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true },
2327 [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true },
2328 [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true },
2329 [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true },
2330 [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true },
2331 [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true },
2332 [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true },
2333 [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true },
2334 [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true },
2335 [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true },
2336 [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true },
2337 [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true },
2338 [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true },
2339 [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true },
2340 [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true },
2341 [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true },
2342 [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true },
2343 [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true },
2344 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true },
2345 [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true },
2346 [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true },
2347 [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true },
2348 [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true },
2349 [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true },
2350 [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true },
2351 [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true },
2352 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },
2353 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },
2354 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },
2355 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },
2356 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
2357 [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
2358 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
2359 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
2360 [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
2361 [tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true },
2362 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
2363 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
2364 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
2365 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
2366 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
2367 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
2368 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },
2369 [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true },
2370 [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
2371 [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
2372 [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
2373 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
2374 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
2375 [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
2376 [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
2377 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
2378 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
2379 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
2380 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
2381 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2382 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
2383 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
2384 [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true },
2385 [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true },
2386 [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true },
2387 [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true },
2388 [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true },
2389 [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true },
2390 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true },
2391 [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true },
2392 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true },
2393 [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true },
2394 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true },
2395 [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true },
2396 [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true },
2397 [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true },
2398 [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true },
2399 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true },
2400 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true },
2401 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true },
2402 [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true },
2403 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true },
2404 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true },
2405 [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true },
2406 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true },
2407 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true },
2408 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true },
2409 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true },
2410 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true },
2411 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true },
2412 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true },
2413 [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true },
2414 [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true },
2415 [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true },
2416 [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
2417 [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
2418 [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
2419 [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
2420 [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
2421 [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
2422 [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
2423 [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
2424 [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
2425 [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
2426 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true },
2427 [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true },
2428 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true },
2429 [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true },
2430 [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true },
2431 [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true },
2432 [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true },
2433 [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true },
2434 [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true },
2435 [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true },
2436 [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true },
2437 [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true },
2438 [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true },
2439 [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true },
2440 [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true },
2441 [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true },
2442 [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true },
2443 [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true },
2444 [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true },
2445 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true },
2446 [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true },
2447 [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true },
2448 [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true },
2449 [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true },
2450 [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true },
2451 [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
2452 [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
2453 [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
2454 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
2455 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
2456 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
2457 [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
2458 [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
2459 [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
2460 [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true },
2461 [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true },
2462 [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true },
2463 [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true },
2464 [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true },
2465 [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true },
2466 [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true },
2467 [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true },
2468 [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true },
2469 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },
2470 [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
2471 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
2472 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
2473 [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
2474 [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
2475 [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
2476 [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
2477 [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true },
2478 [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },
2479 [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },
2480 [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
2481 [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
2482 [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
2483 [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
2484 [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
2485 [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
2486 [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true },
2487 [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true },
2488 [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true },
2489 [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true },
2490 [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true },
2491 [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true },
2492 [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true },
2495 static struct tegra_devclk devclks[] __initdata = {
2496 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2497 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2498 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2499 { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
2500 { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
2501 { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
2502 { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
2503 { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
2504 { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 },
2505 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
2506 { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 },
2507 { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 },
2508 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
2509 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
2510 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
2511 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
2512 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
2513 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
2514 { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT },
2515 { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 },
2516 { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 },
2517 { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M },
2518 { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M },
2519 { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M },
2520 { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D },
2521 { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 },
2522 { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 },
2523 { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 },
2524 { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A },
2525 { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },
2526 { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO },
2527 { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT },
2528 { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC },
2529 { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC },
2530 { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC },
2531 { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC },
2532 { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC },
2533 { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC },
2534 { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC },
2535 { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 },
2536 { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 },
2537 { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 },
2538 { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 },
2539 { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
2540 { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
2541 { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
2542 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
2543 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
2544 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
2545 { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
2546 { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
2547 { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
2548 { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
2549 { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK },
2550 { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK },
2551 { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE },
2552 { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC },
2553 { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER },
2554 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },
2555 { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 },
2556 { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 },
2557 { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 },
2558 { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },
2559 { .con_id = "sor0", .dt_id = TEGRA210_CLK_SOR0 },
2562 static struct tegra_audio_clk_info tegra210_audio_plls[] = {
2563 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" },
2564 { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" },
2567 static const char * const aclk_parents[] = {
2568 "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",
2572 static const unsigned int nvjpg_slcg_clkids[] = { TEGRA210_CLK_NVDEC };
2573 static const unsigned int nvdec_slcg_clkids[] = { TEGRA210_CLK_NVJPG };
2574 static const unsigned int sor_slcg_clkids[] = { TEGRA210_CLK_HDA2CODEC_2X,
2575 TEGRA210_CLK_HDA2HDMI, TEGRA210_CLK_DISP1, TEGRA210_CLK_DISP2 };
2576 static const unsigned int disp_slcg_clkids[] = { TEGRA210_CLK_LA,
2577 TEGRA210_CLK_HOST1X};
2578 static const unsigned int xusba_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2579 TEGRA210_CLK_XUSB_DEV };
2580 static const unsigned int xusbb_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2581 TEGRA210_CLK_XUSB_SS };
2582 static const unsigned int xusbc_slcg_clkids[] = { TEGRA210_CLK_XUSB_DEV,
2583 TEGRA210_CLK_XUSB_SS };
2584 static const unsigned int venc_slcg_clkids[] = { TEGRA210_CLK_HOST1X,
2585 TEGRA210_CLK_PLL_D };
2586 static const unsigned int ape_slcg_clkids[] = { TEGRA210_CLK_ACLK,
2587 TEGRA210_CLK_I2S0, TEGRA210_CLK_I2S1, TEGRA210_CLK_I2S2,
2588 TEGRA210_CLK_I2S3, TEGRA210_CLK_I2S4, TEGRA210_CLK_SPDIF_OUT,
2589 TEGRA210_CLK_D_AUDIO };
2590 static const unsigned int vic_slcg_clkids[] = { TEGRA210_CLK_HOST1X };
2592 static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
2593 [TEGRA_POWERGATE_VENC] = {
2594 .handle_lvl2_ovr = tegra210_venc_mbist_war,
2595 .num_clks = ARRAY_SIZE(venc_slcg_clkids),
2596 .clk_init_data = venc_slcg_clkids,
2598 [TEGRA_POWERGATE_SATA] = {
2599 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2600 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2601 .lvl2_mask = BIT(0) | BIT(17) | BIT(19),
2603 [TEGRA_POWERGATE_MPE] = {
2604 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2605 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2606 .lvl2_mask = BIT(29),
2608 [TEGRA_POWERGATE_SOR] = {
2609 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2610 .num_clks = ARRAY_SIZE(sor_slcg_clkids),
2611 .clk_init_data = sor_slcg_clkids,
2612 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2613 .lvl2_mask = BIT(1) | BIT(2),
2615 [TEGRA_POWERGATE_DIS] = {
2616 .handle_lvl2_ovr = tegra210_disp_mbist_war,
2617 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2618 .clk_init_data = disp_slcg_clkids,
2620 [TEGRA_POWERGATE_DISB] = {
2621 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2622 .clk_init_data = disp_slcg_clkids,
2623 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2624 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2625 .lvl2_mask = BIT(2),
2627 [TEGRA_POWERGATE_XUSBA] = {
2628 .num_clks = ARRAY_SIZE(xusba_slcg_clkids),
2629 .clk_init_data = xusba_slcg_clkids,
2630 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2631 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2632 .lvl2_mask = BIT(30) | BIT(31),
2634 [TEGRA_POWERGATE_XUSBB] = {
2635 .num_clks = ARRAY_SIZE(xusbb_slcg_clkids),
2636 .clk_init_data = xusbb_slcg_clkids,
2637 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2638 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2639 .lvl2_mask = BIT(30) | BIT(31),
2641 [TEGRA_POWERGATE_XUSBC] = {
2642 .num_clks = ARRAY_SIZE(xusbc_slcg_clkids),
2643 .clk_init_data = xusbc_slcg_clkids,
2644 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2645 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2646 .lvl2_mask = BIT(30) | BIT(31),
2648 [TEGRA_POWERGATE_VIC] = {
2649 .num_clks = ARRAY_SIZE(vic_slcg_clkids),
2650 .clk_init_data = vic_slcg_clkids,
2651 .handle_lvl2_ovr = tegra210_vic_mbist_war,
2653 [TEGRA_POWERGATE_NVDEC] = {
2654 .num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
2655 .clk_init_data = nvdec_slcg_clkids,
2656 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2657 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2658 .lvl2_mask = BIT(9) | BIT(31),
2660 [TEGRA_POWERGATE_NVJPG] = {
2661 .num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
2662 .clk_init_data = nvjpg_slcg_clkids,
2663 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2664 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2665 .lvl2_mask = BIT(9) | BIT(31),
2667 [TEGRA_POWERGATE_AUD] = {
2668 .num_clks = ARRAY_SIZE(ape_slcg_clkids),
2669 .clk_init_data = ape_slcg_clkids,
2670 .handle_lvl2_ovr = tegra210_ape_mbist_war,
2672 [TEGRA_POWERGATE_VE2] = {
2673 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2674 .lvl2_offset = LVL2_CLK_GATE_OVRD,
2675 .lvl2_mask = BIT(22),
2679 int tegra210_clk_handle_mbist_war(unsigned int id)
2682 struct tegra210_domain_mbist_war *mbist_war;
2684 if (id >= ARRAY_SIZE(tegra210_pg_mbist_war)) {
2685 WARN(1, "unknown domain id in MBIST WAR handler\n");
2689 mbist_war = &tegra210_pg_mbist_war[id];
2690 if (!mbist_war->handle_lvl2_ovr)
2693 if (mbist_war->num_clks && !mbist_war->clks)
2696 err = clk_bulk_prepare_enable(mbist_war->num_clks, mbist_war->clks);
2700 mutex_lock(&lvl2_ovr_lock);
2702 mbist_war->handle_lvl2_ovr(mbist_war);
2704 mutex_unlock(&lvl2_ovr_lock);
2706 clk_bulk_disable_unprepare(mbist_war->num_clks, mbist_war->clks);
2711 void tegra210_put_utmipll_in_iddq(void)
2715 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2717 if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) {
2718 pr_err("trying to assert IDDQ while UTMIPLL is locked\n");
2722 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2723 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2725 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq);
2727 void tegra210_put_utmipll_out_iddq(void)
2731 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2732 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2733 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2735 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq);
2737 static void tegra210_utmi_param_configure(void)
2742 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2743 if (osc_freq == utmi_parameters[i].osc_frequency)
2747 if (i >= ARRAY_SIZE(utmi_parameters)) {
2748 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
2753 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2754 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2755 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2759 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2761 /* Program UTMIP PLL stable and active counts */
2762 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2763 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2764 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
2766 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2768 UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count);
2769 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2771 /* Program UTMIP PLL delay and oscillator frequency counts */
2772 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2774 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2776 UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count);
2778 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2780 UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count);
2782 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2783 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2785 /* Remove power downs from UTMIP PLL control bits */
2786 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2787 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2788 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2789 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2793 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2794 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2795 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2796 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2797 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2798 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2799 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2800 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2801 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2803 /* Setup HW control of UTMIPLL */
2804 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2805 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2806 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2807 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2809 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2810 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2811 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2812 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2816 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2817 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2818 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2822 /* Enable HW control UTMIPLL */
2823 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2824 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2825 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2828 static int tegra210_enable_pllu(void)
2830 struct tegra_clk_pll_freq_table *fentry;
2831 struct tegra_clk_pll pllu;
2834 for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
2835 if (fentry->input_rate == pll_ref_freq)
2839 if (!fentry->input_rate) {
2840 pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq);
2844 /* clear IDDQ bit */
2845 pllu.params = &pll_u_vco_params;
2846 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2847 reg &= ~BIT(pllu.params->iddq_bit_idx);
2848 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
2851 reg = readl_relaxed(clk_base + PLLU_BASE);
2852 reg &= ~GENMASK(20, 0);
2854 reg |= fentry->n << 8;
2855 reg |= fentry->p << 16;
2856 writel(reg, clk_base + PLLU_BASE);
2859 writel(reg, clk_base + PLLU_BASE);
2861 readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
2862 reg & PLL_BASE_LOCK, 2, 1000);
2863 if (!(reg & PLL_BASE_LOCK)) {
2864 pr_err("Timed out waiting for PLL_U to lock\n");
2871 static int tegra210_init_pllu(void)
2876 tegra210_pllu_set_defaults(&pll_u_vco_params);
2877 /* skip initialization when pllu is in hw controlled mode */
2878 reg = readl_relaxed(clk_base + PLLU_BASE);
2879 if (reg & PLLU_BASE_OVERRIDE) {
2880 if (!(reg & PLL_ENABLE)) {
2881 err = tegra210_enable_pllu();
2887 /* enable hw controlled mode */
2888 reg = readl_relaxed(clk_base + PLLU_BASE);
2889 reg &= ~PLLU_BASE_OVERRIDE;
2890 writel(reg, clk_base + PLLU_BASE);
2892 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2893 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2894 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2895 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2896 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2897 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2898 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2900 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2901 reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK;
2902 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2905 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2906 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2907 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2910 reg = readl_relaxed(clk_base + PLLU_BASE);
2911 reg &= ~PLLU_BASE_CLKENABLE_USB;
2912 writel_relaxed(reg, clk_base + PLLU_BASE);
2915 /* enable UTMIPLL hw control if not yet done by the bootloader */
2916 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2917 if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE))
2918 tegra210_utmi_param_configure();
2923 static const char * const sor1_out_parents[] = {
2925 * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so
2926 * the sor1_pad_clkout parent appears twice in the list below. This is
2927 * merely to support clk_get_parent() if firmware happened to set
2928 * these bits to 0b11. While not an invalid setting, code should
2929 * always set the bits to 0b01 to select sor1_pad_clkout.
2931 "sor_safe", "sor1_pad_clkout", "sor1", "sor1_pad_clkout",
2934 static const char * const sor1_parents[] = {
2935 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m",
2938 static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };
2940 static struct tegra_periph_init_data tegra210_periph[] = {
2941 TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents,
2942 CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1,
2943 TEGRA_DIVIDER_ROUND_UP, 183, 0, tegra_clk_sor1,
2944 sor1_parents_idx, 0, &sor1_lock),
2947 static const char * const la_parents[] = {
2948 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0"
2951 static struct tegra_clk_periph tegra210_la =
2952 TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, 0);
2954 static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2955 void __iomem *pmc_base)
2961 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
2963 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
2965 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
2967 clks[TEGRA210_CLK_SOR_SAFE] = clk;
2969 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
2971 clks[TEGRA210_CLK_DPAUX] = clk;
2973 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
2975 clks[TEGRA210_CLK_DPAUX1] = clk;
2977 clk = clk_register_mux_table(NULL, "sor1_out", sor1_out_parents,
2978 ARRAY_SIZE(sor1_out_parents), 0,
2979 clk_base + CLK_SOURCE_SOR1, 14, 0x3,
2980 0, NULL, &sor1_lock);
2981 clks[TEGRA210_CLK_SOR1_OUT] = clk;
2984 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
2985 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
2986 clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;
2989 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
2991 periph_clk_enb_refcnt);
2992 clks[TEGRA210_CLK_DSIA] = clk;
2995 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
2997 periph_clk_enb_refcnt);
2998 clks[TEGRA210_CLK_DSIB] = clk;
3001 clk = tegra_clk_register_periph("la", la_parents,
3002 ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
3004 clks[TEGRA210_CLK_LA] = clk;
3007 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
3008 ARRAY_SIZE(mux_pllmcp_clkm), 0,
3009 clk_base + CLK_SOURCE_EMC,
3010 29, 3, 0, &emc_lock);
3012 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
3014 clks[TEGRA210_CLK_MC] = clk;
3017 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
3019 clk_register_clkdev(clk, "cml0", NULL);
3020 clks[TEGRA210_CLK_CML0] = clk;
3023 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
3025 clk_register_clkdev(clk, "cml1", NULL);
3026 clks[TEGRA210_CLK_CML1] = clk;
3028 clk = tegra_clk_register_super_clk("aclk", aclk_parents,
3029 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
3031 clks[TEGRA210_CLK_ACLK] = clk;
3033 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
3034 CLK_SOURCE_SDMMC2, 9,
3035 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3036 clks[TEGRA210_CLK_SDMMC2] = clk;
3038 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
3039 CLK_SOURCE_SDMMC4, 15,
3040 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3041 clks[TEGRA210_CLK_SDMMC4] = clk;
3043 for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
3044 struct tegra_periph_init_data *init = &tegra210_periph[i];
3047 clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks);
3049 pr_warn("clock %u not found\n", init->clk_id);
3053 clk = tegra_clk_register_periph_data(clk_base, init);
3057 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
3060 static void __init tegra210_pll_init(void __iomem *clk_base,
3066 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,
3067 pmc, 0, &pll_c_params, NULL);
3068 if (!WARN_ON(IS_ERR(clk)))
3069 clk_register_clkdev(clk, "pll_c", NULL);
3070 clks[TEGRA210_CLK_PLL_C] = clk;
3073 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
3074 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3076 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
3077 clk_base + PLLC_OUT, 1, 0,
3078 CLK_SET_RATE_PARENT, 0, NULL);
3079 clk_register_clkdev(clk, "pll_c_out1", NULL);
3080 clks[TEGRA210_CLK_PLL_C_OUT1] = clk;
3083 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
3084 CLK_SET_RATE_PARENT, 1, 1);
3085 clk_register_clkdev(clk, "pll_c_ud", NULL);
3086 clks[TEGRA210_CLK_PLL_C_UD] = clk;
3089 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
3090 pmc, 0, &pll_c2_params, NULL);
3091 clk_register_clkdev(clk, "pll_c2", NULL);
3092 clks[TEGRA210_CLK_PLL_C2] = clk;
3095 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
3096 pmc, 0, &pll_c3_params, NULL);
3097 clk_register_clkdev(clk, "pll_c3", NULL);
3098 clks[TEGRA210_CLK_PLL_C3] = clk;
3101 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
3102 CLK_SET_RATE_GATE, &pll_m_params, NULL);
3103 clk_register_clkdev(clk, "pll_m", NULL);
3104 clks[TEGRA210_CLK_PLL_M] = clk;
3107 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
3108 CLK_SET_RATE_GATE, &pll_mb_params, NULL);
3109 clk_register_clkdev(clk, "pll_mb", NULL);
3110 clks[TEGRA210_CLK_PLL_MB] = clk;
3113 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
3114 CLK_SET_RATE_PARENT, 1, 1);
3115 clk_register_clkdev(clk, "pll_m_ud", NULL);
3116 clks[TEGRA210_CLK_PLL_M_UD] = clk;
3119 if (!tegra210_init_pllu()) {
3120 clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,
3122 clk_register_clkdev(clk, "pll_u_vco", NULL);
3123 clks[TEGRA210_CLK_PLL_U] = clk;
3127 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,
3128 clk_base + PLLU_BASE, 16, 4, 0,
3129 pll_vco_post_div_table, NULL);
3130 clk_register_clkdev(clk, "pll_u_out", NULL);
3131 clks[TEGRA210_CLK_PLL_U_OUT] = clk;
3134 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",
3135 clk_base + PLLU_OUTA, 0,
3136 TEGRA_DIVIDER_ROUND_UP,
3137 8, 8, 1, &pll_u_lock);
3138 clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",
3139 clk_base + PLLU_OUTA, 1, 0,
3140 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3141 clk_register_clkdev(clk, "pll_u_out1", NULL);
3142 clks[TEGRA210_CLK_PLL_U_OUT1] = clk;
3145 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",
3146 clk_base + PLLU_OUTA, 0,
3147 TEGRA_DIVIDER_ROUND_UP,
3148 24, 8, 1, &pll_u_lock);
3149 clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",
3150 clk_base + PLLU_OUTA, 17, 16,
3151 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3152 clk_register_clkdev(clk, "pll_u_out2", NULL);
3153 clks[TEGRA210_CLK_PLL_U_OUT2] = clk;
3156 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",
3157 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3158 22, 0, &pll_u_lock);
3159 clk_register_clkdev(clk, "pll_u_480M", NULL);
3160 clks[TEGRA210_CLK_PLL_U_480M] = clk;
3163 clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
3164 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3165 23, 0, &pll_u_lock);
3166 clk_register_clkdev(clk, "pll_u_60M", NULL);
3167 clks[TEGRA210_CLK_PLL_U_60M] = clk;
3170 clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
3171 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3172 25, 0, &pll_u_lock);
3173 clk_register_clkdev(clk, "pll_u_48M", NULL);
3174 clks[TEGRA210_CLK_PLL_U_48M] = clk;
3177 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
3178 &pll_d_params, &pll_d_lock);
3179 clk_register_clkdev(clk, "pll_d", NULL);
3180 clks[TEGRA210_CLK_PLL_D] = clk;
3183 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
3184 CLK_SET_RATE_PARENT, 1, 2);
3185 clk_register_clkdev(clk, "pll_d_out0", NULL);
3186 clks[TEGRA210_CLK_PLL_D_OUT0] = clk;
3189 clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref",
3192 &pll_re_lock, pll_ref_freq);
3193 clk_register_clkdev(clk, "pll_re_vco", NULL);
3194 clks[TEGRA210_CLK_PLL_RE_VCO] = clk;
3196 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
3197 clk_base + PLLRE_BASE, 16, 5, 0,
3198 pll_vco_post_div_table, &pll_re_lock);
3199 clk_register_clkdev(clk, "pll_re_out", NULL);
3200 clks[TEGRA210_CLK_PLL_RE_OUT] = clk;
3202 clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco",
3203 clk_base + PLLRE_OUT1, 0,
3204 TEGRA_DIVIDER_ROUND_UP,
3206 clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div",
3207 clk_base + PLLRE_OUT1, 1, 0,
3208 CLK_SET_RATE_PARENT, 0, NULL);
3209 clks[TEGRA210_CLK_PLL_RE_OUT1] = clk;
3212 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref",
3213 clk_base, 0, &pll_e_params, NULL);
3214 clk_register_clkdev(clk, "pll_e", NULL);
3215 clks[TEGRA210_CLK_PLL_E] = clk;
3218 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
3219 0, &pll_c4_vco_params, NULL, pll_ref_freq);
3220 clk_register_clkdev(clk, "pll_c4_vco", NULL);
3221 clks[TEGRA210_CLK_PLL_C4] = clk;
3224 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0,
3225 clk_base + PLLC4_BASE, 19, 4, 0,
3226 pll_vco_post_div_table, NULL);
3227 clk_register_clkdev(clk, "pll_c4_out0", NULL);
3228 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk;
3231 clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",
3232 CLK_SET_RATE_PARENT, 1, 3);
3233 clk_register_clkdev(clk, "pll_c4_out1", NULL);
3234 clks[TEGRA210_CLK_PLL_C4_OUT1] = clk;
3237 clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",
3238 CLK_SET_RATE_PARENT, 1, 5);
3239 clk_register_clkdev(clk, "pll_c4_out2", NULL);
3240 clks[TEGRA210_CLK_PLL_C4_OUT2] = clk;
3243 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",
3244 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3246 clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",
3247 clk_base + PLLC4_OUT, 1, 0,
3248 CLK_SET_RATE_PARENT, 0, NULL);
3249 clk_register_clkdev(clk, "pll_c4_out3", NULL);
3250 clks[TEGRA210_CLK_PLL_C4_OUT3] = clk;
3253 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
3254 0, &pll_dp_params, NULL);
3255 clk_register_clkdev(clk, "pll_dp", NULL);
3256 clks[TEGRA210_CLK_PLL_DP] = clk;
3259 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
3260 0, &pll_d2_params, NULL);
3261 clk_register_clkdev(clk, "pll_d2", NULL);
3262 clks[TEGRA210_CLK_PLL_D2] = clk;
3265 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
3266 CLK_SET_RATE_PARENT, 1, 1);
3267 clk_register_clkdev(clk, "pll_d2_out0", NULL);
3268 clks[TEGRA210_CLK_PLL_D2_OUT0] = clk;
3271 clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",
3272 CLK_SET_RATE_PARENT, 1, 2);
3273 clk_register_clkdev(clk, "pll_p_out2", NULL);
3274 clks[TEGRA210_CLK_PLL_P_OUT2] = clk;
3278 /* Tegra210 CPU clock and reset control functions */
3279 static void tegra210_wait_cpu_in_reset(u32 cpu)
3284 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
3286 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
3289 static void tegra210_disable_cpu_clock(u32 cpu)
3291 /* flow controller would take care in the power sequence. */
3294 #ifdef CONFIG_PM_SLEEP
3295 static void tegra210_cpu_clock_suspend(void)
3297 /* switch coresite to clk_m, save off original source */
3298 tegra210_cpu_clk_sctx.clk_csite_src =
3299 readl(clk_base + CLK_SOURCE_CSITE);
3300 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
3303 static void tegra210_cpu_clock_resume(void)
3305 writel(tegra210_cpu_clk_sctx.clk_csite_src,
3306 clk_base + CLK_SOURCE_CSITE);
3310 static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
3311 .wait_for_reset = tegra210_wait_cpu_in_reset,
3312 .disable_clock = tegra210_disable_cpu_clock,
3313 #ifdef CONFIG_PM_SLEEP
3314 .suspend = tegra210_cpu_clock_suspend,
3315 .resume = tegra210_cpu_clock_resume,
3319 static const struct of_device_id pmc_match[] __initconst = {
3320 { .compatible = "nvidia,tegra210-pmc" },
3324 static struct tegra_clk_init_table init_table[] __initdata = {
3325 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
3326 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
3327 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
3328 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
3329 { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
3330 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
3331 { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
3332 { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
3333 { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
3334 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3335 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3336 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3337 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3338 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3339 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
3340 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
3341 { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 },
3342 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
3343 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
3344 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
3345 { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
3346 { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
3347 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3348 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
3349 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
3350 { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3351 { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3352 { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 },
3353 { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3354 { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3355 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
3356 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
3357 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
3358 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3359 /* TODO find a way to enable this on-demand */
3360 { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
3361 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
3362 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
3363 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
3364 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
3365 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3366 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3367 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3368 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
3369 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
3370 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
3371 { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
3372 { TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3373 { TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3374 { TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3375 { TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3376 { TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3377 { TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3378 { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3379 { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
3380 { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
3381 /* This MUST be the last entry. */
3382 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
3386 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs
3388 * Program an initial clock rate and enable or disable clocks needed
3389 * by the rest of the kernel, for Tegra210 SoCs. It is intended to be
3390 * called by assigning a pointer to it to tegra_clk_apply_init_table -
3391 * this will be called as an arch_initcall. No return value.
3393 static void __init tegra210_clock_apply_init_table(void)
3395 tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX);
3399 * tegra210_car_barrier - wait for pending writes to the CAR to complete
3401 * Wait for any outstanding writes to the CAR MMIO space from this CPU
3402 * to complete before continuing execution. No return value.
3404 static void tegra210_car_barrier(void)
3406 readl_relaxed(clk_base + RST_DFLL_DVCO);
3410 * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
3412 * Assert the reset line of the DFLL's DVCO. No return value.
3414 static void tegra210_clock_assert_dfll_dvco_reset(void)
3418 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3419 v |= (1 << DVFS_DFLL_RESET_SHIFT);
3420 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3421 tegra210_car_barrier();
3425 * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
3427 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
3428 * operate. No return value.
3430 static void tegra210_clock_deassert_dfll_dvco_reset(void)
3434 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3435 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
3436 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3437 tegra210_car_barrier();
3440 static int tegra210_reset_assert(unsigned long id)
3442 if (id == TEGRA210_RST_DFLL_DVCO)
3443 tegra210_clock_assert_dfll_dvco_reset();
3444 else if (id == TEGRA210_RST_ADSP)
3445 writel(GENMASK(26, 21) | BIT(7),
3446 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET);
3453 static int tegra210_reset_deassert(unsigned long id)
3455 if (id == TEGRA210_RST_DFLL_DVCO)
3456 tegra210_clock_deassert_dfll_dvco_reset();
3457 else if (id == TEGRA210_RST_ADSP) {
3458 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3460 * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz)
3461 * a delay of 5us ensures that it's at least
3462 * 6 * adsp_cpu_cycle_period long.
3465 writel(GENMASK(26, 22) | BIT(7),
3466 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3473 static void tegra210_mbist_clk_init(void)
3477 for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) {
3478 unsigned int num_clks = tegra210_pg_mbist_war[i].num_clks;
3479 struct clk_bulk_data *clk_data;
3484 clk_data = kmalloc_array(num_clks, sizeof(*clk_data),
3486 if (WARN_ON(!clk_data))
3489 tegra210_pg_mbist_war[i].clks = clk_data;
3490 for (j = 0; j < num_clks; j++) {
3491 int clk_id = tegra210_pg_mbist_war[i].clk_init_data[j];
3492 struct clk *clk = clks[clk_id];
3494 if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) {
3496 tegra210_pg_mbist_war[i].clks = NULL;
3499 clk_data[j].clk = clk;
3505 * tegra210_clock_init - Tegra210-specific clock initialization
3506 * @np: struct device_node * of the DT node for the SoC CAR IP block
3508 * Register most SoC clocks for the Tegra210 system-on-chip. Intended
3509 * to be called by the OF init code when a DT node with the
3510 * "nvidia,tegra210-car" string is encountered, and declared with
3511 * CLK_OF_DECLARE. No return value.
3513 static void __init tegra210_clock_init(struct device_node *np)
3515 struct device_node *node;
3516 u32 value, clk_m_div;
3518 clk_base = of_iomap(np, 0);
3520 pr_err("ioremap tegra210 CAR failed\n");
3524 node = of_find_matching_node(NULL, pmc_match);
3526 pr_err("Failed to find pmc node\n");
3531 pmc_base = of_iomap(node, 0);
3534 pr_err("Can't map pmc registers\n");
3539 ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K);
3541 pr_err("ioremap tegra210 APE failed\n");
3545 dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K);
3547 pr_err("ioremap tegra210 DISPA failed\n");
3551 vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K);
3553 pr_err("ioremap tegra210 VIC failed\n");
3557 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,
3558 TEGRA210_CAR_BANK_COUNT);
3562 value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
3563 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
3565 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
3566 ARRAY_SIZE(tegra210_input_freq), clk_m_div,
3567 &osc_freq, &pll_ref_freq) < 0)
3570 tegra_fixed_clk_init(tegra210_clks);
3571 tegra210_pll_init(clk_base, pmc_base);
3572 tegra210_periph_clk_init(clk_base, pmc_base);
3573 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
3574 tegra210_audio_plls,
3575 ARRAY_SIZE(tegra210_audio_plls), 24576000);
3576 tegra_pmc_clk_init(pmc_base, tegra210_clks);
3578 /* For Tegra210, PLLD is the only source for DSIA & DSIB */
3579 value = clk_readl(clk_base + PLLD_BASE);
3581 clk_writel(value, clk_base + PLLD_BASE);
3583 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
3585 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,
3587 tegra_init_special_resets(2, tegra210_reset_assert,
3588 tegra210_reset_deassert);
3590 tegra_add_of_provider(np, of_clk_src_onecell_get);
3591 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
3593 tegra210_mbist_clk_init();
3595 tegra_cpu_car_ops = &tegra210_cpu_car_ops;
3597 CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);