1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on drivers/clk/tegra/clk-emc.c
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
6 * Author: Dmitry Osipenko <digetx@gmail.com>
7 * Copyright (C) 2019 GRATE-DRIVER project
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
12 #include <linux/bits.h>
13 #include <linux/clk-provider.h>
14 #include <linux/clk/tegra.h>
15 #include <linux/err.h>
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
22 #define CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK GENMASK(7, 0)
23 #define CLK_SOURCE_EMC_2X_CLK_SRC_MASK GENMASK(31, 30)
24 #define CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT 30
26 #define MC_EMC_SAME_FREQ BIT(16)
27 #define USE_PLLM_UD BIT(29)
29 #define EMC_SRC_PLL_M 0
30 #define EMC_SRC_PLL_C 1
31 #define EMC_SRC_PLL_P 2
32 #define EMC_SRC_CLK_M 3
34 static const char * const emc_parent_clk_names[] = {
35 "pll_m", "pll_c", "pll_p", "clk_m",
38 struct tegra_clk_emc {
44 tegra20_clk_emc_round_cb *round_cb;
48 static inline struct tegra_clk_emc *to_tegra_clk_emc(struct clk_hw *hw)
50 return container_of(hw, struct tegra_clk_emc, hw);
53 static unsigned long emc_recalc_rate(struct clk_hw *hw,
54 unsigned long parent_rate)
56 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
59 val = readl_relaxed(emc->reg);
60 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
62 return DIV_ROUND_UP(parent_rate * 2, div + 2);
65 static u8 emc_get_parent(struct clk_hw *hw)
67 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
69 return readl_relaxed(emc->reg) >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
72 static int emc_set_parent(struct clk_hw *hw, u8 index)
74 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
77 val = readl_relaxed(emc->reg);
78 val &= ~CLK_SOURCE_EMC_2X_CLK_SRC_MASK;
79 val |= index << CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
81 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
83 if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter)
88 if (emc->mc_same_freq)
89 val |= MC_EMC_SAME_FREQ;
91 val &= ~MC_EMC_SAME_FREQ;
93 writel_relaxed(val, emc->reg);
95 fence_udelay(1, emc->reg);
100 static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
101 unsigned long parent_rate)
103 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
107 div = div_frac_get(rate, parent_rate, 8, 1, 0);
109 val = readl_relaxed(emc->reg);
110 val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
113 index = val >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
115 if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter)
120 if (emc->mc_same_freq)
121 val |= MC_EMC_SAME_FREQ;
123 val &= ~MC_EMC_SAME_FREQ;
125 writel_relaxed(val, emc->reg);
127 fence_udelay(1, emc->reg);
132 static int emc_set_rate_and_parent(struct clk_hw *hw,
134 unsigned long parent_rate,
137 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
140 div = div_frac_get(rate, parent_rate, 8, 1, 0);
142 val = readl_relaxed(emc->reg);
144 val &= ~CLK_SOURCE_EMC_2X_CLK_SRC_MASK;
145 val |= index << CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
147 val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
150 if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter)
155 if (emc->mc_same_freq)
156 val |= MC_EMC_SAME_FREQ;
158 val &= ~MC_EMC_SAME_FREQ;
160 writel_relaxed(val, emc->reg);
162 fence_udelay(1, emc->reg);
167 static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
169 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
170 struct clk_hw *parent_hw;
171 unsigned long divided_rate;
172 unsigned long parent_rate;
177 emc_rate = emc->round_cb(req->rate, req->min_rate, req->max_rate,
182 for (i = 0; i < ARRAY_SIZE(emc_parent_clk_names); i++) {
183 parent_hw = clk_hw_get_parent_by_index(hw, i);
185 if (req->best_parent_hw == parent_hw)
186 parent_rate = req->best_parent_rate;
188 parent_rate = clk_hw_get_rate(parent_hw);
190 if (emc_rate > parent_rate)
193 div = div_frac_get(emc_rate, parent_rate, 8, 1, 0);
194 divided_rate = DIV_ROUND_UP(parent_rate * 2, div + 2);
196 if (divided_rate != emc_rate)
199 req->best_parent_rate = parent_rate;
200 req->best_parent_hw = parent_hw;
201 req->rate = emc_rate;
205 if (i == ARRAY_SIZE(emc_parent_clk_names)) {
206 pr_err_once("can't find parent for rate %lu emc_rate %lu\n",
207 req->rate, emc_rate);
214 static const struct clk_ops tegra_clk_emc_ops = {
215 .recalc_rate = emc_recalc_rate,
216 .get_parent = emc_get_parent,
217 .set_parent = emc_set_parent,
218 .set_rate = emc_set_rate,
219 .set_rate_and_parent = emc_set_rate_and_parent,
220 .determine_rate = emc_determine_rate,
223 void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
226 struct clk *clk = __clk_lookup("emc");
227 struct tegra_clk_emc *emc;
231 hw = __clk_get_hw(clk);
232 emc = to_tegra_clk_emc(hw);
234 emc->round_cb = round_cb;
235 emc->cb_arg = cb_arg;
239 bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw)
241 return to_tegra_clk_emc(emc_hw)->round_cb != NULL;
244 struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter)
246 struct tegra_clk_emc *emc;
247 struct clk_init_data init;
250 emc = kzalloc(sizeof(*emc), GFP_KERNEL);
255 * EMC stands for External Memory Controller.
257 * We don't want EMC clock to be disabled ever by gating its
258 * parent and whatnot because system is busted immediately in that
259 * case, hence the clock is marked as critical.
262 init.ops = &tegra_clk_emc_ops;
263 init.flags = CLK_IS_CRITICAL;
264 init.parent_names = emc_parent_clk_names;
265 init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
268 emc->hw.init = &init;
269 emc->want_low_jitter = low_jitter;
271 clk = clk_register(NULL, &emc->hw);
280 int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same)
282 struct tegra_clk_emc *emc;
288 hw = __clk_get_hw(emc_clk);
289 emc = to_tegra_clk_emc(hw);
290 emc->mc_same_freq = same;