1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
5 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
8 * Mikko Perttunen <mperttunen@nvidia.com>
11 #include <linux/clk-provider.h>
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/platform_device.h>
20 #include <linux/sort.h>
21 #include <linux/string.h>
23 #include <soc/tegra/fuse.h>
24 #include <soc/tegra/emc.h>
28 #define CLK_SOURCE_EMC 0x19c
30 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
31 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
32 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
33 CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)
35 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
36 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
37 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \
38 CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
40 static const char * const emc_parent_clk_names[] = {
41 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
42 "pll_c2", "pll_c3", "pll_c_ud"
46 * List of clock sources for various parents the EMC clock can have.
47 * When we change the timing to a timing with a parent that has the same
48 * clock source as the current parent, we must first change to a backup
49 * timing that has a different clock source.
52 #define EMC_SRC_PLL_M 0
53 #define EMC_SRC_PLL_C 1
54 #define EMC_SRC_PLL_P 2
55 #define EMC_SRC_CLK_M 3
56 #define EMC_SRC_PLL_C2 4
57 #define EMC_SRC_PLL_C3 5
59 static const char emc_parent_clk_sources[] = {
60 EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M,
61 EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C
65 unsigned long rate, parent_rate;
71 struct tegra_clk_emc {
73 void __iomem *clk_regs;
74 struct clk *prev_parent;
77 struct device_node *emc_node;
78 struct tegra_emc *emc;
81 struct emc_timing *timings;
85 /* Common clock framework callback implementations */
87 static unsigned long emc_recalc_rate(struct clk_hw *hw,
88 unsigned long parent_rate)
90 struct tegra_clk_emc *tegra;
93 tegra = container_of(hw, struct tegra_clk_emc, hw);
96 * CCF wrongly assumes that the parent won't change during set_rate,
97 * so get the parent rate explicitly.
99 parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
101 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
102 div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;
104 return parent_rate / (div + 2) * 2;
108 * Rounds up unless no higher rate exists, in which case down. This way is
109 * safer since things have EMC rate floors. Also don't touch parent_rate
110 * since we don't want the CCF to play with our parent clocks.
112 static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
114 struct tegra_clk_emc *tegra;
115 u8 ram_code = tegra_read_ram_code();
116 struct emc_timing *timing = NULL;
119 tegra = container_of(hw, struct tegra_clk_emc, hw);
121 for (k = 0; k < tegra->num_timings; k++) {
122 if (tegra->timings[k].ram_code == ram_code)
126 for (t = k; t < tegra->num_timings; t++) {
127 if (tegra->timings[t].ram_code != ram_code)
131 for (i = k; i < t; i++) {
132 timing = tegra->timings + i;
134 if (timing->rate < req->rate && i != t - 1)
137 if (timing->rate > req->max_rate) {
139 req->rate = tegra->timings[i - 1].rate;
143 if (timing->rate < req->min_rate)
146 req->rate = timing->rate;
151 req->rate = timing->rate;
155 req->rate = clk_hw_get_rate(hw);
159 static u8 emc_get_parent(struct clk_hw *hw)
161 struct tegra_clk_emc *tegra;
164 tegra = container_of(hw, struct tegra_clk_emc, hw);
166 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
168 return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
169 & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
172 static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
174 struct platform_device *pdev;
179 if (!tegra->emc_node)
182 pdev = of_find_device_by_node(tegra->emc_node);
184 pr_err("%s: could not get external memory controller\n",
189 of_node_put(tegra->emc_node);
190 tegra->emc_node = NULL;
192 tegra->emc = platform_get_drvdata(pdev);
194 put_device(&pdev->dev);
195 pr_err("%s: cannot find EMC driver\n", __func__);
202 static int emc_set_timing(struct tegra_clk_emc *tegra,
203 struct emc_timing *timing)
208 unsigned long flags = 0;
209 struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
214 pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
215 timing->parent_rate, __clk_get_name(timing->parent));
217 if (emc_get_parent(&tegra->hw) == timing->parent_index &&
218 clk_get_rate(timing->parent) != timing->parent_rate) {
219 WARN_ONCE(1, "parent %s rate mismatch %lu %lu\n",
220 __clk_get_name(timing->parent),
221 clk_get_rate(timing->parent),
222 timing->parent_rate);
226 tegra->changing_timing = true;
228 err = clk_set_rate(timing->parent, timing->parent_rate);
230 pr_err("cannot change parent %s rate to %ld: %d\n",
231 __clk_get_name(timing->parent), timing->parent_rate,
237 err = clk_prepare_enable(timing->parent);
239 pr_err("cannot enable parent clock: %d\n", err);
243 div = timing->parent_rate / (timing->rate / 2) - 2;
245 err = tegra_emc_prepare_timing_change(emc, timing->rate);
249 spin_lock_irqsave(tegra->lock, flags);
251 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
253 car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
254 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
256 car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
257 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);
259 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
261 spin_unlock_irqrestore(tegra->lock, flags);
263 tegra_emc_complete_timing_change(emc, timing->rate);
265 clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
266 clk_disable_unprepare(tegra->prev_parent);
268 tegra->prev_parent = timing->parent;
269 tegra->changing_timing = false;
275 * Get backup timing to use as an intermediate step when a change between
276 * two timings with the same clock source has been requested. First try to
277 * find a timing with a higher clock rate to avoid a rate below any set rate
278 * floors. If that is not possible, find a lower rate.
280 static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,
284 u32 ram_code = tegra_read_ram_code();
285 struct emc_timing *timing;
287 for (i = timing_index+1; i < tegra->num_timings; i++) {
288 timing = tegra->timings + i;
289 if (timing->ram_code != ram_code)
292 if (emc_parent_clk_sources[timing->parent_index] !=
293 emc_parent_clk_sources[
294 tegra->timings[timing_index].parent_index])
298 for (i = timing_index-1; i >= 0; --i) {
299 timing = tegra->timings + i;
300 if (timing->ram_code != ram_code)
303 if (emc_parent_clk_sources[timing->parent_index] !=
304 emc_parent_clk_sources[
305 tegra->timings[timing_index].parent_index])
312 static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
313 unsigned long parent_rate)
315 struct tegra_clk_emc *tegra;
316 struct emc_timing *timing = NULL;
318 u32 ram_code = tegra_read_ram_code();
320 tegra = container_of(hw, struct tegra_clk_emc, hw);
322 if (clk_hw_get_rate(hw) == rate)
326 * When emc_set_timing changes the parent rate, CCF will propagate
327 * that downward to us, so ignore any set_rate calls while a rate
328 * change is already going on.
330 if (tegra->changing_timing)
333 for (i = 0; i < tegra->num_timings; i++) {
334 if (tegra->timings[i].rate == rate &&
335 tegra->timings[i].ram_code == ram_code) {
336 timing = tegra->timings + i;
342 pr_err("cannot switch to rate %ld without emc table\n", rate);
346 if (emc_parent_clk_sources[emc_get_parent(hw)] ==
347 emc_parent_clk_sources[timing->parent_index] &&
348 clk_get_rate(timing->parent) != timing->parent_rate) {
350 * Parent clock source not changed but parent rate has changed,
351 * need to temporarily switch to another parent
354 struct emc_timing *backup_timing;
356 backup_timing = get_backup_timing(tegra, i);
357 if (!backup_timing) {
358 pr_err("cannot find backup timing\n");
362 pr_debug("using %ld as backup rate when going to %ld\n",
363 backup_timing->rate, rate);
365 err = emc_set_timing(tegra, backup_timing);
367 pr_err("cannot set backup timing: %d\n", err);
372 return emc_set_timing(tegra, timing);
375 /* Initialization and deinitialization */
377 static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
378 struct emc_timing *timing,
379 struct device_node *node)
384 err = of_property_read_u32(node, "clock-frequency", &tmp);
386 pr_err("timing %pOF: failed to read rate\n", node);
392 err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
394 pr_err("timing %pOF: failed to read parent rate\n", node);
398 timing->parent_rate = tmp;
400 timing->parent = of_clk_get_by_name(node, "emc-parent");
401 if (IS_ERR(timing->parent)) {
402 pr_err("timing %pOF: failed to get parent clock\n", node);
403 return PTR_ERR(timing->parent);
406 timing->parent_index = 0xff;
407 i = match_string(emc_parent_clk_names, ARRAY_SIZE(emc_parent_clk_names),
408 __clk_get_name(timing->parent));
410 pr_err("timing %pOF: %s is not a valid parent\n",
411 node, __clk_get_name(timing->parent));
412 clk_put(timing->parent);
416 timing->parent_index = i;
420 static int cmp_timings(const void *_a, const void *_b)
422 const struct emc_timing *a = _a;
423 const struct emc_timing *b = _b;
425 if (a->rate < b->rate)
427 else if (a->rate == b->rate)
433 static int load_timings_from_dt(struct tegra_clk_emc *tegra,
434 struct device_node *node,
437 struct emc_timing *timings_ptr;
438 struct device_node *child;
439 int child_count = of_get_child_count(node);
443 size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);
445 tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);
449 timings_ptr = tegra->timings + tegra->num_timings;
450 tegra->num_timings += child_count;
452 for_each_child_of_node(node, child) {
453 struct emc_timing *timing = timings_ptr + (i++);
455 err = load_one_timing_from_dt(tegra, timing, child);
458 kfree(tegra->timings);
462 timing->ram_code = ram_code;
465 sort(timings_ptr, child_count, sizeof(struct emc_timing),
471 static const struct clk_ops tegra_clk_emc_ops = {
472 .recalc_rate = emc_recalc_rate,
473 .determine_rate = emc_determine_rate,
474 .set_rate = emc_set_rate,
475 .get_parent = emc_get_parent,
478 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
481 struct tegra_clk_emc *tegra;
482 struct clk_init_data init;
483 struct device_node *node;
488 tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
490 return ERR_PTR(-ENOMEM);
492 tegra->clk_regs = base;
495 tegra->num_timings = 0;
497 for_each_child_of_node(np, node) {
498 err = of_property_read_u32(node, "nvidia,ram-code",
504 * Store timings for all ram codes as we cannot read the
505 * fuses until the apbmisc driver is loaded.
507 err = load_timings_from_dt(tegra, node, node_ram_code);
515 if (tegra->num_timings == 0)
516 pr_warn("%s: no memory timings registered\n", __func__);
518 tegra->emc_node = of_parse_phandle(np,
519 "nvidia,external-memory-controller", 0);
520 if (!tegra->emc_node)
521 pr_warn("%s: couldn't find node for EMC driver\n", __func__);
524 init.ops = &tegra_clk_emc_ops;
525 init.flags = CLK_IS_CRITICAL;
526 init.parent_names = emc_parent_clk_names;
527 init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
529 tegra->hw.init = &init;
531 clk = clk_register(NULL, &tegra->hw);
535 tegra->prev_parent = clk_hw_get_parent_by_index(
536 &tegra->hw, emc_get_parent(&tegra->hw))->clk;
537 tegra->changing_timing = false;
539 /* Allow debugging tools to see the EMC clock */
540 clk_register_clkdev(clk, "emc", "tegra-clk-debug");